clk_rk3328.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <bitfield.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <syscon.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk3328.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <asm/arch-rockchip/grf_rk3328.h>
  17. #include <asm/io.h>
  18. #include <dm/device-internal.h>
  19. #include <dm/lists.h>
  20. #include <dt-bindings/clock/rk3328-cru.h>
  21. #include <linux/bitops.h>
  22. #include <linux/delay.h>
  23. struct pll_div {
  24. u32 refdiv;
  25. u32 fbdiv;
  26. u32 postdiv1;
  27. u32 postdiv2;
  28. u32 frac;
  29. };
  30. #define RATE_TO_DIV(input_rate, output_rate) \
  31. ((input_rate) / (output_rate) - 1);
  32. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  33. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  34. .refdiv = _refdiv,\
  35. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  36. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  37. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1);
  38. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
  39. static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
  40. static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
  41. static const struct pll_div *apll_cfgs[] = {
  42. [APLL_816_MHZ] = &apll_816_cfg,
  43. [APLL_600_MHZ] = &apll_600_cfg,
  44. };
  45. enum {
  46. /* PLL_CON0 */
  47. PLL_POSTDIV1_SHIFT = 12,
  48. PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT,
  49. PLL_FBDIV_SHIFT = 0,
  50. PLL_FBDIV_MASK = 0xfff,
  51. /* PLL_CON1 */
  52. PLL_DSMPD_SHIFT = 12,
  53. PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
  54. PLL_INTEGER_MODE = 1,
  55. PLL_LOCK_STATUS_SHIFT = 10,
  56. PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
  57. PLL_POSTDIV2_SHIFT = 6,
  58. PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT,
  59. PLL_REFDIV_SHIFT = 0,
  60. PLL_REFDIV_MASK = 0x3f,
  61. /* PLL_CON2 */
  62. PLL_FRACDIV_SHIFT = 0,
  63. PLL_FRACDIV_MASK = 0xffffff,
  64. /* MODE_CON */
  65. APLL_MODE_SHIFT = 0,
  66. NPLL_MODE_SHIFT = 1,
  67. DPLL_MODE_SHIFT = 4,
  68. CPLL_MODE_SHIFT = 8,
  69. GPLL_MODE_SHIFT = 12,
  70. PLL_MODE_SLOW = 0,
  71. PLL_MODE_NORM,
  72. /* CLKSEL_CON0 */
  73. CLK_CORE_PLL_SEL_APLL = 0,
  74. CLK_CORE_PLL_SEL_GPLL,
  75. CLK_CORE_PLL_SEL_DPLL,
  76. CLK_CORE_PLL_SEL_NPLL,
  77. CLK_CORE_PLL_SEL_SHIFT = 6,
  78. CLK_CORE_PLL_SEL_MASK = 3 << CLK_CORE_PLL_SEL_SHIFT,
  79. CLK_CORE_DIV_SHIFT = 0,
  80. CLK_CORE_DIV_MASK = 0x1f,
  81. /* CLKSEL_CON1 */
  82. ACLKM_CORE_DIV_SHIFT = 4,
  83. ACLKM_CORE_DIV_MASK = 0x7 << ACLKM_CORE_DIV_SHIFT,
  84. PCLK_DBG_DIV_SHIFT = 0,
  85. PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
  86. /* CLKSEL_CON27 */
  87. GMAC2IO_PLL_SEL_SHIFT = 7,
  88. GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
  89. GMAC2IO_PLL_SEL_CPLL = 0,
  90. GMAC2IO_PLL_SEL_GPLL = 1,
  91. GMAC2IO_CLK_DIV_MASK = 0x1f,
  92. GMAC2IO_CLK_DIV_SHIFT = 0,
  93. /* CLKSEL_CON28 */
  94. ACLK_PERIHP_PLL_SEL_CPLL = 0,
  95. ACLK_PERIHP_PLL_SEL_GPLL,
  96. ACLK_PERIHP_PLL_SEL_HDMIPHY,
  97. ACLK_PERIHP_PLL_SEL_SHIFT = 6,
  98. ACLK_PERIHP_PLL_SEL_MASK = 3 << ACLK_PERIHP_PLL_SEL_SHIFT,
  99. ACLK_PERIHP_DIV_CON_SHIFT = 0,
  100. ACLK_PERIHP_DIV_CON_MASK = 0x1f,
  101. /* CLKSEL_CON29 */
  102. PCLK_PERIHP_DIV_CON_SHIFT = 4,
  103. PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT,
  104. HCLK_PERIHP_DIV_CON_SHIFT = 0,
  105. HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT,
  106. /* CLKSEL_CON22 */
  107. CLK_TSADC_DIV_CON_SHIFT = 0,
  108. CLK_TSADC_DIV_CON_MASK = 0x3ff,
  109. /* CLKSEL_CON23 */
  110. CLK_SARADC_DIV_CON_SHIFT = 0,
  111. CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
  112. CLK_SARADC_DIV_CON_WIDTH = 10,
  113. /* CLKSEL_CON24 */
  114. CLK_PWM_PLL_SEL_CPLL = 0,
  115. CLK_PWM_PLL_SEL_GPLL,
  116. CLK_PWM_PLL_SEL_SHIFT = 15,
  117. CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
  118. CLK_PWM_DIV_CON_SHIFT = 8,
  119. CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
  120. CLK_SPI_PLL_SEL_CPLL = 0,
  121. CLK_SPI_PLL_SEL_GPLL,
  122. CLK_SPI_PLL_SEL_SHIFT = 7,
  123. CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
  124. CLK_SPI_DIV_CON_SHIFT = 0,
  125. CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
  126. /* CLKSEL_CON30 */
  127. CLK_SDMMC_PLL_SEL_CPLL = 0,
  128. CLK_SDMMC_PLL_SEL_GPLL,
  129. CLK_SDMMC_PLL_SEL_24M,
  130. CLK_SDMMC_PLL_SEL_USBPHY,
  131. CLK_SDMMC_PLL_SHIFT = 8,
  132. CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
  133. CLK_SDMMC_DIV_CON_SHIFT = 0,
  134. CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
  135. /* CLKSEL_CON32 */
  136. CLK_EMMC_PLL_SEL_CPLL = 0,
  137. CLK_EMMC_PLL_SEL_GPLL,
  138. CLK_EMMC_PLL_SEL_24M,
  139. CLK_EMMC_PLL_SEL_USBPHY,
  140. CLK_EMMC_PLL_SHIFT = 8,
  141. CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
  142. CLK_EMMC_DIV_CON_SHIFT = 0,
  143. CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
  144. /* CLKSEL_CON34 */
  145. CLK_I2C_PLL_SEL_CPLL = 0,
  146. CLK_I2C_PLL_SEL_GPLL,
  147. CLK_I2C_DIV_CON_MASK = 0x7f,
  148. CLK_I2C_PLL_SEL_MASK = 1,
  149. CLK_I2C1_PLL_SEL_SHIFT = 15,
  150. CLK_I2C1_DIV_CON_SHIFT = 8,
  151. CLK_I2C0_PLL_SEL_SHIFT = 7,
  152. CLK_I2C0_DIV_CON_SHIFT = 0,
  153. /* CLKSEL_CON35 */
  154. CLK_I2C3_PLL_SEL_SHIFT = 15,
  155. CLK_I2C3_DIV_CON_SHIFT = 8,
  156. CLK_I2C2_PLL_SEL_SHIFT = 7,
  157. CLK_I2C2_DIV_CON_SHIFT = 0,
  158. };
  159. #define VCO_MAX_KHZ (3200 * (MHz / KHz))
  160. #define VCO_MIN_KHZ (800 * (MHz / KHz))
  161. #define OUTPUT_MAX_KHZ (3200 * (MHz / KHz))
  162. #define OUTPUT_MIN_KHZ (16 * (MHz / KHz))
  163. /*
  164. * the div restructions of pll in integer mode, these are defined in
  165. * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0
  166. */
  167. #define PLL_DIV_MIN 16
  168. #define PLL_DIV_MAX 3200
  169. /*
  170. * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
  171. * Formulas also embedded within the Fractional PLL Verilog model:
  172. * If DSMPD = 1 (DSM is disabled, "integer mode")
  173. * FOUTVCO = FREF / REFDIV * FBDIV
  174. * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2
  175. * Where:
  176. * FOUTVCO = Fractional PLL non-divided output frequency
  177. * FOUTPOSTDIV = Fractional PLL divided output frequency
  178. * (output of second post divider)
  179. * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
  180. * REFDIV = Fractional PLL input reference clock divider
  181. * FBDIV = Integer value programmed into feedback divide
  182. *
  183. */
  184. static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id,
  185. const struct pll_div *div)
  186. {
  187. u32 *pll_con;
  188. u32 mode_shift, mode_mask;
  189. pll_con = NULL;
  190. mode_shift = 0;
  191. switch (clk_id) {
  192. case CLK_ARM:
  193. pll_con = cru->apll_con;
  194. mode_shift = APLL_MODE_SHIFT;
  195. break;
  196. case CLK_DDR:
  197. pll_con = cru->dpll_con;
  198. mode_shift = DPLL_MODE_SHIFT;
  199. break;
  200. case CLK_CODEC:
  201. pll_con = cru->cpll_con;
  202. mode_shift = CPLL_MODE_SHIFT;
  203. break;
  204. case CLK_GENERAL:
  205. pll_con = cru->gpll_con;
  206. mode_shift = GPLL_MODE_SHIFT;
  207. break;
  208. case CLK_NEW:
  209. pll_con = cru->npll_con;
  210. mode_shift = NPLL_MODE_SHIFT;
  211. break;
  212. default:
  213. break;
  214. }
  215. mode_mask = 1 << mode_shift;
  216. /* All 8 PLLs have same VCO and output frequency range restrictions. */
  217. u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv;
  218. u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2;
  219. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, \
  220. postdiv2=%d, vco=%u khz, output=%u khz\n",
  221. pll_con, div->fbdiv, div->refdiv, div->postdiv1,
  222. div->postdiv2, vco_khz, output_khz);
  223. assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ &&
  224. output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ &&
  225. div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX);
  226. /*
  227. * When power on or changing PLL setting,
  228. * we must force PLL into slow mode to ensure output stable clock.
  229. */
  230. rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift);
  231. /* use integer mode */
  232. rk_clrsetreg(&pll_con[1], PLL_DSMPD_MASK,
  233. PLL_INTEGER_MODE << PLL_DSMPD_SHIFT);
  234. rk_clrsetreg(&pll_con[0],
  235. PLL_FBDIV_MASK | PLL_POSTDIV1_MASK,
  236. (div->fbdiv << PLL_FBDIV_SHIFT) |
  237. (div->postdiv1 << PLL_POSTDIV1_SHIFT));
  238. rk_clrsetreg(&pll_con[1],
  239. PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  240. (div->postdiv2 << PLL_POSTDIV2_SHIFT) |
  241. (div->refdiv << PLL_REFDIV_SHIFT));
  242. /* waiting for pll lock */
  243. while (!(readl(&pll_con[1]) & (1 << PLL_LOCK_STATUS_SHIFT)))
  244. udelay(1);
  245. /* pll enter normal mode */
  246. rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift);
  247. }
  248. static void rkclk_init(struct rk3328_cru *cru)
  249. {
  250. u32 aclk_div;
  251. u32 hclk_div;
  252. u32 pclk_div;
  253. rk3328_configure_cpu(cru, APLL_600_MHZ);
  254. /* configure gpll cpll */
  255. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  256. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
  257. /* configure perihp aclk, hclk, pclk */
  258. aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
  259. hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
  260. pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
  261. rk_clrsetreg(&cru->clksel_con[28],
  262. ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
  263. ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
  264. aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
  265. rk_clrsetreg(&cru->clksel_con[29],
  266. PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK,
  267. pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
  268. hclk_div << HCLK_PERIHP_DIV_CON_SHIFT);
  269. }
  270. void rk3328_configure_cpu(struct rk3328_cru *cru,
  271. enum apll_frequencies apll_freq)
  272. {
  273. u32 clk_core_div;
  274. u32 aclkm_div;
  275. u32 pclk_dbg_div;
  276. rkclk_set_pll(cru, CLK_ARM, apll_cfgs[apll_freq]);
  277. clk_core_div = APLL_HZ / CLK_CORE_HZ - 1;
  278. aclkm_div = APLL_HZ / ACLKM_CORE_HZ / (clk_core_div + 1) - 1;
  279. pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ / (clk_core_div + 1) - 1;
  280. rk_clrsetreg(&cru->clksel_con[0],
  281. CLK_CORE_PLL_SEL_MASK | CLK_CORE_DIV_MASK,
  282. CLK_CORE_PLL_SEL_APLL << CLK_CORE_PLL_SEL_SHIFT |
  283. clk_core_div << CLK_CORE_DIV_SHIFT);
  284. rk_clrsetreg(&cru->clksel_con[1],
  285. PCLK_DBG_DIV_MASK | ACLKM_CORE_DIV_MASK,
  286. pclk_dbg_div << PCLK_DBG_DIV_SHIFT |
  287. aclkm_div << ACLKM_CORE_DIV_SHIFT);
  288. }
  289. static ulong rk3328_i2c_get_clk(struct rk3328_cru *cru, ulong clk_id)
  290. {
  291. u32 div, con;
  292. switch (clk_id) {
  293. case SCLK_I2C0:
  294. con = readl(&cru->clksel_con[34]);
  295. div = con >> CLK_I2C0_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  296. break;
  297. case SCLK_I2C1:
  298. con = readl(&cru->clksel_con[34]);
  299. div = con >> CLK_I2C1_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  300. break;
  301. case SCLK_I2C2:
  302. con = readl(&cru->clksel_con[35]);
  303. div = con >> CLK_I2C2_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  304. break;
  305. case SCLK_I2C3:
  306. con = readl(&cru->clksel_con[35]);
  307. div = con >> CLK_I2C3_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  308. break;
  309. default:
  310. printf("do not support this i2c bus\n");
  311. return -EINVAL;
  312. }
  313. return DIV_TO_RATE(GPLL_HZ, div);
  314. }
  315. static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz)
  316. {
  317. int src_clk_div;
  318. src_clk_div = GPLL_HZ / hz;
  319. assert(src_clk_div - 1 < 127);
  320. switch (clk_id) {
  321. case SCLK_I2C0:
  322. rk_clrsetreg(&cru->clksel_con[34],
  323. CLK_I2C_DIV_CON_MASK << CLK_I2C0_DIV_CON_SHIFT |
  324. CLK_I2C_PLL_SEL_MASK << CLK_I2C0_PLL_SEL_SHIFT,
  325. (src_clk_div - 1) << CLK_I2C0_DIV_CON_SHIFT |
  326. CLK_I2C_PLL_SEL_GPLL << CLK_I2C0_PLL_SEL_SHIFT);
  327. break;
  328. case SCLK_I2C1:
  329. rk_clrsetreg(&cru->clksel_con[34],
  330. CLK_I2C_DIV_CON_MASK << CLK_I2C1_DIV_CON_SHIFT |
  331. CLK_I2C_PLL_SEL_MASK << CLK_I2C1_PLL_SEL_SHIFT,
  332. (src_clk_div - 1) << CLK_I2C1_DIV_CON_SHIFT |
  333. CLK_I2C_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT);
  334. break;
  335. case SCLK_I2C2:
  336. rk_clrsetreg(&cru->clksel_con[35],
  337. CLK_I2C_DIV_CON_MASK << CLK_I2C2_DIV_CON_SHIFT |
  338. CLK_I2C_PLL_SEL_MASK << CLK_I2C2_PLL_SEL_SHIFT,
  339. (src_clk_div - 1) << CLK_I2C2_DIV_CON_SHIFT |
  340. CLK_I2C_PLL_SEL_GPLL << CLK_I2C2_PLL_SEL_SHIFT);
  341. break;
  342. case SCLK_I2C3:
  343. rk_clrsetreg(&cru->clksel_con[35],
  344. CLK_I2C_DIV_CON_MASK << CLK_I2C3_DIV_CON_SHIFT |
  345. CLK_I2C_PLL_SEL_MASK << CLK_I2C3_PLL_SEL_SHIFT,
  346. (src_clk_div - 1) << CLK_I2C3_DIV_CON_SHIFT |
  347. CLK_I2C_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT);
  348. break;
  349. default:
  350. printf("do not support this i2c bus\n");
  351. return -EINVAL;
  352. }
  353. return DIV_TO_RATE(GPLL_HZ, src_clk_div);
  354. }
  355. static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate)
  356. {
  357. struct rk3328_grf_regs *grf;
  358. ulong ret;
  359. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  360. /*
  361. * The RGMII CLK can be derived either from an external "clkin"
  362. * or can be generated from internally by a divider from SCLK_MAC.
  363. */
  364. if (readl(&grf->mac_con[1]) & BIT(10) &&
  365. readl(&grf->soc_con[4]) & BIT(14)) {
  366. /* An external clock will always generate the right rate... */
  367. ret = rate;
  368. } else {
  369. u32 con = readl(&cru->clksel_con[27]);
  370. ulong pll_rate;
  371. u8 div;
  372. if ((con >> GMAC2IO_PLL_SEL_SHIFT) & GMAC2IO_PLL_SEL_GPLL)
  373. pll_rate = GPLL_HZ;
  374. else
  375. pll_rate = CPLL_HZ;
  376. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  377. if (div <= 0x1f)
  378. rk_clrsetreg(&cru->clksel_con[27], GMAC2IO_CLK_DIV_MASK,
  379. div << GMAC2IO_CLK_DIV_SHIFT);
  380. else
  381. debug("Unsupported div for gmac:%d\n", div);
  382. return DIV_TO_RATE(pll_rate, div);
  383. }
  384. return ret;
  385. }
  386. static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
  387. {
  388. u32 div, con, con_id;
  389. switch (clk_id) {
  390. case HCLK_SDMMC:
  391. case SCLK_SDMMC:
  392. con_id = 30;
  393. break;
  394. case HCLK_EMMC:
  395. case SCLK_EMMC:
  396. con_id = 32;
  397. break;
  398. default:
  399. return -EINVAL;
  400. }
  401. con = readl(&cru->clksel_con[con_id]);
  402. div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT;
  403. if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT
  404. == CLK_EMMC_PLL_SEL_24M)
  405. return DIV_TO_RATE(OSC_HZ, div) / 2;
  406. else
  407. return DIV_TO_RATE(GPLL_HZ, div) / 2;
  408. }
  409. static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
  410. ulong clk_id, ulong set_rate)
  411. {
  412. int src_clk_div;
  413. u32 con_id;
  414. switch (clk_id) {
  415. case HCLK_SDMMC:
  416. case SCLK_SDMMC:
  417. con_id = 30;
  418. break;
  419. case HCLK_EMMC:
  420. case SCLK_EMMC:
  421. con_id = 32;
  422. break;
  423. default:
  424. return -EINVAL;
  425. }
  426. /* Select clk_sdmmc/emmc source from GPLL by default */
  427. /* mmc clock defaulg div 2 internal, need provide double in cru */
  428. src_clk_div = DIV_ROUND_UP(GPLL_HZ / 2, set_rate);
  429. if (src_clk_div > 127) {
  430. /* use 24MHz source for 400KHz clock */
  431. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
  432. rk_clrsetreg(&cru->clksel_con[con_id],
  433. CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
  434. CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT |
  435. (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
  436. } else {
  437. rk_clrsetreg(&cru->clksel_con[con_id],
  438. CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK,
  439. CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT |
  440. (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT);
  441. }
  442. return rk3328_mmc_get_clk(cru, clk_id);
  443. }
  444. static ulong rk3328_pwm_get_clk(struct rk3328_cru *cru)
  445. {
  446. u32 div, con;
  447. con = readl(&cru->clksel_con[24]);
  448. div = (con & CLK_PWM_DIV_CON_MASK) >> CLK_PWM_DIV_CON_SHIFT;
  449. return DIV_TO_RATE(GPLL_HZ, div);
  450. }
  451. static ulong rk3328_pwm_set_clk(struct rk3328_cru *cru, uint hz)
  452. {
  453. u32 div = GPLL_HZ / hz;
  454. rk_clrsetreg(&cru->clksel_con[24],
  455. CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
  456. CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
  457. (div - 1) << CLK_PWM_DIV_CON_SHIFT);
  458. return DIV_TO_RATE(GPLL_HZ, div);
  459. }
  460. static ulong rk3328_saradc_get_clk(struct rk3328_cru *cru)
  461. {
  462. u32 div, val;
  463. val = readl(&cru->clksel_con[23]);
  464. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  465. CLK_SARADC_DIV_CON_WIDTH);
  466. return DIV_TO_RATE(OSC_HZ, div);
  467. }
  468. static ulong rk3328_saradc_set_clk(struct rk3328_cru *cru, uint hz)
  469. {
  470. int src_clk_div;
  471. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  472. assert(src_clk_div < 128);
  473. rk_clrsetreg(&cru->clksel_con[23],
  474. CLK_SARADC_DIV_CON_MASK,
  475. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  476. return rk3328_saradc_get_clk(cru);
  477. }
  478. static ulong rk3328_spi_get_clk(struct rk3328_cru *cru)
  479. {
  480. u32 div, val;
  481. val = readl(&cru->clksel_con[24]);
  482. div = (val & CLK_SPI_DIV_CON_MASK) >> CLK_SPI_DIV_CON_SHIFT;
  483. return DIV_TO_RATE(OSC_HZ, div);
  484. }
  485. static ulong rk3328_spi_set_clk(struct rk3328_cru *cru, uint hz)
  486. {
  487. u32 src_clk_div;
  488. src_clk_div = GPLL_HZ / hz;
  489. assert(src_clk_div < 128);
  490. rk_clrsetreg(&cru->clksel_con[24],
  491. CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
  492. CLK_PWM_PLL_SEL_GPLL << CLK_PWM_PLL_SEL_SHIFT |
  493. (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
  494. return rk3328_spi_get_clk(cru);
  495. }
  496. static ulong rk3328_clk_get_rate(struct clk *clk)
  497. {
  498. struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
  499. ulong rate = 0;
  500. switch (clk->id) {
  501. case 0 ... 29:
  502. return 0;
  503. case HCLK_SDMMC:
  504. case HCLK_EMMC:
  505. case SCLK_SDMMC:
  506. case SCLK_EMMC:
  507. rate = rk3328_mmc_get_clk(priv->cru, clk->id);
  508. break;
  509. case SCLK_I2C0:
  510. case SCLK_I2C1:
  511. case SCLK_I2C2:
  512. case SCLK_I2C3:
  513. rate = rk3328_i2c_get_clk(priv->cru, clk->id);
  514. break;
  515. case SCLK_PWM:
  516. rate = rk3328_pwm_get_clk(priv->cru);
  517. break;
  518. case SCLK_SARADC:
  519. rate = rk3328_saradc_get_clk(priv->cru);
  520. break;
  521. case SCLK_SPI:
  522. rate = rk3328_spi_get_clk(priv->cru);
  523. break;
  524. default:
  525. return -ENOENT;
  526. }
  527. return rate;
  528. }
  529. static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
  530. {
  531. struct rk3328_clk_priv *priv = dev_get_priv(clk->dev);
  532. ulong ret = 0;
  533. switch (clk->id) {
  534. case 0 ... 29:
  535. return 0;
  536. case HCLK_SDMMC:
  537. case HCLK_EMMC:
  538. case SCLK_SDMMC:
  539. case SCLK_EMMC:
  540. ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
  541. break;
  542. case SCLK_I2C0:
  543. case SCLK_I2C1:
  544. case SCLK_I2C2:
  545. case SCLK_I2C3:
  546. ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
  547. break;
  548. case SCLK_MAC2IO:
  549. ret = rk3328_gmac2io_set_clk(priv->cru, rate);
  550. break;
  551. case SCLK_PWM:
  552. ret = rk3328_pwm_set_clk(priv->cru, rate);
  553. break;
  554. case SCLK_SARADC:
  555. ret = rk3328_saradc_set_clk(priv->cru, rate);
  556. break;
  557. case SCLK_SPI:
  558. ret = rk3328_spi_set_clk(priv->cru, rate);
  559. break;
  560. case DCLK_LCDC:
  561. case SCLK_PDM:
  562. case SCLK_RTC32K:
  563. case SCLK_UART0:
  564. case SCLK_UART1:
  565. case SCLK_UART2:
  566. case SCLK_SDIO:
  567. case SCLK_TSP:
  568. case SCLK_WIFI:
  569. case ACLK_BUS_PRE:
  570. case HCLK_BUS_PRE:
  571. case PCLK_BUS_PRE:
  572. case ACLK_PERI_PRE:
  573. case HCLK_PERI:
  574. case PCLK_PERI:
  575. case ACLK_VIO_PRE:
  576. case HCLK_VIO_PRE:
  577. case ACLK_RGA_PRE:
  578. case SCLK_RGA:
  579. case ACLK_VOP_PRE:
  580. case ACLK_RKVDEC_PRE:
  581. case ACLK_RKVENC:
  582. case ACLK_VPU_PRE:
  583. case SCLK_VDEC_CABAC:
  584. case SCLK_VDEC_CORE:
  585. case SCLK_VENC_CORE:
  586. case SCLK_VENC_DSP:
  587. case SCLK_EFUSE:
  588. case PCLK_DDR:
  589. case ACLK_GMAC:
  590. case PCLK_GMAC:
  591. case SCLK_USB3OTG_SUSPEND:
  592. return 0;
  593. default:
  594. return -ENOENT;
  595. }
  596. return ret;
  597. }
  598. static int rk3328_gmac2io_set_parent(struct clk *clk, struct clk *parent)
  599. {
  600. struct rk3328_grf_regs *grf;
  601. const char *clock_output_name;
  602. int ret;
  603. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  604. /*
  605. * If the requested parent is in the same clock-controller and the id
  606. * is SCLK_MAC2IO_SRC ("clk_mac2io_src"), switch to the internal clock.
  607. */
  608. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO_SRC)) {
  609. debug("%s: switching RGMII to SCLK_MAC2IO_SRC\n", __func__);
  610. rk_clrreg(&grf->mac_con[1], BIT(10));
  611. return 0;
  612. }
  613. /*
  614. * Otherwise, we need to check the clock-output-names of the
  615. * requested parent to see if the requested id is "gmac_clkin".
  616. */
  617. ret = dev_read_string_index(parent->dev, "clock-output-names",
  618. parent->id, &clock_output_name);
  619. if (ret < 0)
  620. return -ENODATA;
  621. /* If this is "gmac_clkin", switch to the external clock input */
  622. if (!strcmp(clock_output_name, "gmac_clkin")) {
  623. debug("%s: switching RGMII to CLKIN\n", __func__);
  624. rk_setreg(&grf->mac_con[1], BIT(10));
  625. return 0;
  626. }
  627. return -EINVAL;
  628. }
  629. static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent)
  630. {
  631. struct rk3328_grf_regs *grf;
  632. const char *clock_output_name;
  633. int ret;
  634. grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  635. /*
  636. * If the requested parent is in the same clock-controller and the id
  637. * is SCLK_MAC2IO ("clk_mac2io"), switch to the internal clock.
  638. */
  639. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2IO)) {
  640. debug("%s: switching RGMII to SCLK_MAC2IO\n", __func__);
  641. rk_clrreg(&grf->soc_con[4], BIT(14));
  642. return 0;
  643. }
  644. /*
  645. * Otherwise, we need to check the clock-output-names of the
  646. * requested parent to see if the requested id is "gmac_clkin".
  647. */
  648. ret = dev_read_string_index(parent->dev, "clock-output-names",
  649. parent->id, &clock_output_name);
  650. if (ret < 0)
  651. return -ENODATA;
  652. /* If this is "gmac_clkin", switch to the external clock input */
  653. if (!strcmp(clock_output_name, "gmac_clkin")) {
  654. debug("%s: switching RGMII to CLKIN\n", __func__);
  655. rk_setreg(&grf->soc_con[4], BIT(14));
  656. return 0;
  657. }
  658. return -EINVAL;
  659. }
  660. static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
  661. {
  662. switch (clk->id) {
  663. case SCLK_MAC2IO:
  664. return rk3328_gmac2io_set_parent(clk, parent);
  665. case SCLK_MAC2IO_EXT:
  666. return rk3328_gmac2io_ext_set_parent(clk, parent);
  667. case DCLK_LCDC:
  668. case SCLK_PDM:
  669. case SCLK_RTC32K:
  670. case SCLK_UART0:
  671. case SCLK_UART1:
  672. case SCLK_UART2:
  673. return 0;
  674. }
  675. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  676. return -ENOENT;
  677. }
  678. static struct clk_ops rk3328_clk_ops = {
  679. .get_rate = rk3328_clk_get_rate,
  680. .set_rate = rk3328_clk_set_rate,
  681. .set_parent = rk3328_clk_set_parent,
  682. };
  683. static int rk3328_clk_probe(struct udevice *dev)
  684. {
  685. struct rk3328_clk_priv *priv = dev_get_priv(dev);
  686. rkclk_init(priv->cru);
  687. return 0;
  688. }
  689. static int rk3328_clk_of_to_plat(struct udevice *dev)
  690. {
  691. struct rk3328_clk_priv *priv = dev_get_priv(dev);
  692. priv->cru = dev_read_addr_ptr(dev);
  693. return 0;
  694. }
  695. static int rk3328_clk_bind(struct udevice *dev)
  696. {
  697. int ret;
  698. struct udevice *sys_child;
  699. struct sysreset_reg *priv;
  700. /* The reset driver does not have a device node, so bind it here */
  701. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  702. &sys_child);
  703. if (ret) {
  704. debug("Warning: No sysreset driver: ret=%d\n", ret);
  705. } else {
  706. priv = malloc(sizeof(struct sysreset_reg));
  707. priv->glb_srst_fst_value = offsetof(struct rk3328_cru,
  708. glb_srst_fst_value);
  709. priv->glb_srst_snd_value = offsetof(struct rk3328_cru,
  710. glb_srst_snd_value);
  711. dev_set_priv(sys_child, priv);
  712. }
  713. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  714. ret = offsetof(struct rk3328_cru, softrst_con[0]);
  715. ret = rockchip_reset_bind(dev, ret, 12);
  716. if (ret)
  717. debug("Warning: software reset driver bind faile\n");
  718. #endif
  719. return ret;
  720. }
  721. static const struct udevice_id rk3328_clk_ids[] = {
  722. { .compatible = "rockchip,rk3328-cru" },
  723. { }
  724. };
  725. U_BOOT_DRIVER(rockchip_rk3328_cru) = {
  726. .name = "rockchip_rk3328_cru",
  727. .id = UCLASS_CLK,
  728. .of_match = rk3328_clk_ids,
  729. .priv_auto = sizeof(struct rk3328_clk_priv),
  730. .of_to_plat = rk3328_clk_of_to_plat,
  731. .ops = &rk3328_clk_ops,
  732. .bind = rk3328_clk_bind,
  733. .probe = rk3328_clk_probe,
  734. };