clk_rk3308.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017-2019 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <bitfield.h>
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <div64.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <syscon.h>
  14. #include <asm/global_data.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/cru_rk3308.h>
  17. #include <asm/arch-rockchip/clock.h>
  18. #include <asm/arch-rockchip/hardware.h>
  19. #include <dm/device-internal.h>
  20. #include <dm/lists.h>
  21. #include <dt-bindings/clock/rk3308-cru.h>
  22. #include <linux/bitops.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. enum {
  25. VCO_MAX_HZ = 3200U * 1000000,
  26. VCO_MIN_HZ = 800 * 1000000,
  27. OUTPUT_MAX_HZ = 3200U * 1000000,
  28. OUTPUT_MIN_HZ = 24 * 1000000,
  29. };
  30. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  31. #define RK3308_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \
  32. { \
  33. .rate = _rate##U, \
  34. .aclk_div = _aclk_div, \
  35. .pclk_div = _pclk_div, \
  36. }
  37. static struct rockchip_pll_rate_table rk3308_pll_rates[] = {
  38. /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
  39. RK3036_PLL_RATE(1300000000, 6, 325, 1, 1, 1, 0),
  40. RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
  41. RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
  42. RK3036_PLL_RATE(748000000, 2, 187, 3, 1, 1, 0),
  43. };
  44. static struct rockchip_cpu_rate_table rk3308_cpu_rates[] = {
  45. RK3308_CPUCLK_RATE(1200000000, 1, 5),
  46. RK3308_CPUCLK_RATE(1008000000, 1, 5),
  47. RK3308_CPUCLK_RATE(816000000, 1, 3),
  48. RK3308_CPUCLK_RATE(600000000, 1, 3),
  49. RK3308_CPUCLK_RATE(408000000, 1, 1),
  50. };
  51. static struct rockchip_pll_clock rk3308_pll_clks[] = {
  52. [APLL] = PLL(pll_rk3328, PLL_APLL, RK3308_PLL_CON(0),
  53. RK3308_MODE_CON, 0, 10, 0, rk3308_pll_rates),
  54. [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3308_PLL_CON(8),
  55. RK3308_MODE_CON, 2, 10, 0, NULL),
  56. [VPLL0] = PLL(pll_rk3328, PLL_VPLL0, RK3308_PLL_CON(16),
  57. RK3308_MODE_CON, 4, 10, 0, NULL),
  58. [VPLL1] = PLL(pll_rk3328, PLL_VPLL1, RK3308_PLL_CON(24),
  59. RK3308_MODE_CON, 6, 10, 0, NULL),
  60. };
  61. static ulong rk3308_armclk_set_clk(struct rk3308_clk_priv *priv, ulong hz)
  62. {
  63. struct rk3308_cru *cru = priv->cru;
  64. const struct rockchip_cpu_rate_table *rate;
  65. ulong old_rate;
  66. rate = rockchip_get_cpu_settings(rk3308_cpu_rates, hz);
  67. if (!rate) {
  68. printf("%s unsupport rate\n", __func__);
  69. return -EINVAL;
  70. }
  71. /*
  72. * select apll as cpu/core clock pll source and
  73. * set up dependent divisors for PERI and ACLK clocks.
  74. * core hz : apll = 1:1
  75. */
  76. old_rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
  77. priv->cru, APLL);
  78. if (old_rate > hz) {
  79. if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
  80. priv->cru, APLL, hz))
  81. return -EINVAL;
  82. rk_clrsetreg(&cru->clksel_con[0],
  83. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
  84. CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
  85. rate->aclk_div << CORE_ACLK_DIV_SHIFT |
  86. rate->pclk_div << CORE_DBG_DIV_SHIFT |
  87. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  88. 0 << CORE_DIV_CON_SHIFT);
  89. } else if (old_rate < hz) {
  90. rk_clrsetreg(&cru->clksel_con[0],
  91. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK |
  92. CORE_ACLK_DIV_MASK | CORE_DBG_DIV_MASK,
  93. rate->aclk_div << CORE_ACLK_DIV_SHIFT |
  94. rate->pclk_div << CORE_DBG_DIV_SHIFT |
  95. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  96. 0 << CORE_DIV_CON_SHIFT);
  97. if (rockchip_pll_set_rate(&rk3308_pll_clks[APLL],
  98. priv->cru, APLL, hz))
  99. return -EINVAL;
  100. }
  101. return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL);
  102. }
  103. static void rk3308_clk_get_pll_rate(struct rk3308_clk_priv *priv)
  104. {
  105. if (!priv->dpll_hz)
  106. priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
  107. priv->cru, DPLL);
  108. if (!priv->vpll0_hz)
  109. priv->vpll0_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
  110. priv->cru, VPLL0);
  111. if (!priv->vpll1_hz)
  112. priv->vpll1_hz = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
  113. priv->cru, VPLL1);
  114. }
  115. static ulong rk3308_i2c_get_clk(struct clk *clk)
  116. {
  117. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  118. struct rk3308_cru *cru = priv->cru;
  119. u32 div, con, con_id;
  120. switch (clk->id) {
  121. case SCLK_I2C0:
  122. con_id = 25;
  123. break;
  124. case SCLK_I2C1:
  125. con_id = 26;
  126. break;
  127. case SCLK_I2C2:
  128. con_id = 27;
  129. break;
  130. case SCLK_I2C3:
  131. con_id = 28;
  132. break;
  133. default:
  134. printf("do not support this i2c bus\n");
  135. return -EINVAL;
  136. }
  137. con = readl(&cru->clksel_con[con_id]);
  138. div = con >> CLK_I2C_DIV_CON_SHIFT & CLK_I2C_DIV_CON_MASK;
  139. return DIV_TO_RATE(priv->dpll_hz, div);
  140. }
  141. static ulong rk3308_i2c_set_clk(struct clk *clk, uint hz)
  142. {
  143. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  144. struct rk3308_cru *cru = priv->cru;
  145. u32 src_clk_div, con_id;
  146. src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
  147. assert(src_clk_div - 1 <= 127);
  148. switch (clk->id) {
  149. case SCLK_I2C0:
  150. con_id = 25;
  151. break;
  152. case SCLK_I2C1:
  153. con_id = 26;
  154. break;
  155. case SCLK_I2C2:
  156. con_id = 27;
  157. break;
  158. case SCLK_I2C3:
  159. con_id = 28;
  160. break;
  161. default:
  162. printf("do not support this i2c bus\n");
  163. return -EINVAL;
  164. }
  165. rk_clrsetreg(&cru->clksel_con[con_id],
  166. CLK_I2C_PLL_SEL_MASK | CLK_I2C_DIV_CON_MASK,
  167. CLK_I2C_PLL_SEL_DPLL << CLK_I2C_PLL_SEL_SHIFT |
  168. (src_clk_div - 1) << CLK_I2C_DIV_CON_SHIFT);
  169. return rk3308_i2c_get_clk(clk);
  170. }
  171. static ulong rk3308_mac_set_clk(struct clk *clk, uint hz)
  172. {
  173. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  174. struct rk3308_cru *cru = priv->cru;
  175. u32 con = readl(&cru->clksel_con[43]);
  176. ulong pll_rate;
  177. u8 div;
  178. if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL0)
  179. pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
  180. priv->cru, VPLL0);
  181. else if ((con >> MAC_PLL_SHIFT) & MAC_SEL_VPLL1)
  182. pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
  183. priv->cru, VPLL1);
  184. else
  185. pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
  186. priv->cru, DPLL);
  187. /*default set 50MHZ for gmac*/
  188. if (!hz)
  189. hz = 50000000;
  190. div = DIV_ROUND_UP(pll_rate, hz) - 1;
  191. assert(div < 32);
  192. rk_clrsetreg(&cru->clksel_con[43], MAC_DIV_MASK,
  193. div << MAC_DIV_SHIFT);
  194. return DIV_TO_RATE(pll_rate, div);
  195. }
  196. static int rk3308_mac_set_speed_clk(struct clk *clk, uint hz)
  197. {
  198. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  199. struct rk3308_cru *cru = priv->cru;
  200. if (hz != 2500000 && hz != 25000000) {
  201. debug("Unsupported mac speed:%d\n", hz);
  202. return -EINVAL;
  203. }
  204. rk_clrsetreg(&cru->clksel_con[43], MAC_CLK_SPEED_SEL_MASK,
  205. ((hz == 2500000) ? 0 : 1) << MAC_CLK_SPEED_SEL_SHIFT);
  206. return 0;
  207. }
  208. static ulong rk3308_mmc_get_clk(struct clk *clk)
  209. {
  210. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  211. struct rk3308_cru *cru = priv->cru;
  212. u32 div, con, con_id;
  213. switch (clk->id) {
  214. case HCLK_SDMMC:
  215. case SCLK_SDMMC:
  216. con_id = 39;
  217. break;
  218. case HCLK_EMMC:
  219. case SCLK_EMMC:
  220. case SCLK_EMMC_SAMPLE:
  221. con_id = 41;
  222. break;
  223. default:
  224. return -EINVAL;
  225. }
  226. con = readl(&cru->clksel_con[con_id]);
  227. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  228. if ((con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT
  229. == EMMC_SEL_24M)
  230. return DIV_TO_RATE(OSC_HZ, div) / 2;
  231. else
  232. return DIV_TO_RATE(priv->vpll0_hz, div) / 2;
  233. }
  234. static ulong rk3308_mmc_set_clk(struct clk *clk, ulong set_rate)
  235. {
  236. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  237. struct rk3308_cru *cru = priv->cru;
  238. int src_clk_div;
  239. u32 con_id;
  240. switch (clk->id) {
  241. case HCLK_SDMMC:
  242. case SCLK_SDMMC:
  243. con_id = 39;
  244. break;
  245. case HCLK_EMMC:
  246. case SCLK_EMMC:
  247. con_id = 41;
  248. break;
  249. default:
  250. return -EINVAL;
  251. }
  252. /* Select clk_sdmmc/emmc source from VPLL0 by default */
  253. /* mmc clock defaulg div 2 internal, need provide double in cru */
  254. src_clk_div = DIV_ROUND_UP(priv->vpll0_hz / 2, set_rate);
  255. if (src_clk_div > 127) {
  256. /* use 24MHz source for 400KHz clock */
  257. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, set_rate);
  258. rk_clrsetreg(&cru->clksel_con[con_id],
  259. EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
  260. EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
  261. EMMC_SEL_24M << EMMC_PLL_SHIFT |
  262. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  263. } else {
  264. rk_clrsetreg(&cru->clksel_con[con_id],
  265. EMMC_PLL_MASK | EMMC_DIV_MASK | EMMC_CLK_SEL_MASK,
  266. EMMC_CLK_SEL_EMMC << EMMC_CLK_SEL_SHIFT |
  267. EMMC_SEL_VPLL0 << EMMC_PLL_SHIFT |
  268. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  269. }
  270. return rk3308_mmc_get_clk(clk);
  271. }
  272. static ulong rk3308_saradc_get_clk(struct clk *clk)
  273. {
  274. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  275. struct rk3308_cru *cru = priv->cru;
  276. u32 div, con;
  277. con = readl(&cru->clksel_con[34]);
  278. div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
  279. return DIV_TO_RATE(OSC_HZ, div);
  280. }
  281. static ulong rk3308_saradc_set_clk(struct clk *clk, uint hz)
  282. {
  283. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  284. struct rk3308_cru *cru = priv->cru;
  285. int src_clk_div;
  286. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
  287. assert(src_clk_div - 1 <= 2047);
  288. rk_clrsetreg(&cru->clksel_con[34],
  289. CLK_SARADC_DIV_CON_MASK,
  290. (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
  291. return rk3308_saradc_get_clk(clk);
  292. }
  293. static ulong rk3308_tsadc_get_clk(struct clk *clk)
  294. {
  295. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  296. struct rk3308_cru *cru = priv->cru;
  297. u32 div, con;
  298. con = readl(&cru->clksel_con[33]);
  299. div = con >> CLK_SARADC_DIV_CON_SHIFT & CLK_SARADC_DIV_CON_MASK;
  300. return DIV_TO_RATE(OSC_HZ, div);
  301. }
  302. static ulong rk3308_tsadc_set_clk(struct clk *clk, uint hz)
  303. {
  304. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  305. struct rk3308_cru *cru = priv->cru;
  306. int src_clk_div;
  307. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz);
  308. assert(src_clk_div - 1 <= 2047);
  309. rk_clrsetreg(&cru->clksel_con[33],
  310. CLK_SARADC_DIV_CON_MASK,
  311. (src_clk_div - 1) << CLK_SARADC_DIV_CON_SHIFT);
  312. return rk3308_tsadc_get_clk(clk);
  313. }
  314. static ulong rk3308_spi_get_clk(struct clk *clk)
  315. {
  316. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  317. struct rk3308_cru *cru = priv->cru;
  318. u32 div, con, con_id;
  319. switch (clk->id) {
  320. case SCLK_SPI0:
  321. con_id = 30;
  322. break;
  323. case SCLK_SPI1:
  324. con_id = 31;
  325. break;
  326. case SCLK_SPI2:
  327. con_id = 32;
  328. break;
  329. default:
  330. printf("do not support this spi bus\n");
  331. return -EINVAL;
  332. }
  333. con = readl(&cru->clksel_con[con_id]);
  334. div = con >> CLK_SPI_DIV_CON_SHIFT & CLK_SPI_DIV_CON_MASK;
  335. return DIV_TO_RATE(priv->dpll_hz, div);
  336. }
  337. static ulong rk3308_spi_set_clk(struct clk *clk, uint hz)
  338. {
  339. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  340. struct rk3308_cru *cru = priv->cru;
  341. u32 src_clk_div, con_id;
  342. src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
  343. assert(src_clk_div - 1 <= 127);
  344. switch (clk->id) {
  345. case SCLK_SPI0:
  346. con_id = 30;
  347. break;
  348. case SCLK_SPI1:
  349. con_id = 31;
  350. break;
  351. case SCLK_SPI2:
  352. con_id = 32;
  353. break;
  354. default:
  355. printf("do not support this spi bus\n");
  356. return -EINVAL;
  357. }
  358. rk_clrsetreg(&cru->clksel_con[con_id],
  359. CLK_SPI_PLL_SEL_MASK | CLK_SPI_DIV_CON_MASK,
  360. CLK_SPI_PLL_SEL_DPLL << CLK_SPI_PLL_SEL_SHIFT |
  361. (src_clk_div - 1) << CLK_SPI_DIV_CON_SHIFT);
  362. return rk3308_spi_get_clk(clk);
  363. }
  364. static ulong rk3308_pwm_get_clk(struct clk *clk)
  365. {
  366. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  367. struct rk3308_cru *cru = priv->cru;
  368. u32 div, con;
  369. con = readl(&cru->clksel_con[29]);
  370. div = con >> CLK_PWM_DIV_CON_SHIFT & CLK_PWM_DIV_CON_MASK;
  371. return DIV_TO_RATE(priv->dpll_hz, div);
  372. }
  373. static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
  374. {
  375. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  376. struct rk3308_cru *cru = priv->cru;
  377. int src_clk_div;
  378. src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
  379. assert(src_clk_div - 1 <= 127);
  380. rk_clrsetreg(&cru->clksel_con[29],
  381. CLK_PWM_PLL_SEL_MASK | CLK_PWM_DIV_CON_MASK,
  382. CLK_PWM_PLL_SEL_DPLL << CLK_PWM_PLL_SEL_SHIFT |
  383. (src_clk_div - 1) << CLK_PWM_DIV_CON_SHIFT);
  384. return rk3308_pwm_get_clk(clk);
  385. }
  386. static ulong rk3308_vop_get_clk(struct clk *clk)
  387. {
  388. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  389. struct rk3308_cru *cru = priv->cru;
  390. u32 div, pll_sel, vol_sel, con, parent;
  391. con = readl(&cru->clksel_con[8]);
  392. vol_sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
  393. pll_sel = (con & DCLK_VOP_PLL_SEL_MASK) >> DCLK_VOP_PLL_SEL_SHIFT;
  394. div = con & DCLK_VOP_DIV_MASK;
  395. if (vol_sel == DCLK_VOP_SEL_24M) {
  396. parent = OSC_HZ;
  397. } else if (vol_sel == DCLK_VOP_SEL_DIVOUT) {
  398. switch (pll_sel) {
  399. case DCLK_VOP_PLL_SEL_DPLL:
  400. parent = priv->dpll_hz;
  401. break;
  402. case DCLK_VOP_PLL_SEL_VPLL0:
  403. parent = priv->vpll0_hz;
  404. break;
  405. case DCLK_VOP_PLL_SEL_VPLL1:
  406. parent = priv->vpll0_hz;
  407. break;
  408. default:
  409. printf("do not support this vop pll sel\n");
  410. return -EINVAL;
  411. }
  412. } else {
  413. printf("do not support this vop sel\n");
  414. return -EINVAL;
  415. }
  416. return DIV_TO_RATE(parent, div);
  417. }
  418. static ulong rk3308_vop_set_clk(struct clk *clk, ulong hz)
  419. {
  420. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  421. struct rk3308_cru *cru = priv->cru;
  422. ulong pll_rate, now, best_rate = 0;
  423. u32 i, div, best_div = 0, best_sel = 0;
  424. for (i = 0; i <= DCLK_VOP_PLL_SEL_VPLL1; i++) {
  425. switch (i) {
  426. case DCLK_VOP_PLL_SEL_DPLL:
  427. pll_rate = priv->dpll_hz;
  428. break;
  429. case DCLK_VOP_PLL_SEL_VPLL0:
  430. pll_rate = priv->vpll0_hz;
  431. break;
  432. case DCLK_VOP_PLL_SEL_VPLL1:
  433. pll_rate = priv->vpll1_hz;
  434. break;
  435. default:
  436. printf("do not support this vop pll sel\n");
  437. return -EINVAL;
  438. }
  439. div = DIV_ROUND_UP(pll_rate, hz);
  440. if (div > 255)
  441. continue;
  442. now = pll_rate / div;
  443. if (abs(hz - now) < abs(hz - best_rate)) {
  444. best_rate = now;
  445. best_div = div;
  446. best_sel = i;
  447. }
  448. debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n",
  449. pll_rate, best_rate, best_div, best_sel);
  450. }
  451. if (best_rate != hz && hz == OSC_HZ) {
  452. rk_clrsetreg(&cru->clksel_con[8],
  453. DCLK_VOP_SEL_MASK,
  454. DCLK_VOP_SEL_24M << DCLK_VOP_SEL_SHIFT);
  455. } else if (best_rate) {
  456. rk_clrsetreg(&cru->clksel_con[8],
  457. DCLK_VOP_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |
  458. DCLK_VOP_DIV_MASK,
  459. DCLK_VOP_SEL_DIVOUT << DCLK_VOP_SEL_SHIFT |
  460. best_sel << DCLK_VOP_PLL_SEL_SHIFT |
  461. (best_div - 1) << DCLK_VOP_DIV_SHIFT);
  462. } else {
  463. printf("do not support this vop freq\n");
  464. return -EINVAL;
  465. }
  466. return rk3308_vop_get_clk(clk);
  467. }
  468. static ulong rk3308_bus_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
  469. {
  470. struct rk3308_cru *cru = priv->cru;
  471. u32 div, con, parent = priv->dpll_hz;
  472. switch (clk_id) {
  473. case ACLK_BUS:
  474. con = readl(&cru->clksel_con[5]);
  475. div = (con & BUS_ACLK_DIV_MASK) >> BUS_ACLK_DIV_SHIFT;
  476. break;
  477. case HCLK_BUS:
  478. con = readl(&cru->clksel_con[6]);
  479. div = (con & BUS_HCLK_DIV_MASK) >> BUS_HCLK_DIV_SHIFT;
  480. break;
  481. case PCLK_BUS:
  482. case PCLK_WDT:
  483. con = readl(&cru->clksel_con[6]);
  484. div = (con & BUS_PCLK_DIV_MASK) >> BUS_PCLK_DIV_SHIFT;
  485. break;
  486. default:
  487. return -ENOENT;
  488. }
  489. return DIV_TO_RATE(parent, div);
  490. }
  491. static ulong rk3308_bus_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
  492. ulong hz)
  493. {
  494. struct rk3308_cru *cru = priv->cru;
  495. int src_clk_div;
  496. src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
  497. assert(src_clk_div - 1 <= 31);
  498. /*
  499. * select dpll as pd_bus bus clock source and
  500. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  501. */
  502. switch (clk_id) {
  503. case ACLK_BUS:
  504. rk_clrsetreg(&cru->clksel_con[5],
  505. BUS_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  506. BUS_PLL_SEL_DPLL << BUS_PLL_SEL_SHIFT |
  507. (src_clk_div - 1) << BUS_ACLK_DIV_SHIFT);
  508. break;
  509. case HCLK_BUS:
  510. rk_clrsetreg(&cru->clksel_con[6],
  511. BUS_HCLK_DIV_MASK,
  512. (src_clk_div - 1) << BUS_HCLK_DIV_SHIFT);
  513. break;
  514. case PCLK_BUS:
  515. rk_clrsetreg(&cru->clksel_con[6],
  516. BUS_PCLK_DIV_MASK,
  517. (src_clk_div - 1) << BUS_PCLK_DIV_SHIFT);
  518. break;
  519. default:
  520. printf("do not support this bus freq\n");
  521. return -EINVAL;
  522. }
  523. return rk3308_bus_get_clk(priv, clk_id);
  524. }
  525. static ulong rk3308_peri_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
  526. {
  527. struct rk3308_cru *cru = priv->cru;
  528. u32 div, con, parent = priv->dpll_hz;
  529. switch (clk_id) {
  530. case ACLK_PERI:
  531. con = readl(&cru->clksel_con[36]);
  532. div = (con & PERI_ACLK_DIV_MASK) >> PERI_ACLK_DIV_SHIFT;
  533. break;
  534. case HCLK_PERI:
  535. con = readl(&cru->clksel_con[37]);
  536. div = (con & PERI_HCLK_DIV_MASK) >> PERI_HCLK_DIV_SHIFT;
  537. break;
  538. case PCLK_PERI:
  539. con = readl(&cru->clksel_con[37]);
  540. div = (con & PERI_PCLK_DIV_MASK) >> PERI_PCLK_DIV_SHIFT;
  541. break;
  542. default:
  543. return -ENOENT;
  544. }
  545. return DIV_TO_RATE(parent, div);
  546. }
  547. static ulong rk3308_peri_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
  548. ulong hz)
  549. {
  550. struct rk3308_cru *cru = priv->cru;
  551. int src_clk_div;
  552. src_clk_div = DIV_ROUND_UP(priv->dpll_hz, hz);
  553. assert(src_clk_div - 1 <= 31);
  554. /*
  555. * select dpll as pd_peri bus clock source and
  556. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  557. */
  558. switch (clk_id) {
  559. case ACLK_PERI:
  560. rk_clrsetreg(&cru->clksel_con[36],
  561. PERI_PLL_SEL_MASK | PERI_ACLK_DIV_MASK,
  562. PERI_PLL_DPLL << PERI_PLL_SEL_SHIFT |
  563. (src_clk_div - 1) << PERI_ACLK_DIV_SHIFT);
  564. break;
  565. case HCLK_PERI:
  566. rk_clrsetreg(&cru->clksel_con[37],
  567. PERI_HCLK_DIV_MASK,
  568. (src_clk_div - 1) << PERI_HCLK_DIV_SHIFT);
  569. break;
  570. case PCLK_PERI:
  571. rk_clrsetreg(&cru->clksel_con[37],
  572. PERI_PCLK_DIV_MASK,
  573. (src_clk_div - 1) << PERI_PCLK_DIV_SHIFT);
  574. break;
  575. default:
  576. printf("do not support this peri freq\n");
  577. return -EINVAL;
  578. }
  579. return rk3308_peri_get_clk(priv, clk_id);
  580. }
  581. static ulong rk3308_audio_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
  582. {
  583. struct rk3308_cru *cru = priv->cru;
  584. u32 div, con, parent = priv->vpll0_hz;
  585. switch (clk_id) {
  586. case HCLK_AUDIO:
  587. con = readl(&cru->clksel_con[45]);
  588. div = (con & AUDIO_HCLK_DIV_MASK) >> AUDIO_HCLK_DIV_SHIFT;
  589. break;
  590. case PCLK_AUDIO:
  591. con = readl(&cru->clksel_con[45]);
  592. div = (con & AUDIO_PCLK_DIV_MASK) >> AUDIO_PCLK_DIV_SHIFT;
  593. break;
  594. default:
  595. return -ENOENT;
  596. }
  597. return DIV_TO_RATE(parent, div);
  598. }
  599. static ulong rk3308_audio_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
  600. ulong hz)
  601. {
  602. struct rk3308_cru *cru = priv->cru;
  603. int src_clk_div;
  604. src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
  605. assert(src_clk_div - 1 <= 31);
  606. /*
  607. * select vpll0 as audio bus clock source and
  608. * set up dependent divisors for HCLK and PCLK clocks.
  609. */
  610. switch (clk_id) {
  611. case HCLK_AUDIO:
  612. rk_clrsetreg(&cru->clksel_con[45],
  613. AUDIO_PLL_SEL_MASK | AUDIO_HCLK_DIV_MASK,
  614. AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
  615. (src_clk_div - 1) << AUDIO_HCLK_DIV_SHIFT);
  616. break;
  617. case PCLK_AUDIO:
  618. rk_clrsetreg(&cru->clksel_con[45],
  619. AUDIO_PLL_SEL_MASK | AUDIO_PCLK_DIV_MASK,
  620. AUDIO_PLL_VPLL0 << AUDIO_PLL_SEL_SHIFT |
  621. (src_clk_div - 1) << AUDIO_PCLK_DIV_SHIFT);
  622. break;
  623. default:
  624. printf("do not support this audio freq\n");
  625. return -EINVAL;
  626. }
  627. return rk3308_peri_get_clk(priv, clk_id);
  628. }
  629. static ulong rk3308_crypto_get_clk(struct rk3308_clk_priv *priv, ulong clk_id)
  630. {
  631. struct rk3308_cru *cru = priv->cru;
  632. u32 div, con, parent;
  633. switch (clk_id) {
  634. case SCLK_CRYPTO:
  635. con = readl(&cru->clksel_con[7]);
  636. div = (con & CRYPTO_DIV_MASK) >> CRYPTO_DIV_SHIFT;
  637. parent = priv->vpll0_hz;
  638. break;
  639. case SCLK_CRYPTO_APK:
  640. con = readl(&cru->clksel_con[7]);
  641. div = (con & CRYPTO_APK_DIV_MASK) >> CRYPTO_APK_DIV_SHIFT;
  642. parent = priv->vpll0_hz;
  643. break;
  644. default:
  645. return -ENOENT;
  646. }
  647. return DIV_TO_RATE(parent, div);
  648. }
  649. static ulong rk3308_crypto_set_clk(struct rk3308_clk_priv *priv, ulong clk_id,
  650. ulong hz)
  651. {
  652. struct rk3308_cru *cru = priv->cru;
  653. int src_clk_div;
  654. src_clk_div = DIV_ROUND_UP(priv->vpll0_hz, hz);
  655. assert(src_clk_div - 1 <= 31);
  656. /*
  657. * select gpll as crypto clock source and
  658. * set up dependent divisors for crypto clocks.
  659. */
  660. switch (clk_id) {
  661. case SCLK_CRYPTO:
  662. rk_clrsetreg(&cru->clksel_con[7],
  663. CRYPTO_PLL_SEL_MASK | CRYPTO_DIV_MASK,
  664. CRYPTO_PLL_SEL_VPLL0 << CRYPTO_PLL_SEL_SHIFT |
  665. (src_clk_div - 1) << CRYPTO_DIV_SHIFT);
  666. break;
  667. case SCLK_CRYPTO_APK:
  668. rk_clrsetreg(&cru->clksel_con[7],
  669. CRYPTO_APK_PLL_SEL_MASK | CRYPTO_APK_DIV_MASK,
  670. CRYPTO_PLL_SEL_VPLL0 << CRYPTO_APK_SEL_SHIFT |
  671. (src_clk_div - 1) << CRYPTO_APK_DIV_SHIFT);
  672. break;
  673. default:
  674. printf("do not support this peri freq\n");
  675. return -EINVAL;
  676. }
  677. return rk3308_crypto_get_clk(priv, clk_id);
  678. }
  679. static ulong rk3308_clk_get_rate(struct clk *clk)
  680. {
  681. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  682. ulong rate = 0;
  683. debug("%s id:%ld\n", __func__, clk->id);
  684. switch (clk->id) {
  685. case PLL_APLL:
  686. case ARMCLK:
  687. rate = rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
  688. priv->cru, APLL);
  689. break;
  690. case PLL_DPLL:
  691. rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
  692. priv->cru, DPLL);
  693. break;
  694. case PLL_VPLL0:
  695. rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0],
  696. priv->cru, VPLL0);
  697. break;
  698. case PLL_VPLL1:
  699. rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1],
  700. priv->cru, VPLL1);
  701. break;
  702. case HCLK_SDMMC:
  703. case HCLK_EMMC:
  704. case SCLK_SDMMC:
  705. case SCLK_EMMC:
  706. case SCLK_EMMC_SAMPLE:
  707. rate = rk3308_mmc_get_clk(clk);
  708. break;
  709. case SCLK_I2C0:
  710. case SCLK_I2C1:
  711. case SCLK_I2C2:
  712. case SCLK_I2C3:
  713. rate = rk3308_i2c_get_clk(clk);
  714. break;
  715. case SCLK_SARADC:
  716. rate = rk3308_saradc_get_clk(clk);
  717. break;
  718. case SCLK_TSADC:
  719. rate = rk3308_tsadc_get_clk(clk);
  720. break;
  721. case SCLK_SPI0:
  722. case SCLK_SPI1:
  723. rate = rk3308_spi_get_clk(clk);
  724. break;
  725. case SCLK_PWM0:
  726. rate = rk3308_pwm_get_clk(clk);
  727. break;
  728. case DCLK_VOP:
  729. rate = rk3308_vop_get_clk(clk);
  730. break;
  731. case ACLK_BUS:
  732. case HCLK_BUS:
  733. case PCLK_BUS:
  734. case PCLK_WDT:
  735. rate = rk3308_bus_get_clk(priv, clk->id);
  736. break;
  737. case ACLK_PERI:
  738. case HCLK_PERI:
  739. case PCLK_PERI:
  740. rate = rk3308_peri_get_clk(priv, clk->id);
  741. break;
  742. case HCLK_AUDIO:
  743. case PCLK_AUDIO:
  744. rate = rk3308_audio_get_clk(priv, clk->id);
  745. break;
  746. case SCLK_CRYPTO:
  747. case SCLK_CRYPTO_APK:
  748. rate = rk3308_crypto_get_clk(priv, clk->id);
  749. break;
  750. default:
  751. return -ENOENT;
  752. }
  753. return rate;
  754. }
  755. static ulong rk3308_clk_set_rate(struct clk *clk, ulong rate)
  756. {
  757. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  758. ulong ret = 0;
  759. debug("%s %ld %ld\n", __func__, clk->id, rate);
  760. switch (clk->id) {
  761. case PLL_DPLL:
  762. ret = rockchip_pll_set_rate(&rk3308_pll_clks[DPLL], priv->cru,
  763. DPLL, rate);
  764. priv->dpll_hz = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL],
  765. priv->cru, DPLL);
  766. break;
  767. case ARMCLK:
  768. if (priv->armclk_hz)
  769. rk3308_armclk_set_clk(priv, rate);
  770. priv->armclk_hz = rate;
  771. break;
  772. case HCLK_SDMMC:
  773. case HCLK_EMMC:
  774. case SCLK_SDMMC:
  775. case SCLK_EMMC:
  776. ret = rk3308_mmc_set_clk(clk, rate);
  777. break;
  778. case SCLK_I2C0:
  779. case SCLK_I2C1:
  780. case SCLK_I2C2:
  781. case SCLK_I2C3:
  782. ret = rk3308_i2c_set_clk(clk, rate);
  783. break;
  784. case SCLK_MAC:
  785. ret = rk3308_mac_set_clk(clk, rate);
  786. break;
  787. case SCLK_MAC_RMII:
  788. ret = rk3308_mac_set_speed_clk(clk, rate);
  789. break;
  790. case SCLK_SARADC:
  791. ret = rk3308_saradc_set_clk(clk, rate);
  792. break;
  793. case SCLK_TSADC:
  794. ret = rk3308_tsadc_set_clk(clk, rate);
  795. break;
  796. case SCLK_SPI0:
  797. case SCLK_SPI1:
  798. ret = rk3308_spi_set_clk(clk, rate);
  799. break;
  800. case SCLK_PWM0:
  801. ret = rk3308_pwm_set_clk(clk, rate);
  802. break;
  803. case DCLK_VOP:
  804. ret = rk3308_vop_set_clk(clk, rate);
  805. break;
  806. case ACLK_BUS:
  807. case HCLK_BUS:
  808. case PCLK_BUS:
  809. rate = rk3308_bus_set_clk(priv, clk->id, rate);
  810. break;
  811. case ACLK_PERI:
  812. case HCLK_PERI:
  813. case PCLK_PERI:
  814. rate = rk3308_peri_set_clk(priv, clk->id, rate);
  815. break;
  816. case HCLK_AUDIO:
  817. case PCLK_AUDIO:
  818. rate = rk3308_audio_set_clk(priv, clk->id, rate);
  819. break;
  820. case SCLK_CRYPTO:
  821. case SCLK_CRYPTO_APK:
  822. ret = rk3308_crypto_set_clk(priv, clk->id, rate);
  823. break;
  824. default:
  825. return -ENOENT;
  826. }
  827. return ret;
  828. }
  829. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  830. static int __maybe_unused rk3308_mac_set_parent(struct clk *clk, struct clk *parent)
  831. {
  832. struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
  833. /*
  834. * If the requested parent is in the same clock-controller and
  835. * the id is SCLK_MAC_SRC, switch to the internal clock.
  836. */
  837. if (parent->id == SCLK_MAC_SRC) {
  838. debug("%s: switching RMII to SCLK_MAC\n", __func__);
  839. rk_clrreg(&priv->cru->clksel_con[43], BIT(14));
  840. } else {
  841. debug("%s: switching RMII to CLKIN\n", __func__);
  842. rk_setreg(&priv->cru->clksel_con[43], BIT(14));
  843. }
  844. return 0;
  845. }
  846. static int __maybe_unused rk3308_clk_set_parent(struct clk *clk, struct clk *parent)
  847. {
  848. switch (clk->id) {
  849. case SCLK_MAC:
  850. return rk3308_mac_set_parent(clk, parent);
  851. default:
  852. break;
  853. }
  854. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  855. return -ENOENT;
  856. }
  857. #endif
  858. static struct clk_ops rk3308_clk_ops = {
  859. .get_rate = rk3308_clk_get_rate,
  860. .set_rate = rk3308_clk_set_rate,
  861. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  862. .set_parent = rk3308_clk_set_parent,
  863. #endif
  864. };
  865. static void rk3308_clk_init(struct udevice *dev)
  866. {
  867. struct rk3308_clk_priv *priv = dev_get_priv(dev);
  868. int ret;
  869. if (rockchip_pll_get_rate(&rk3308_pll_clks[APLL],
  870. priv->cru, APLL) != APLL_HZ) {
  871. ret = rk3308_armclk_set_clk(priv, APLL_HZ);
  872. if (ret < 0)
  873. printf("%s failed to set armclk rate\n", __func__);
  874. }
  875. rk3308_clk_get_pll_rate(priv);
  876. rk3308_bus_set_clk(priv, ACLK_BUS, BUS_ACLK_HZ);
  877. rk3308_bus_set_clk(priv, HCLK_BUS, BUS_HCLK_HZ);
  878. rk3308_bus_set_clk(priv, PCLK_BUS, BUS_PCLK_HZ);
  879. rk3308_peri_set_clk(priv, ACLK_PERI, PERI_ACLK_HZ);
  880. rk3308_peri_set_clk(priv, HCLK_PERI, PERI_HCLK_HZ);
  881. rk3308_peri_set_clk(priv, PCLK_PERI, PERI_PCLK_HZ);
  882. rk3308_audio_set_clk(priv, HCLK_AUDIO, AUDIO_HCLK_HZ);
  883. rk3308_audio_set_clk(priv, PCLK_AUDIO, AUDIO_PCLK_HZ);
  884. }
  885. static int rk3308_clk_probe(struct udevice *dev)
  886. {
  887. int ret;
  888. rk3308_clk_init(dev);
  889. /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
  890. ret = clk_set_defaults(dev, CLK_DEFAULTS_POST);
  891. if (ret)
  892. debug("%s clk_set_defaults failed %d\n", __func__, ret);
  893. return ret;
  894. }
  895. static int rk3308_clk_of_to_plat(struct udevice *dev)
  896. {
  897. struct rk3308_clk_priv *priv = dev_get_priv(dev);
  898. priv->cru = dev_read_addr_ptr(dev);
  899. return 0;
  900. }
  901. static int rk3308_clk_bind(struct udevice *dev)
  902. {
  903. int ret;
  904. struct udevice *sys_child;
  905. struct sysreset_reg *priv;
  906. /* The reset driver does not have a device node, so bind it here */
  907. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  908. &sys_child);
  909. if (ret) {
  910. debug("Warning: No sysreset driver: ret=%d\n", ret);
  911. } else {
  912. priv = malloc(sizeof(struct sysreset_reg));
  913. priv->glb_srst_fst_value = offsetof(struct rk3308_cru,
  914. glb_srst_fst);
  915. priv->glb_srst_snd_value = offsetof(struct rk3308_cru,
  916. glb_srst_snd);
  917. dev_set_priv(sys_child, priv);
  918. }
  919. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  920. ret = offsetof(struct rk3308_cru, softrst_con[0]);
  921. ret = rockchip_reset_bind(dev, ret, 12);
  922. if (ret)
  923. debug("Warning: software reset driver bind faile\n");
  924. #endif
  925. return 0;
  926. }
  927. static const struct udevice_id rk3308_clk_ids[] = {
  928. { .compatible = "rockchip,rk3308-cru" },
  929. { }
  930. };
  931. U_BOOT_DRIVER(rockchip_rk3308_cru) = {
  932. .name = "rockchip_rk3308_cru",
  933. .id = UCLASS_CLK,
  934. .of_match = rk3308_clk_ids,
  935. .priv_auto = sizeof(struct rk3308_clk_priv),
  936. .of_to_plat = rk3308_clk_of_to_plat,
  937. .ops = &rk3308_clk_ops,
  938. .bind = rk3308_clk_bind,
  939. .probe = rk3308_clk_probe,
  940. };