clk_rk3288.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <bitfield.h>
  7. #include <clk-uclass.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <dt-structs.h>
  11. #include <errno.h>
  12. #include <log.h>
  13. #include <malloc.h>
  14. #include <mapmem.h>
  15. #include <syscon.h>
  16. #include <asm/global_data.h>
  17. #include <asm/io.h>
  18. #include <asm/arch-rockchip/clock.h>
  19. #include <asm/arch-rockchip/cru.h>
  20. #include <asm/arch-rockchip/grf_rk3288.h>
  21. #include <asm/arch-rockchip/hardware.h>
  22. #include <dt-bindings/clock/rk3288-cru.h>
  23. #include <dm/device-internal.h>
  24. #include <dm/lists.h>
  25. #include <dm/uclass-internal.h>
  26. #include <linux/bitops.h>
  27. #include <linux/delay.h>
  28. #include <linux/err.h>
  29. #include <linux/log2.h>
  30. #include <linux/stringify.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. struct rk3288_clk_plat {
  33. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  34. struct dtd_rockchip_rk3288_cru dtd;
  35. #endif
  36. };
  37. struct pll_div {
  38. u32 nr;
  39. u32 nf;
  40. u32 no;
  41. };
  42. enum {
  43. VCO_MAX_HZ = 2200U * 1000000,
  44. VCO_MIN_HZ = 440 * 1000000,
  45. OUTPUT_MAX_HZ = 2200U * 1000000,
  46. OUTPUT_MIN_HZ = 27500000,
  47. FREF_MAX_HZ = 2200U * 1000000,
  48. FREF_MIN_HZ = 269 * 1000,
  49. };
  50. enum {
  51. /* PLL CON0 */
  52. PLL_OD_MASK = 0x0f,
  53. /* PLL CON1 */
  54. PLL_NF_MASK = 0x1fff,
  55. /* PLL CON2 */
  56. PLL_BWADJ_MASK = 0x0fff,
  57. /* PLL CON3 */
  58. PLL_RESET_SHIFT = 5,
  59. /* CLKSEL0 */
  60. CORE_SEL_PLL_SHIFT = 15,
  61. CORE_SEL_PLL_MASK = 1 << CORE_SEL_PLL_SHIFT,
  62. A17_DIV_SHIFT = 8,
  63. A17_DIV_MASK = 0x1f << A17_DIV_SHIFT,
  64. MP_DIV_SHIFT = 4,
  65. MP_DIV_MASK = 0xf << MP_DIV_SHIFT,
  66. M0_DIV_SHIFT = 0,
  67. M0_DIV_MASK = 0xf << M0_DIV_SHIFT,
  68. /* CLKSEL1: pd bus clk pll sel: codec or general */
  69. PD_BUS_SEL_PLL_MASK = 15,
  70. PD_BUS_SEL_CPLL = 0,
  71. PD_BUS_SEL_GPLL,
  72. /* pd bus pclk div: pclk = pd_bus_aclk /(div + 1) */
  73. PD_BUS_PCLK_DIV_SHIFT = 12,
  74. PD_BUS_PCLK_DIV_MASK = 7 << PD_BUS_PCLK_DIV_SHIFT,
  75. /* pd bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  76. PD_BUS_HCLK_DIV_SHIFT = 8,
  77. PD_BUS_HCLK_DIV_MASK = 3 << PD_BUS_HCLK_DIV_SHIFT,
  78. /* pd bus aclk div: pd_bus_aclk = pd_bus_src_clk /(div0 * div1) */
  79. PD_BUS_ACLK_DIV0_SHIFT = 3,
  80. PD_BUS_ACLK_DIV0_MASK = 0x1f << PD_BUS_ACLK_DIV0_SHIFT,
  81. PD_BUS_ACLK_DIV1_SHIFT = 0,
  82. PD_BUS_ACLK_DIV1_MASK = 0x7 << PD_BUS_ACLK_DIV1_SHIFT,
  83. /*
  84. * CLKSEL10
  85. * peripheral bus pclk div:
  86. * aclk_bus: pclk_bus = 1:1 or 2:1 or 4:1 or 8:1
  87. */
  88. PERI_SEL_PLL_SHIFT = 15,
  89. PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
  90. PERI_SEL_CPLL = 0,
  91. PERI_SEL_GPLL,
  92. PERI_PCLK_DIV_SHIFT = 12,
  93. PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
  94. /* peripheral bus hclk div: aclk_bus: hclk_bus = 1:1 or 2:1 or 4:1 */
  95. PERI_HCLK_DIV_SHIFT = 8,
  96. PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
  97. /*
  98. * peripheral bus aclk div:
  99. * aclk_periph = periph_clk_src / (peri_aclk_div_con + 1)
  100. */
  101. PERI_ACLK_DIV_SHIFT = 0,
  102. PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
  103. /*
  104. * CLKSEL24
  105. * saradc_div_con:
  106. * clk_saradc=24MHz/(saradc_div_con+1)
  107. */
  108. CLK_SARADC_DIV_CON_SHIFT = 8,
  109. CLK_SARADC_DIV_CON_MASK = GENMASK(15, 8),
  110. CLK_SARADC_DIV_CON_WIDTH = 8,
  111. SOCSTS_DPLL_LOCK = 1 << 5,
  112. SOCSTS_APLL_LOCK = 1 << 6,
  113. SOCSTS_CPLL_LOCK = 1 << 7,
  114. SOCSTS_GPLL_LOCK = 1 << 8,
  115. SOCSTS_NPLL_LOCK = 1 << 9,
  116. };
  117. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  118. #define PLL_DIVISORS(hz, _nr, _no) {\
  119. .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\
  120. _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\
  121. (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\
  122. "divisors on line " __stringify(__LINE__));
  123. /* Keep divisors as low as possible to reduce jitter and power usage */
  124. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
  125. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
  126. static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
  127. static int rkclk_set_pll(struct rockchip_cru *cru, enum rk_clk_id clk_id,
  128. const struct pll_div *div)
  129. {
  130. int pll_id = rk_pll_id(clk_id);
  131. struct rk3288_pll *pll = &cru->pll[pll_id];
  132. /* All PLLs have same VCO and output frequency range restrictions. */
  133. uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000;
  134. uint output_hz = vco_hz / div->no;
  135. debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n",
  136. (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz);
  137. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  138. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ &&
  139. (div->no == 1 || !(div->no % 2)));
  140. /* enter reset */
  141. rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  142. rk_clrsetreg(&pll->con0, CLKR_MASK | PLL_OD_MASK,
  143. ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1));
  144. rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1);
  145. rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1);
  146. udelay(10);
  147. /* return from reset */
  148. rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT);
  149. return 0;
  150. }
  151. static int rkclk_configure_ddr(struct rockchip_cru *cru, struct rk3288_grf *grf,
  152. unsigned int hz)
  153. {
  154. static const struct pll_div dpll_cfg[] = {
  155. {.nf = 25, .nr = 2, .no = 1},
  156. {.nf = 400, .nr = 9, .no = 2},
  157. {.nf = 500, .nr = 9, .no = 2},
  158. {.nf = 100, .nr = 3, .no = 1},
  159. };
  160. int cfg;
  161. switch (hz) {
  162. case 300000000:
  163. cfg = 0;
  164. break;
  165. case 533000000: /* actually 533.3P MHz */
  166. cfg = 1;
  167. break;
  168. case 666000000: /* actually 666.6P MHz */
  169. cfg = 2;
  170. break;
  171. case 800000000:
  172. cfg = 3;
  173. break;
  174. default:
  175. debug("Unsupported SDRAM frequency");
  176. return -EINVAL;
  177. }
  178. /* pll enter slow-mode */
  179. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
  180. DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
  181. rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]);
  182. /* wait for pll lock */
  183. while (!(readl(&grf->soc_status[1]) & SOCSTS_DPLL_LOCK))
  184. udelay(1);
  185. /* PLL enter normal-mode */
  186. rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
  187. DPLL_MODE_NORMAL << DPLL_MODE_SHIFT);
  188. return 0;
  189. }
  190. #ifndef CONFIG_SPL_BUILD
  191. #define VCO_MAX_KHZ 2200000
  192. #define VCO_MIN_KHZ 440000
  193. #define FREF_MAX_KHZ 2200000
  194. #define FREF_MIN_KHZ 269
  195. static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div)
  196. {
  197. uint ref_khz = OSC_HZ / 1000, nr, nf = 0;
  198. uint fref_khz;
  199. uint diff_khz, best_diff_khz;
  200. const uint max_nr = 1 << 6, max_nf = 1 << 12, max_no = 1 << 4;
  201. uint vco_khz;
  202. uint no = 1;
  203. uint freq_khz = freq_hz / 1000;
  204. if (!freq_hz) {
  205. printf("%s: the frequency can not be 0 Hz\n", __func__);
  206. return -EINVAL;
  207. }
  208. no = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz);
  209. if (ext_div) {
  210. *ext_div = DIV_ROUND_UP(no, max_no);
  211. no = DIV_ROUND_UP(no, *ext_div);
  212. }
  213. /* only even divisors (and 1) are supported */
  214. if (no > 1)
  215. no = DIV_ROUND_UP(no, 2) * 2;
  216. vco_khz = freq_khz * no;
  217. if (ext_div)
  218. vco_khz *= *ext_div;
  219. if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || no > max_no) {
  220. printf("%s: Cannot find out a supported VCO for Frequency (%luHz).\n",
  221. __func__, freq_hz);
  222. return -1;
  223. }
  224. div->no = no;
  225. best_diff_khz = vco_khz;
  226. for (nr = 1; nr < max_nr && best_diff_khz; nr++) {
  227. fref_khz = ref_khz / nr;
  228. if (fref_khz < FREF_MIN_KHZ)
  229. break;
  230. if (fref_khz > FREF_MAX_KHZ)
  231. continue;
  232. nf = vco_khz / fref_khz;
  233. if (nf >= max_nf)
  234. continue;
  235. diff_khz = vco_khz - nf * fref_khz;
  236. if (nf + 1 < max_nf && diff_khz > fref_khz / 2) {
  237. nf++;
  238. diff_khz = fref_khz - diff_khz;
  239. }
  240. if (diff_khz >= best_diff_khz)
  241. continue;
  242. best_diff_khz = diff_khz;
  243. div->nr = nr;
  244. div->nf = nf;
  245. }
  246. if (best_diff_khz > 4 * 1000) {
  247. printf("%s: Failed to match output frequency %lu, difference is %u Hz, exceed 4MHZ\n",
  248. __func__, freq_hz, best_diff_khz * 1000);
  249. return -EINVAL;
  250. }
  251. return 0;
  252. }
  253. static int rockchip_mac_set_clk(struct rockchip_cru *cru, uint freq)
  254. {
  255. ulong ret;
  256. /*
  257. * The gmac clock can be derived either from an external clock
  258. * or can be generated from internally by a divider from SCLK_MAC.
  259. */
  260. if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) {
  261. /* An external clock will always generate the right rate... */
  262. ret = freq;
  263. } else {
  264. u32 con = readl(&cru->cru_clksel_con[21]);
  265. ulong pll_rate;
  266. u8 div;
  267. if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
  268. EMAC_PLL_SELECT_GENERAL)
  269. pll_rate = GPLL_HZ;
  270. else if (((con >> EMAC_PLL_SHIFT) & EMAC_PLL_MASK) ==
  271. EMAC_PLL_SELECT_CODEC)
  272. pll_rate = CPLL_HZ;
  273. else
  274. pll_rate = NPLL_HZ;
  275. div = DIV_ROUND_UP(pll_rate, freq) - 1;
  276. if (div <= 0x1f)
  277. rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK,
  278. div << MAC_DIV_CON_SHIFT);
  279. else
  280. debug("Unsupported div for gmac:%d\n", div);
  281. return DIV_TO_RATE(pll_rate, div);
  282. }
  283. return ret;
  284. }
  285. static int rockchip_vop_set_clk(struct rockchip_cru *cru, struct rk3288_grf *grf,
  286. int periph, unsigned int rate_hz)
  287. {
  288. struct pll_div npll_config = {0};
  289. u32 lcdc_div;
  290. int ret;
  291. ret = pll_para_config(rate_hz, &npll_config, &lcdc_div);
  292. if (ret)
  293. return ret;
  294. rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
  295. NPLL_MODE_SLOW << NPLL_MODE_SHIFT);
  296. rkclk_set_pll(cru, CLK_NEW, &npll_config);
  297. /* waiting for pll lock */
  298. while (1) {
  299. if (readl(&grf->soc_status[1]) & SOCSTS_NPLL_LOCK)
  300. break;
  301. udelay(1);
  302. }
  303. rk_clrsetreg(&cru->cru_mode_con, NPLL_MODE_MASK,
  304. NPLL_MODE_NORMAL << NPLL_MODE_SHIFT);
  305. /* vop dclk source clk: npll,dclk_div: 1 */
  306. switch (periph) {
  307. case DCLK_VOP0:
  308. rk_clrsetreg(&cru->cru_clksel_con[27], 0xff << 8 | 3 << 0,
  309. (lcdc_div - 1) << 8 | 2 << 0);
  310. break;
  311. case DCLK_VOP1:
  312. rk_clrsetreg(&cru->cru_clksel_con[29], 0xff << 8 | 3 << 6,
  313. (lcdc_div - 1) << 8 | 2 << 6);
  314. break;
  315. }
  316. return 0;
  317. }
  318. static u32 rockchip_clk_gcd(u32 a, u32 b)
  319. {
  320. while (b != 0) {
  321. int r = b;
  322. b = a % b;
  323. a = r;
  324. }
  325. return a;
  326. }
  327. static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate)
  328. {
  329. unsigned long long rate;
  330. uint val;
  331. int n, d;
  332. val = readl(&cru->cru_clksel_con[8]);
  333. n = (val & I2S0_FRAC_NUMER_MASK) >> I2S0_FRAC_NUMER_SHIFT;
  334. d = (val & I2S0_FRAC_DENOM_MASK) >> I2S0_FRAC_DENOM_SHIFT;
  335. rate = (unsigned long long)gclk_rate * n;
  336. do_div(rate, d);
  337. return (ulong)rate;
  338. }
  339. static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate,
  340. uint freq)
  341. {
  342. int n, d;
  343. int v;
  344. /* set frac divider */
  345. v = rockchip_clk_gcd(gclk_rate, freq);
  346. n = gclk_rate / v;
  347. d = freq / v;
  348. assert(freq == gclk_rate / n * d);
  349. writel(d << I2S0_FRAC_NUMER_SHIFT | n << I2S0_FRAC_DENOM_SHIFT,
  350. &cru->cru_clksel_con[8]);
  351. return rockchip_i2s_get_clk(cru, gclk_rate);
  352. }
  353. #endif /* CONFIG_SPL_BUILD */
  354. static void rkclk_init(struct rockchip_cru *cru, struct rk3288_grf *grf)
  355. {
  356. u32 aclk_div;
  357. u32 hclk_div;
  358. u32 pclk_div;
  359. /* pll enter slow-mode */
  360. rk_clrsetreg(&cru->cru_mode_con,
  361. GPLL_MODE_MASK | CPLL_MODE_MASK,
  362. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  363. CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
  364. /* init pll */
  365. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  366. rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
  367. /* waiting for pll lock */
  368. while ((readl(&grf->soc_status[1]) &
  369. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) !=
  370. (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK))
  371. udelay(1);
  372. /*
  373. * pd_bus clock pll source selection and
  374. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  375. */
  376. aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1;
  377. assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  378. hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1;
  379. assert((hclk_div + 1) * PD_BUS_HCLK_HZ ==
  380. PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2));
  381. pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1;
  382. assert((pclk_div + 1) * PD_BUS_PCLK_HZ ==
  383. PD_BUS_ACLK_HZ && pclk_div < 0x7);
  384. rk_clrsetreg(&cru->cru_clksel_con[1],
  385. PD_BUS_PCLK_DIV_MASK | PD_BUS_HCLK_DIV_MASK |
  386. PD_BUS_ACLK_DIV0_MASK | PD_BUS_ACLK_DIV1_MASK,
  387. pclk_div << PD_BUS_PCLK_DIV_SHIFT |
  388. hclk_div << PD_BUS_HCLK_DIV_SHIFT |
  389. aclk_div << PD_BUS_ACLK_DIV0_SHIFT |
  390. 0 << 0);
  391. /*
  392. * peri clock pll source selection and
  393. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  394. */
  395. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  396. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  397. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  398. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  399. PERI_ACLK_HZ && (hclk_div < 0x4));
  400. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  401. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  402. PERI_ACLK_HZ && (pclk_div < 0x4));
  403. rk_clrsetreg(&cru->cru_clksel_con[10],
  404. PERI_PCLK_DIV_MASK | PERI_HCLK_DIV_MASK |
  405. PERI_ACLK_DIV_MASK,
  406. PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT |
  407. pclk_div << PERI_PCLK_DIV_SHIFT |
  408. hclk_div << PERI_HCLK_DIV_SHIFT |
  409. aclk_div << PERI_ACLK_DIV_SHIFT);
  410. /* PLL enter normal-mode */
  411. rk_clrsetreg(&cru->cru_mode_con,
  412. GPLL_MODE_MASK | CPLL_MODE_MASK,
  413. GPLL_MODE_NORMAL << GPLL_MODE_SHIFT |
  414. CPLL_MODE_NORMAL << CPLL_MODE_SHIFT);
  415. }
  416. void rk3288_clk_configure_cpu(struct rockchip_cru *cru, struct rk3288_grf *grf)
  417. {
  418. /* pll enter slow-mode */
  419. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
  420. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  421. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  422. /* waiting for pll lock */
  423. while (!(readl(&grf->soc_status[1]) & SOCSTS_APLL_LOCK))
  424. udelay(1);
  425. /*
  426. * core clock pll source selection and
  427. * set up dependent divisors for MPAXI/M0AXI and ARM clocks.
  428. * core clock select apll, apll clk = 1800MHz
  429. * arm clk = 1800MHz, mpclk = 450MHz, m0clk = 900MHz
  430. */
  431. rk_clrsetreg(&cru->cru_clksel_con[0],
  432. CORE_SEL_PLL_MASK | A17_DIV_MASK | MP_DIV_MASK |
  433. M0_DIV_MASK,
  434. 0 << A17_DIV_SHIFT |
  435. 3 << MP_DIV_SHIFT |
  436. 1 << M0_DIV_SHIFT);
  437. /*
  438. * set up dependent divisors for L2RAM/ATCLK and PCLK clocks.
  439. * l2ramclk = 900MHz, atclk = 450MHz, pclk_dbg = 450MHz
  440. */
  441. rk_clrsetreg(&cru->cru_clksel_con[37],
  442. CLK_L2RAM_DIV_MASK | ATCLK_CORE_DIV_CON_MASK |
  443. PCLK_CORE_DBG_DIV_MASK,
  444. 1 << CLK_L2RAM_DIV_SHIFT |
  445. 3 << ATCLK_CORE_DIV_CON_SHIFT |
  446. 3 << PCLK_CORE_DBG_DIV_SHIFT);
  447. /* PLL enter normal-mode */
  448. rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK,
  449. APLL_MODE_NORMAL << APLL_MODE_SHIFT);
  450. }
  451. /* Get pll rate by id */
  452. static uint32_t rkclk_pll_get_rate(struct rockchip_cru *cru,
  453. enum rk_clk_id clk_id)
  454. {
  455. uint32_t nr, no, nf;
  456. uint32_t con;
  457. int pll_id = rk_pll_id(clk_id);
  458. struct rk3288_pll *pll = &cru->pll[pll_id];
  459. static u8 clk_shift[CLK_COUNT] = {
  460. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  461. GPLL_MODE_SHIFT, NPLL_MODE_SHIFT
  462. };
  463. uint shift;
  464. con = readl(&cru->cru_mode_con);
  465. shift = clk_shift[clk_id];
  466. switch ((con >> shift) & CRU_MODE_MASK) {
  467. case APLL_MODE_SLOW:
  468. return OSC_HZ;
  469. case APLL_MODE_NORMAL:
  470. /* normal mode */
  471. con = readl(&pll->con0);
  472. no = ((con & CLKOD_MASK) >> CLKOD_SHIFT) + 1;
  473. nr = ((con & CLKR_MASK) >> CLKR_SHIFT) + 1;
  474. con = readl(&pll->con1);
  475. nf = ((con & CLKF_MASK) >> CLKF_SHIFT) + 1;
  476. return (24 * nf / (nr * no)) * 1000000;
  477. case APLL_MODE_DEEP:
  478. default:
  479. return 32768;
  480. }
  481. }
  482. static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate,
  483. int periph)
  484. {
  485. uint src_rate;
  486. uint div, mux;
  487. u32 con;
  488. switch (periph) {
  489. case HCLK_EMMC:
  490. case SCLK_EMMC:
  491. con = readl(&cru->cru_clksel_con[12]);
  492. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  493. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  494. break;
  495. case HCLK_SDMMC:
  496. case SCLK_SDMMC:
  497. con = readl(&cru->cru_clksel_con[11]);
  498. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  499. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  500. break;
  501. case HCLK_SDIO0:
  502. case SCLK_SDIO0:
  503. con = readl(&cru->cru_clksel_con[12]);
  504. mux = (con & SDIO0_PLL_MASK) >> SDIO0_PLL_SHIFT;
  505. div = (con & SDIO0_DIV_MASK) >> SDIO0_DIV_SHIFT;
  506. break;
  507. default:
  508. return -EINVAL;
  509. }
  510. src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
  511. return DIV_TO_RATE(src_rate, div);
  512. }
  513. static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate,
  514. int periph, uint freq)
  515. {
  516. int src_clk_div;
  517. int mux;
  518. debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
  519. /* mmc clock default div 2 internal, need provide double in cru */
  520. src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq);
  521. if (src_clk_div > 0x3f) {
  522. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  523. assert(src_clk_div < 0x40);
  524. mux = EMMC_PLL_SELECT_24MHZ;
  525. assert((int)EMMC_PLL_SELECT_24MHZ ==
  526. (int)MMC0_PLL_SELECT_24MHZ);
  527. } else {
  528. mux = EMMC_PLL_SELECT_GENERAL;
  529. assert((int)EMMC_PLL_SELECT_GENERAL ==
  530. (int)MMC0_PLL_SELECT_GENERAL);
  531. }
  532. switch (periph) {
  533. case HCLK_EMMC:
  534. case SCLK_EMMC:
  535. rk_clrsetreg(&cru->cru_clksel_con[12],
  536. EMMC_PLL_MASK | EMMC_DIV_MASK,
  537. mux << EMMC_PLL_SHIFT |
  538. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  539. break;
  540. case HCLK_SDMMC:
  541. case SCLK_SDMMC:
  542. rk_clrsetreg(&cru->cru_clksel_con[11],
  543. MMC0_PLL_MASK | MMC0_DIV_MASK,
  544. mux << MMC0_PLL_SHIFT |
  545. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  546. break;
  547. case HCLK_SDIO0:
  548. case SCLK_SDIO0:
  549. rk_clrsetreg(&cru->cru_clksel_con[12],
  550. SDIO0_PLL_MASK | SDIO0_DIV_MASK,
  551. mux << SDIO0_PLL_SHIFT |
  552. (src_clk_div - 1) << SDIO0_DIV_SHIFT);
  553. break;
  554. default:
  555. return -EINVAL;
  556. }
  557. return rockchip_mmc_get_clk(cru, gclk_rate, periph);
  558. }
  559. static ulong rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate,
  560. int periph)
  561. {
  562. uint div, mux;
  563. u32 con;
  564. switch (periph) {
  565. case SCLK_SPI0:
  566. con = readl(&cru->cru_clksel_con[25]);
  567. mux = (con & SPI0_PLL_MASK) >> SPI0_PLL_SHIFT;
  568. div = (con & SPI0_DIV_MASK) >> SPI0_DIV_SHIFT;
  569. break;
  570. case SCLK_SPI1:
  571. con = readl(&cru->cru_clksel_con[25]);
  572. mux = (con & SPI1_PLL_MASK) >> SPI1_PLL_SHIFT;
  573. div = (con & SPI1_DIV_MASK) >> SPI1_DIV_SHIFT;
  574. break;
  575. case SCLK_SPI2:
  576. con = readl(&cru->cru_clksel_con[39]);
  577. mux = (con & SPI2_PLL_MASK) >> SPI2_PLL_SHIFT;
  578. div = (con & SPI2_DIV_MASK) >> SPI2_DIV_SHIFT;
  579. break;
  580. default:
  581. return -EINVAL;
  582. }
  583. assert(mux == SPI0_PLL_SELECT_GENERAL);
  584. return DIV_TO_RATE(gclk_rate, div);
  585. }
  586. static ulong rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate,
  587. int periph, uint freq)
  588. {
  589. int src_clk_div;
  590. debug("%s: clk_general_rate=%u\n", __func__, gclk_rate);
  591. src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1;
  592. assert(src_clk_div < 128);
  593. switch (periph) {
  594. case SCLK_SPI0:
  595. rk_clrsetreg(&cru->cru_clksel_con[25],
  596. SPI0_PLL_MASK | SPI0_DIV_MASK,
  597. SPI0_PLL_SELECT_GENERAL << SPI0_PLL_SHIFT |
  598. src_clk_div << SPI0_DIV_SHIFT);
  599. break;
  600. case SCLK_SPI1:
  601. rk_clrsetreg(&cru->cru_clksel_con[25],
  602. SPI1_PLL_MASK | SPI1_DIV_MASK,
  603. SPI1_PLL_SELECT_GENERAL << SPI1_PLL_SHIFT |
  604. src_clk_div << SPI1_DIV_SHIFT);
  605. break;
  606. case SCLK_SPI2:
  607. rk_clrsetreg(&cru->cru_clksel_con[39],
  608. SPI2_PLL_MASK | SPI2_DIV_MASK,
  609. SPI2_PLL_SELECT_GENERAL << SPI2_PLL_SHIFT |
  610. src_clk_div << SPI2_DIV_SHIFT);
  611. break;
  612. default:
  613. return -EINVAL;
  614. }
  615. return rockchip_spi_get_clk(cru, gclk_rate, periph);
  616. }
  617. static ulong rockchip_saradc_get_clk(struct rockchip_cru *cru)
  618. {
  619. u32 div, val;
  620. val = readl(&cru->cru_clksel_con[24]);
  621. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  622. CLK_SARADC_DIV_CON_WIDTH);
  623. return DIV_TO_RATE(OSC_HZ, div);
  624. }
  625. static ulong rockchip_saradc_set_clk(struct rockchip_cru *cru, uint hz)
  626. {
  627. int src_clk_div;
  628. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  629. assert(src_clk_div < 128);
  630. rk_clrsetreg(&cru->cru_clksel_con[24],
  631. CLK_SARADC_DIV_CON_MASK,
  632. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  633. return rockchip_saradc_get_clk(cru);
  634. }
  635. static ulong rk3288_clk_get_rate(struct clk *clk)
  636. {
  637. struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
  638. ulong new_rate, gclk_rate;
  639. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  640. switch (clk->id) {
  641. case 0 ... 63:
  642. new_rate = rkclk_pll_get_rate(priv->cru, clk->id);
  643. break;
  644. case HCLK_EMMC:
  645. case HCLK_SDMMC:
  646. case HCLK_SDIO0:
  647. case SCLK_EMMC:
  648. case SCLK_SDMMC:
  649. case SCLK_SDIO0:
  650. new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
  651. break;
  652. case SCLK_SPI0:
  653. case SCLK_SPI1:
  654. case SCLK_SPI2:
  655. new_rate = rockchip_spi_get_clk(priv->cru, gclk_rate, clk->id);
  656. break;
  657. case PCLK_I2C0:
  658. case PCLK_I2C1:
  659. case PCLK_I2C2:
  660. case PCLK_I2C3:
  661. case PCLK_I2C4:
  662. case PCLK_I2C5:
  663. return gclk_rate;
  664. case PCLK_PWM:
  665. return PD_BUS_PCLK_HZ;
  666. case SCLK_SARADC:
  667. new_rate = rockchip_saradc_get_clk(priv->cru);
  668. break;
  669. default:
  670. return -ENOENT;
  671. }
  672. return new_rate;
  673. }
  674. static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
  675. {
  676. struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
  677. struct rockchip_cru *cru = priv->cru;
  678. ulong new_rate, gclk_rate;
  679. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  680. switch (clk->id) {
  681. case PLL_APLL:
  682. /* We only support a fixed rate here */
  683. if (rate != 1800000000)
  684. return -EINVAL;
  685. rk3288_clk_configure_cpu(priv->cru, priv->grf);
  686. new_rate = rate;
  687. break;
  688. case CLK_DDR:
  689. new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate);
  690. break;
  691. case HCLK_EMMC:
  692. case HCLK_SDMMC:
  693. case HCLK_SDIO0:
  694. case SCLK_EMMC:
  695. case SCLK_SDMMC:
  696. case SCLK_SDIO0:
  697. new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
  698. break;
  699. case SCLK_SPI0:
  700. case SCLK_SPI1:
  701. case SCLK_SPI2:
  702. new_rate = rockchip_spi_set_clk(cru, gclk_rate, clk->id, rate);
  703. break;
  704. #ifndef CONFIG_SPL_BUILD
  705. case SCLK_I2S0:
  706. new_rate = rockchip_i2s_set_clk(cru, gclk_rate, rate);
  707. break;
  708. case SCLK_MAC:
  709. new_rate = rockchip_mac_set_clk(priv->cru, rate);
  710. break;
  711. case DCLK_VOP0:
  712. case DCLK_VOP1:
  713. new_rate = rockchip_vop_set_clk(cru, priv->grf, clk->id, rate);
  714. break;
  715. case SCLK_EDP_24M:
  716. /* clk_edp_24M source: 24M */
  717. rk_setreg(&cru->cru_clksel_con[28], 1 << 15);
  718. /* rst edp */
  719. rk_setreg(&cru->cru_clksel_con[6], 1 << 15);
  720. udelay(1);
  721. rk_clrreg(&cru->cru_clksel_con[6], 1 << 15);
  722. new_rate = rate;
  723. break;
  724. case ACLK_VOP0:
  725. case ACLK_VOP1: {
  726. u32 div;
  727. /* vop aclk source clk: cpll */
  728. div = CPLL_HZ / rate;
  729. assert((div - 1 < 64) && (div * rate == CPLL_HZ));
  730. switch (clk->id) {
  731. case ACLK_VOP0:
  732. rk_clrsetreg(&cru->cru_clksel_con[31],
  733. 3 << 6 | 0x1f << 0,
  734. 0 << 6 | (div - 1) << 0);
  735. break;
  736. case ACLK_VOP1:
  737. rk_clrsetreg(&cru->cru_clksel_con[31],
  738. 3 << 14 | 0x1f << 8,
  739. 0 << 14 | (div - 1) << 8);
  740. break;
  741. }
  742. new_rate = rate;
  743. break;
  744. }
  745. case PCLK_HDMI_CTRL:
  746. /* enable pclk hdmi ctrl */
  747. rk_clrreg(&cru->cru_clkgate_con[16], 1 << 9);
  748. /* software reset hdmi */
  749. rk_setreg(&cru->cru_clkgate_con[7], 1 << 9);
  750. udelay(1);
  751. rk_clrreg(&cru->cru_clkgate_con[7], 1 << 9);
  752. new_rate = rate;
  753. break;
  754. #endif
  755. case SCLK_SARADC:
  756. new_rate = rockchip_saradc_set_clk(priv->cru, rate);
  757. break;
  758. case PLL_GPLL:
  759. case PLL_CPLL:
  760. case PLL_NPLL:
  761. case ACLK_CPU:
  762. case HCLK_CPU:
  763. case PCLK_CPU:
  764. case ACLK_PERI:
  765. case HCLK_PERI:
  766. case PCLK_PERI:
  767. case SCLK_UART0:
  768. return 0;
  769. default:
  770. return -ENOENT;
  771. }
  772. return new_rate;
  773. }
  774. static int __maybe_unused rk3288_gmac_set_parent(struct clk *clk, struct clk *parent)
  775. {
  776. struct rk3288_clk_priv *priv = dev_get_priv(clk->dev);
  777. struct rockchip_cru *cru = priv->cru;
  778. const char *clock_output_name;
  779. int ret;
  780. /*
  781. * If the requested parent is in the same clock-controller and
  782. * the id is SCLK_MAC_PLL ("mac_pll_src"), switch to the internal
  783. * clock.
  784. */
  785. if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_PLL)) {
  786. debug("%s: switching GAMC to SCLK_MAC_PLL\n", __func__);
  787. rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK, 0);
  788. return 0;
  789. }
  790. /*
  791. * Otherwise, we need to check the clock-output-names of the
  792. * requested parent to see if the requested id is "ext_gmac".
  793. */
  794. ret = dev_read_string_index(parent->dev, "clock-output-names",
  795. parent->id, &clock_output_name);
  796. if (ret < 0)
  797. return -ENODATA;
  798. /* If this is "ext_gmac", switch to the external clock input */
  799. if (!strcmp(clock_output_name, "ext_gmac")) {
  800. debug("%s: switching GMAC to external clock\n", __func__);
  801. rk_clrsetreg(&cru->cru_clksel_con[21], RMII_EXTCLK_MASK,
  802. RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
  803. return 0;
  804. }
  805. return -EINVAL;
  806. }
  807. static int __maybe_unused rk3288_clk_set_parent(struct clk *clk, struct clk *parent)
  808. {
  809. switch (clk->id) {
  810. case SCLK_MAC:
  811. return rk3288_gmac_set_parent(clk, parent);
  812. case SCLK_USBPHY480M_SRC:
  813. return 0;
  814. }
  815. debug("%s: unsupported clk %ld\n", __func__, clk->id);
  816. return -ENOENT;
  817. }
  818. static struct clk_ops rk3288_clk_ops = {
  819. .get_rate = rk3288_clk_get_rate,
  820. .set_rate = rk3288_clk_set_rate,
  821. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  822. .set_parent = rk3288_clk_set_parent,
  823. #endif
  824. };
  825. static int rk3288_clk_of_to_plat(struct udevice *dev)
  826. {
  827. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  828. struct rk3288_clk_priv *priv = dev_get_priv(dev);
  829. priv->cru = dev_read_addr_ptr(dev);
  830. #endif
  831. return 0;
  832. }
  833. static int rk3288_clk_probe(struct udevice *dev)
  834. {
  835. struct rk3288_clk_priv *priv = dev_get_priv(dev);
  836. bool init_clocks = false;
  837. priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  838. if (IS_ERR(priv->grf))
  839. return PTR_ERR(priv->grf);
  840. #ifdef CONFIG_SPL_BUILD
  841. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  842. struct rk3288_clk_plat *plat = dev_get_plat(dev);
  843. priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]);
  844. #endif
  845. init_clocks = true;
  846. #endif
  847. if (!(gd->flags & GD_FLG_RELOC)) {
  848. u32 reg;
  849. /*
  850. * Init clocks in U-Boot proper if the NPLL is runnning. This
  851. * indicates that a previous boot loader set up the clocks, so
  852. * we need to redo it. U-Boot's SPL does not set this clock.
  853. */
  854. reg = readl(&priv->cru->cru_mode_con);
  855. if (((reg & NPLL_MODE_MASK) >> NPLL_MODE_SHIFT) ==
  856. NPLL_MODE_NORMAL)
  857. init_clocks = true;
  858. }
  859. if (init_clocks)
  860. rkclk_init(priv->cru, priv->grf);
  861. return 0;
  862. }
  863. static int rk3288_clk_bind(struct udevice *dev)
  864. {
  865. int ret;
  866. struct udevice *sys_child;
  867. struct sysreset_reg *priv;
  868. /* The reset driver does not have a device node, so bind it here */
  869. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  870. &sys_child);
  871. if (ret) {
  872. debug("Warning: No sysreset driver: ret=%d\n", ret);
  873. } else {
  874. priv = malloc(sizeof(struct sysreset_reg));
  875. priv->glb_srst_fst_value = offsetof(struct rockchip_cru,
  876. cru_glb_srst_fst_value);
  877. priv->glb_srst_snd_value = offsetof(struct rockchip_cru,
  878. cru_glb_srst_snd_value);
  879. dev_set_priv(sys_child, priv);
  880. }
  881. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  882. ret = offsetof(struct rockchip_cru, cru_softrst_con[0]);
  883. ret = rockchip_reset_bind(dev, ret, 12);
  884. if (ret)
  885. debug("Warning: software reset driver bind faile\n");
  886. #endif
  887. return 0;
  888. }
  889. static const struct udevice_id rk3288_clk_ids[] = {
  890. { .compatible = "rockchip,rk3288-cru" },
  891. { }
  892. };
  893. U_BOOT_DRIVER(rockchip_rk3288_cru) = {
  894. .name = "rockchip_rk3288_cru",
  895. .id = UCLASS_CLK,
  896. .of_match = rk3288_clk_ids,
  897. .priv_auto = sizeof(struct rk3288_clk_priv),
  898. .plat_auto = sizeof(struct rk3288_clk_plat),
  899. .ops = &rk3288_clk_ops,
  900. .bind = rk3288_clk_bind,
  901. .of_to_plat = rk3288_clk_of_to_plat,
  902. .probe = rk3288_clk_probe,
  903. };