clk_rk3128.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2017 Rockchip Electronics Co., Ltd
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk3128.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <bitfield.h>
  17. #include <dm/device-internal.h>
  18. #include <dm/lists.h>
  19. #include <dt-bindings/clock/rk3128-cru.h>
  20. #include <linux/delay.h>
  21. #include <linux/log2.h>
  22. enum {
  23. VCO_MAX_HZ = 2400U * 1000000,
  24. VCO_MIN_HZ = 600 * 1000000,
  25. OUTPUT_MAX_HZ = 2400U * 1000000,
  26. OUTPUT_MIN_HZ = 24 * 1000000,
  27. };
  28. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  29. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  30. .refdiv = _refdiv,\
  31. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  32. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
  33. /* use integer mode*/
  34. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  35. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  36. static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id,
  37. const struct pll_div *div)
  38. {
  39. int pll_id = rk_pll_id(clk_id);
  40. struct rk3128_pll *pll = &cru->pll[pll_id];
  41. /* All PLLs have same VCO and output frequency range restrictions. */
  42. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  43. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  44. debug("PLL at %p:fd=%d,rd=%d,pd1=%d,pd2=%d,vco=%uHz,output=%uHz\n",
  45. pll, div->fbdiv, div->refdiv, div->postdiv1,
  46. div->postdiv2, vco_hz, output_hz);
  47. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  48. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  49. /* use integer mode */
  50. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  51. /* Power down */
  52. rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
  53. rk_clrsetreg(&pll->con0,
  54. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  55. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  56. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  57. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  58. div->refdiv << PLL_REFDIV_SHIFT));
  59. /* Power Up */
  60. rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
  61. /* waiting for pll lock */
  62. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  63. udelay(1);
  64. return 0;
  65. }
  66. static int pll_para_config(u32 freq_hz, struct pll_div *div)
  67. {
  68. u32 ref_khz = OSC_HZ / 1000, refdiv, fbdiv = 0;
  69. u32 postdiv1, postdiv2 = 1;
  70. u32 fref_khz;
  71. u32 diff_khz, best_diff_khz;
  72. const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16;
  73. const u32 max_postdiv1 = 7, max_postdiv2 = 7;
  74. u32 vco_khz;
  75. u32 freq_khz = freq_hz / 1000;
  76. if (!freq_hz) {
  77. printf("%s: the frequency can't be 0 Hz\n", __func__);
  78. return -1;
  79. }
  80. postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz);
  81. if (postdiv1 > max_postdiv1) {
  82. postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1);
  83. postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2);
  84. }
  85. vco_khz = freq_khz * postdiv1 * postdiv2;
  86. if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) ||
  87. postdiv2 > max_postdiv2) {
  88. printf("%s: Cannot find out a supported VCO for Freq (%uHz)\n",
  89. __func__, freq_hz);
  90. return -1;
  91. }
  92. div->postdiv1 = postdiv1;
  93. div->postdiv2 = postdiv2;
  94. best_diff_khz = vco_khz;
  95. for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) {
  96. fref_khz = ref_khz / refdiv;
  97. fbdiv = vco_khz / fref_khz;
  98. if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))
  99. continue;
  100. diff_khz = vco_khz - fbdiv * fref_khz;
  101. if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {
  102. fbdiv++;
  103. diff_khz = fref_khz - diff_khz;
  104. }
  105. if (diff_khz >= best_diff_khz)
  106. continue;
  107. best_diff_khz = diff_khz;
  108. div->refdiv = refdiv;
  109. div->fbdiv = fbdiv;
  110. }
  111. if (best_diff_khz > 4 * (1000)) {
  112. printf("%s: Failed to match output frequency %u bestis %u Hz\n",
  113. __func__, freq_hz,
  114. best_diff_khz * 1000);
  115. return -1;
  116. }
  117. return 0;
  118. }
  119. static void rkclk_init(struct rk3128_cru *cru)
  120. {
  121. u32 aclk_div;
  122. u32 hclk_div;
  123. u32 pclk_div;
  124. /* pll enter slow-mode */
  125. rk_clrsetreg(&cru->cru_mode_con,
  126. GPLL_MODE_MASK | APLL_MODE_MASK,
  127. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  128. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  129. /* init pll */
  130. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  131. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  132. /*
  133. * select apll as cpu/core clock pll source and
  134. * set up dependent divisors for PERI and ACLK clocks.
  135. * core hz : apll = 1:1
  136. */
  137. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  138. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  139. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  140. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  141. rk_clrsetreg(&cru->cru_clksel_con[0],
  142. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  143. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  144. 0 << CORE_DIV_CON_SHIFT);
  145. rk_clrsetreg(&cru->cru_clksel_con[1],
  146. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  147. aclk_div << CORE_ACLK_DIV_SHIFT |
  148. pclk_div << CORE_PERI_DIV_SHIFT);
  149. /*
  150. * select gpll as pd_bus bus clock source and
  151. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  152. */
  153. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  154. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  155. pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
  156. assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
  157. hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
  158. assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
  159. rk_clrsetreg(&cru->cru_clksel_con[0],
  160. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  161. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  162. aclk_div << BUS_ACLK_DIV_SHIFT);
  163. rk_clrsetreg(&cru->cru_clksel_con[1],
  164. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  165. pclk_div << BUS_PCLK_DIV_SHIFT |
  166. hclk_div << BUS_HCLK_DIV_SHIFT);
  167. /*
  168. * select gpll as pd_peri bus clock source and
  169. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  170. */
  171. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  172. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  173. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  174. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  175. PERI_ACLK_HZ && (hclk_div < 0x4));
  176. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  177. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  178. PERI_ACLK_HZ && pclk_div < 0x8);
  179. rk_clrsetreg(&cru->cru_clksel_con[10],
  180. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  181. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  182. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  183. pclk_div << PERI_PCLK_DIV_SHIFT |
  184. hclk_div << PERI_HCLK_DIV_SHIFT |
  185. aclk_div << PERI_ACLK_DIV_SHIFT);
  186. /* PLL enter normal-mode */
  187. rk_clrsetreg(&cru->cru_mode_con,
  188. GPLL_MODE_MASK | APLL_MODE_MASK | CPLL_MODE_MASK,
  189. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  190. APLL_MODE_NORM << APLL_MODE_SHIFT |
  191. CPLL_MODE_NORM << CPLL_MODE_SHIFT);
  192. /*fix NAND controller working clock max to 150Mhz */
  193. rk_clrsetreg(&cru->cru_clksel_con[2],
  194. NANDC_PLL_SEL_MASK | NANDC_CLK_DIV_MASK,
  195. NANDC_PLL_SEL_GPLL << NANDC_PLL_SEL_SHIFT |
  196. 3 << NANDC_CLK_DIV_SHIFT);
  197. }
  198. /* Get pll rate by id */
  199. static u32 rkclk_pll_get_rate(struct rk3128_cru *cru,
  200. enum rk_clk_id clk_id)
  201. {
  202. u32 refdiv, fbdiv, postdiv1, postdiv2;
  203. u32 con;
  204. int pll_id = rk_pll_id(clk_id);
  205. struct rk3128_pll *pll = &cru->pll[pll_id];
  206. static u8 clk_shift[CLK_COUNT] = {
  207. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT,
  208. GPLL_MODE_SHIFT, 0xff
  209. };
  210. static u32 clk_mask[CLK_COUNT] = {
  211. 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, CPLL_MODE_MASK,
  212. GPLL_MODE_MASK, 0xff
  213. };
  214. uint shift;
  215. uint mask;
  216. con = readl(&cru->cru_mode_con);
  217. shift = clk_shift[clk_id];
  218. mask = clk_mask[clk_id];
  219. switch ((con & mask) >> shift) {
  220. case GPLL_MODE_SLOW:
  221. return OSC_HZ;
  222. case GPLL_MODE_NORM:
  223. /* normal mode */
  224. con = readl(&pll->con0);
  225. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  226. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  227. con = readl(&pll->con1);
  228. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  229. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  230. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  231. case GPLL_MODE_DEEP:
  232. default:
  233. return 32768;
  234. }
  235. }
  236. static ulong rockchip_mmc_get_clk(struct rk3128_cru *cru, uint clk_general_rate,
  237. int periph)
  238. {
  239. uint src_rate;
  240. uint div, mux;
  241. u32 con;
  242. switch (periph) {
  243. case HCLK_EMMC:
  244. case SCLK_EMMC:
  245. case SCLK_EMMC_SAMPLE:
  246. con = readl(&cru->cru_clksel_con[12]);
  247. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  248. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  249. break;
  250. case HCLK_SDMMC:
  251. case SCLK_SDMMC:
  252. con = readl(&cru->cru_clksel_con[11]);
  253. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  254. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  255. break;
  256. default:
  257. return -EINVAL;
  258. }
  259. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  260. return DIV_TO_RATE(src_rate, div);
  261. }
  262. static ulong rockchip_mmc_set_clk(struct rk3128_cru *cru, uint clk_general_rate,
  263. int periph, uint freq)
  264. {
  265. int src_clk_div;
  266. int mux;
  267. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  268. /* mmc clock defaulg div 2 internal, need provide double in cru */
  269. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  270. if (src_clk_div > 128) {
  271. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  272. mux = EMMC_SEL_24M;
  273. } else {
  274. mux = EMMC_SEL_GPLL;
  275. }
  276. switch (periph) {
  277. case HCLK_EMMC:
  278. rk_clrsetreg(&cru->cru_clksel_con[12],
  279. EMMC_PLL_MASK | EMMC_DIV_MASK,
  280. mux << EMMC_PLL_SHIFT |
  281. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  282. break;
  283. case HCLK_SDMMC:
  284. case SCLK_SDMMC:
  285. rk_clrsetreg(&cru->cru_clksel_con[11],
  286. MMC0_PLL_MASK | MMC0_DIV_MASK,
  287. mux << MMC0_PLL_SHIFT |
  288. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  289. break;
  290. default:
  291. return -EINVAL;
  292. }
  293. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  294. }
  295. static ulong rk3128_peri_get_pclk(struct rk3128_cru *cru, ulong clk_id)
  296. {
  297. u32 div, con;
  298. switch (clk_id) {
  299. case PCLK_I2C0:
  300. case PCLK_I2C1:
  301. case PCLK_I2C2:
  302. case PCLK_I2C3:
  303. case PCLK_PWM:
  304. con = readl(&cru->cru_clksel_con[10]);
  305. div = con >> 12 & 0x3;
  306. break;
  307. default:
  308. printf("do not support this peripheral bus\n");
  309. return -EINVAL;
  310. }
  311. return DIV_TO_RATE(PERI_ACLK_HZ, div);
  312. }
  313. static ulong rk3128_peri_set_pclk(struct rk3128_cru *cru, ulong clk_id, uint hz)
  314. {
  315. int src_clk_div;
  316. src_clk_div = PERI_ACLK_HZ / hz;
  317. assert(src_clk_div - 1 < 4);
  318. switch (clk_id) {
  319. case PCLK_I2C0:
  320. case PCLK_I2C1:
  321. case PCLK_I2C2:
  322. case PCLK_I2C3:
  323. case PCLK_PWM:
  324. rk_setreg(&cru->cru_clksel_con[10],
  325. ((src_clk_div - 1) << 12));
  326. break;
  327. default:
  328. printf("do not support this peripheral bus\n");
  329. return -EINVAL;
  330. }
  331. return DIV_TO_RATE(PERI_ACLK_HZ, src_clk_div);
  332. }
  333. static ulong rk3128_saradc_get_clk(struct rk3128_cru *cru)
  334. {
  335. u32 div, val;
  336. val = readl(&cru->cru_clksel_con[24]);
  337. div = bitfield_extract(val, SARADC_DIV_CON_SHIFT,
  338. SARADC_DIV_CON_WIDTH);
  339. return DIV_TO_RATE(OSC_HZ, div);
  340. }
  341. static ulong rk3128_saradc_set_clk(struct rk3128_cru *cru, uint hz)
  342. {
  343. int src_clk_div;
  344. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  345. assert(src_clk_div < 128);
  346. rk_clrsetreg(&cru->cru_clksel_con[24],
  347. SARADC_DIV_CON_MASK,
  348. src_clk_div << SARADC_DIV_CON_SHIFT);
  349. return rk3128_saradc_get_clk(cru);
  350. }
  351. static ulong rk3128_vop_set_clk(struct rk3128_cru *cru, ulong clk_id, uint hz)
  352. {
  353. int src_clk_div;
  354. struct pll_div cpll_config = {0};
  355. src_clk_div = GPLL_HZ / hz;
  356. assert(src_clk_div - 1 < 31);
  357. switch (clk_id) {
  358. case ACLK_VIO0:
  359. rk_clrsetreg(&cru->cru_clksel_con[31],
  360. VIO0_PLL_MASK | VIO0_DIV_MASK,
  361. VIO0_SEL_GPLL << VIO0_PLL_SHIFT |
  362. (src_clk_div - 1) << VIO0_DIV_SHIFT);
  363. break;
  364. case ACLK_VIO1:
  365. rk_clrsetreg(&cru->cru_clksel_con[31],
  366. VIO1_PLL_MASK | VIO1_DIV_MASK,
  367. VIO1_SEL_GPLL << VIO1_PLL_SHIFT |
  368. (src_clk_div - 1) << VIO1_DIV_SHIFT);
  369. break;
  370. case DCLK_LCDC:
  371. if (pll_para_config(hz, &cpll_config))
  372. return -1;
  373. rkclk_set_pll(cru, CLK_CODEC, &cpll_config);
  374. rk_clrsetreg(&cru->cru_clksel_con[27],
  375. DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_CON_MASK,
  376. DCLK_VOP_PLL_SEL_CPLL << DCLK_VOP_SEL_SHIFT |
  377. (1 - 1) << DCLK_VOP_DIV_CON_SHIFT);
  378. break;
  379. default:
  380. printf("do not support this vop freq\n");
  381. return -EINVAL;
  382. }
  383. return hz;
  384. }
  385. static ulong rk3128_vop_get_rate(struct rk3128_cru *cru, ulong clk_id)
  386. {
  387. u32 div, con, parent;
  388. switch (clk_id) {
  389. case ACLK_VIO0:
  390. con = readl(&cru->cru_clksel_con[31]);
  391. div = con & 0x1f;
  392. parent = GPLL_HZ;
  393. break;
  394. case ACLK_VIO1:
  395. con = readl(&cru->cru_clksel_con[31]);
  396. div = (con >> 8) & 0x1f;
  397. parent = GPLL_HZ;
  398. break;
  399. case DCLK_LCDC:
  400. con = readl(&cru->cru_clksel_con[27]);
  401. div = (con >> 8) & 0xfff;
  402. parent = rkclk_pll_get_rate(cru, CLK_CODEC);
  403. break;
  404. default:
  405. return -ENOENT;
  406. }
  407. return DIV_TO_RATE(parent, div);
  408. }
  409. static ulong rk3128_clk_get_rate(struct clk *clk)
  410. {
  411. struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
  412. switch (clk->id) {
  413. case 0 ... 63:
  414. return rkclk_pll_get_rate(priv->cru, clk->id);
  415. case PCLK_I2C0:
  416. case PCLK_I2C1:
  417. case PCLK_I2C2:
  418. case PCLK_I2C3:
  419. case PCLK_PWM:
  420. return rk3128_peri_get_pclk(priv->cru, clk->id);
  421. case SCLK_SARADC:
  422. return rk3128_saradc_get_clk(priv->cru);
  423. case DCLK_LCDC:
  424. case ACLK_VIO0:
  425. case ACLK_VIO1:
  426. return rk3128_vop_get_rate(priv->cru, clk->id);
  427. default:
  428. return -ENOENT;
  429. }
  430. }
  431. static ulong rk3128_clk_set_rate(struct clk *clk, ulong rate)
  432. {
  433. struct rk3128_clk_priv *priv = dev_get_priv(clk->dev);
  434. ulong new_rate, gclk_rate;
  435. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  436. switch (clk->id) {
  437. case 0 ... 63:
  438. return 0;
  439. case DCLK_LCDC:
  440. case ACLK_VIO0:
  441. case ACLK_VIO1:
  442. new_rate = rk3128_vop_set_clk(priv->cru,
  443. clk->id, rate);
  444. break;
  445. case HCLK_EMMC:
  446. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  447. clk->id, rate);
  448. break;
  449. case PCLK_I2C0:
  450. case PCLK_I2C1:
  451. case PCLK_I2C2:
  452. case PCLK_I2C3:
  453. case PCLK_PWM:
  454. new_rate = rk3128_peri_set_pclk(priv->cru, clk->id, rate);
  455. break;
  456. case SCLK_SARADC:
  457. new_rate = rk3128_saradc_set_clk(priv->cru, rate);
  458. break;
  459. default:
  460. return -ENOENT;
  461. }
  462. return new_rate;
  463. }
  464. static struct clk_ops rk3128_clk_ops = {
  465. .get_rate = rk3128_clk_get_rate,
  466. .set_rate = rk3128_clk_set_rate,
  467. };
  468. static int rk3128_clk_of_to_plat(struct udevice *dev)
  469. {
  470. struct rk3128_clk_priv *priv = dev_get_priv(dev);
  471. priv->cru = dev_read_addr_ptr(dev);
  472. return 0;
  473. }
  474. static int rk3128_clk_probe(struct udevice *dev)
  475. {
  476. struct rk3128_clk_priv *priv = dev_get_priv(dev);
  477. rkclk_init(priv->cru);
  478. return 0;
  479. }
  480. static int rk3128_clk_bind(struct udevice *dev)
  481. {
  482. int ret;
  483. struct udevice *sys_child;
  484. struct sysreset_reg *priv;
  485. /* The reset driver does not have a device node, so bind it here */
  486. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  487. &sys_child);
  488. if (ret) {
  489. debug("Warning: No sysreset driver: ret=%d\n", ret);
  490. } else {
  491. priv = malloc(sizeof(struct sysreset_reg));
  492. priv->glb_srst_fst_value = offsetof(struct rk3128_cru,
  493. cru_glb_srst_fst_value);
  494. priv->glb_srst_snd_value = offsetof(struct rk3128_cru,
  495. cru_glb_srst_snd_value);
  496. dev_set_priv(sys_child, priv);
  497. }
  498. return 0;
  499. }
  500. static const struct udevice_id rk3128_clk_ids[] = {
  501. { .compatible = "rockchip,rk3128-cru" },
  502. { .compatible = "rockchip,rk3126-cru" },
  503. { }
  504. };
  505. U_BOOT_DRIVER(rockchip_rk3128_cru) = {
  506. .name = "clk_rk3128",
  507. .id = UCLASS_CLK,
  508. .of_match = rk3128_clk_ids,
  509. .priv_auto = sizeof(struct rk3128_clk_priv),
  510. .of_to_plat = rk3128_clk_of_to_plat,
  511. .ops = &rk3128_clk_ops,
  512. .bind = rk3128_clk_bind,
  513. .probe = rk3128_clk_probe,
  514. };