clk_rk3036.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <syscon.h>
  12. #include <asm/io.h>
  13. #include <asm/arch-rockchip/clock.h>
  14. #include <asm/arch-rockchip/cru_rk3036.h>
  15. #include <asm/arch-rockchip/hardware.h>
  16. #include <dm/device-internal.h>
  17. #include <dm/lists.h>
  18. #include <dt-bindings/clock/rk3036-cru.h>
  19. #include <linux/delay.h>
  20. #include <linux/log2.h>
  21. #include <linux/stringify.h>
  22. enum {
  23. VCO_MAX_HZ = 2400U * 1000000,
  24. VCO_MIN_HZ = 600 * 1000000,
  25. OUTPUT_MAX_HZ = 2400U * 1000000,
  26. OUTPUT_MIN_HZ = 24 * 1000000,
  27. };
  28. #define RATE_TO_DIV(input_rate, output_rate) \
  29. ((input_rate) / (output_rate) - 1);
  30. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  31. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  32. .refdiv = _refdiv,\
  33. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  34. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  35. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  36. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  37. #hz "Hz cannot be hit with PLL "\
  38. "divisors on line " __stringify(__LINE__));
  39. /* use integer mode*/
  40. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  41. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  42. static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id,
  43. const struct pll_div *div)
  44. {
  45. int pll_id = rk_pll_id(clk_id);
  46. struct rk3036_pll *pll = &cru->pll[pll_id];
  47. /* All PLLs have same VCO and output frequency range restrictions. */
  48. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  49. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  50. debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, postdiv2=%d,\
  51. vco=%u Hz, output=%u Hz\n",
  52. pll, div->fbdiv, div->refdiv, div->postdiv1,
  53. div->postdiv2, vco_hz, output_hz);
  54. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  55. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  56. /* use integer mode */
  57. rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
  58. rk_clrsetreg(&pll->con0,
  59. PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
  60. (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
  61. rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
  62. (div->postdiv2 << PLL_POSTDIV2_SHIFT |
  63. div->refdiv << PLL_REFDIV_SHIFT));
  64. /* waiting for pll lock */
  65. while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
  66. udelay(1);
  67. return 0;
  68. }
  69. static void rkclk_init(struct rk3036_cru *cru)
  70. {
  71. u32 aclk_div;
  72. u32 hclk_div;
  73. u32 pclk_div;
  74. /* pll enter slow-mode */
  75. rk_clrsetreg(&cru->cru_mode_con,
  76. GPLL_MODE_MASK | APLL_MODE_MASK,
  77. GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
  78. APLL_MODE_SLOW << APLL_MODE_SHIFT);
  79. /* init pll */
  80. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  81. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  82. /*
  83. * select apll as cpu/core clock pll source and
  84. * set up dependent divisors for PERI and ACLK clocks.
  85. * core hz : apll = 1:1
  86. */
  87. aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
  88. assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
  89. pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
  90. assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
  91. rk_clrsetreg(&cru->cru_clksel_con[0],
  92. CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
  93. CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
  94. 0 << CORE_DIV_CON_SHIFT);
  95. rk_clrsetreg(&cru->cru_clksel_con[1],
  96. CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
  97. aclk_div << CORE_ACLK_DIV_SHIFT |
  98. pclk_div << CORE_PERI_DIV_SHIFT);
  99. /*
  100. * select apll as pd_bus bus clock source and
  101. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  102. */
  103. aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
  104. assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
  105. pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
  106. assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
  107. hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
  108. assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
  109. rk_clrsetreg(&cru->cru_clksel_con[0],
  110. BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
  111. BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
  112. aclk_div << BUS_ACLK_DIV_SHIFT);
  113. rk_clrsetreg(&cru->cru_clksel_con[1],
  114. BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
  115. pclk_div << BUS_PCLK_DIV_SHIFT |
  116. hclk_div << BUS_HCLK_DIV_SHIFT);
  117. /*
  118. * select gpll as pd_peri bus clock source and
  119. * set up dependent divisors for PCLK/HCLK and ACLK clocks.
  120. */
  121. aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
  122. assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
  123. hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
  124. assert((1 << hclk_div) * PERI_HCLK_HZ ==
  125. PERI_ACLK_HZ && (hclk_div < 0x4));
  126. pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
  127. assert((1 << pclk_div) * PERI_PCLK_HZ ==
  128. PERI_ACLK_HZ && pclk_div < 0x8);
  129. rk_clrsetreg(&cru->cru_clksel_con[10],
  130. PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
  131. PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
  132. PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
  133. pclk_div << PERI_PCLK_DIV_SHIFT |
  134. hclk_div << PERI_HCLK_DIV_SHIFT |
  135. aclk_div << PERI_ACLK_DIV_SHIFT);
  136. /* PLL enter normal-mode */
  137. rk_clrsetreg(&cru->cru_mode_con,
  138. GPLL_MODE_MASK | APLL_MODE_MASK,
  139. GPLL_MODE_NORM << GPLL_MODE_SHIFT |
  140. APLL_MODE_NORM << APLL_MODE_SHIFT);
  141. }
  142. /* Get pll rate by id */
  143. static uint32_t rkclk_pll_get_rate(struct rk3036_cru *cru,
  144. enum rk_clk_id clk_id)
  145. {
  146. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  147. uint32_t con;
  148. int pll_id = rk_pll_id(clk_id);
  149. struct rk3036_pll *pll = &cru->pll[pll_id];
  150. static u8 clk_shift[CLK_COUNT] = {
  151. 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
  152. GPLL_MODE_SHIFT, 0xff
  153. };
  154. static u32 clk_mask[CLK_COUNT] = {
  155. 0xffffffff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xffffffff,
  156. GPLL_MODE_MASK, 0xffffffff
  157. };
  158. uint shift;
  159. uint mask;
  160. con = readl(&cru->cru_mode_con);
  161. shift = clk_shift[clk_id];
  162. mask = clk_mask[clk_id];
  163. switch ((con & mask) >> shift) {
  164. case GPLL_MODE_SLOW:
  165. return OSC_HZ;
  166. case GPLL_MODE_NORM:
  167. /* normal mode */
  168. con = readl(&pll->con0);
  169. postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
  170. fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
  171. con = readl(&pll->con1);
  172. postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
  173. refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
  174. return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  175. case GPLL_MODE_DEEP:
  176. default:
  177. return 32768;
  178. }
  179. }
  180. static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
  181. int periph)
  182. {
  183. uint src_rate;
  184. uint div, mux;
  185. u32 con;
  186. switch (periph) {
  187. case HCLK_EMMC:
  188. case SCLK_EMMC:
  189. con = readl(&cru->cru_clksel_con[12]);
  190. mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
  191. div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
  192. break;
  193. case HCLK_SDIO:
  194. case SCLK_SDIO:
  195. con = readl(&cru->cru_clksel_con[12]);
  196. mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
  197. div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
  198. break;
  199. default:
  200. return -EINVAL;
  201. }
  202. src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
  203. return DIV_TO_RATE(src_rate, div) / 2;
  204. }
  205. static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
  206. int periph, uint freq)
  207. {
  208. int src_clk_div;
  209. int mux;
  210. debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
  211. /* mmc clock auto divide 2 in internal */
  212. src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
  213. if (src_clk_div > 128) {
  214. src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
  215. assert(src_clk_div - 1 < 128);
  216. mux = EMMC_SEL_24M;
  217. } else {
  218. mux = EMMC_SEL_GPLL;
  219. }
  220. switch (periph) {
  221. case HCLK_EMMC:
  222. case SCLK_EMMC:
  223. rk_clrsetreg(&cru->cru_clksel_con[12],
  224. EMMC_PLL_MASK | EMMC_DIV_MASK,
  225. mux << EMMC_PLL_SHIFT |
  226. (src_clk_div - 1) << EMMC_DIV_SHIFT);
  227. break;
  228. case HCLK_SDIO:
  229. case SCLK_SDIO:
  230. rk_clrsetreg(&cru->cru_clksel_con[11],
  231. MMC0_PLL_MASK | MMC0_DIV_MASK,
  232. mux << MMC0_PLL_SHIFT |
  233. (src_clk_div - 1) << MMC0_DIV_SHIFT);
  234. break;
  235. default:
  236. return -EINVAL;
  237. }
  238. return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
  239. }
  240. static ulong rk3036_clk_get_rate(struct clk *clk)
  241. {
  242. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  243. switch (clk->id) {
  244. case 0 ... 63:
  245. return rkclk_pll_get_rate(priv->cru, clk->id);
  246. default:
  247. return -ENOENT;
  248. }
  249. }
  250. static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
  251. {
  252. struct rk3036_clk_priv *priv = dev_get_priv(clk->dev);
  253. ulong new_rate, gclk_rate;
  254. gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
  255. switch (clk->id) {
  256. case 0 ... 63:
  257. return 0;
  258. case HCLK_EMMC:
  259. case SCLK_EMMC:
  260. new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
  261. clk->id, rate);
  262. break;
  263. default:
  264. return -ENOENT;
  265. }
  266. return new_rate;
  267. }
  268. static struct clk_ops rk3036_clk_ops = {
  269. .get_rate = rk3036_clk_get_rate,
  270. .set_rate = rk3036_clk_set_rate,
  271. };
  272. static int rk3036_clk_of_to_plat(struct udevice *dev)
  273. {
  274. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  275. priv->cru = dev_read_addr_ptr(dev);
  276. return 0;
  277. }
  278. static int rk3036_clk_probe(struct udevice *dev)
  279. {
  280. struct rk3036_clk_priv *priv = dev_get_priv(dev);
  281. rkclk_init(priv->cru);
  282. return 0;
  283. }
  284. static int rk3036_clk_bind(struct udevice *dev)
  285. {
  286. int ret;
  287. struct udevice *sys_child;
  288. struct sysreset_reg *priv;
  289. /* The reset driver does not have a device node, so bind it here */
  290. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  291. &sys_child);
  292. if (ret) {
  293. debug("Warning: No sysreset driver: ret=%d\n", ret);
  294. } else {
  295. priv = malloc(sizeof(struct sysreset_reg));
  296. priv->glb_srst_fst_value = offsetof(struct rk3036_cru,
  297. cru_glb_srst_fst_value);
  298. priv->glb_srst_snd_value = offsetof(struct rk3036_cru,
  299. cru_glb_srst_snd_value);
  300. dev_set_priv(sys_child, priv);
  301. }
  302. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  303. ret = offsetof(struct rk3036_cru, cru_softrst_con[0]);
  304. ret = rockchip_reset_bind(dev, ret, 9);
  305. if (ret)
  306. debug("Warning: software reset driver bind faile\n");
  307. #endif
  308. return 0;
  309. }
  310. static const struct udevice_id rk3036_clk_ids[] = {
  311. { .compatible = "rockchip,rk3036-cru" },
  312. { }
  313. };
  314. U_BOOT_DRIVER(rockchip_rk3036_cru) = {
  315. .name = "clk_rk3036",
  316. .id = UCLASS_CLK,
  317. .of_match = rk3036_clk_ids,
  318. .priv_auto = sizeof(struct rk3036_clk_priv),
  319. .of_to_plat = rk3036_clk_of_to_plat,
  320. .ops = &rk3036_clk_ops,
  321. .bind = rk3036_clk_bind,
  322. .probe = rk3036_clk_probe,
  323. };