clk-mt7620.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
  4. *
  5. * Author: Weijie Gao <weijie.gao@mediatek.com>
  6. */
  7. #include <clk-uclass.h>
  8. #include <dm.h>
  9. #include <dm/device_compat.h>
  10. #include <dt-bindings/clock/mt7620-clk.h>
  11. #include <misc.h>
  12. #include <mach/mt7620-sysc.h>
  13. /* CLKCFG1 */
  14. #define CLKCFG1_REG 0x30
  15. #define CLK_SRC_CPU -1
  16. #define CLK_SRC_CPU_D2 -2
  17. #define CLK_SRC_SYS -3
  18. #define CLK_SRC_XTAL -4
  19. #define CLK_SRC_PERI -5
  20. struct mt7620_clk_priv {
  21. struct udevice *dev;
  22. struct udevice *sysc;
  23. struct mt7620_sysc_clks clks;
  24. };
  25. static const int mt7620_clks[] = {
  26. [CLK_SYS] = CLK_SRC_SYS,
  27. [CLK_CPU] = CLK_SRC_CPU,
  28. [CLK_XTAL] = CLK_SRC_XTAL,
  29. [CLK_MIPS_CNT] = CLK_SRC_CPU_D2,
  30. [CLK_UARTF] = CLK_SRC_PERI,
  31. [CLK_UARTL] = CLK_SRC_PERI,
  32. [CLK_SPI] = CLK_SRC_SYS,
  33. [CLK_I2C] = CLK_SRC_PERI,
  34. [CLK_I2S] = CLK_SRC_PERI,
  35. };
  36. static ulong mt7620_clk_get_rate(struct clk *clk)
  37. {
  38. struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
  39. if (clk->id >= ARRAY_SIZE(mt7620_clks))
  40. return 0;
  41. switch (mt7620_clks[clk->id]) {
  42. case CLK_SRC_CPU:
  43. return priv->clks.cpu_clk;
  44. case CLK_SRC_CPU_D2:
  45. return priv->clks.cpu_clk / 2;
  46. case CLK_SRC_SYS:
  47. return priv->clks.sys_clk;
  48. case CLK_SRC_XTAL:
  49. return priv->clks.xtal_clk;
  50. case CLK_SRC_PERI:
  51. return priv->clks.peri_clk;
  52. default:
  53. return mt7620_clks[clk->id];
  54. }
  55. }
  56. static int mt7620_clkcfg1_rmw(struct mt7620_clk_priv *priv, u32 clr, u32 set)
  57. {
  58. u32 val;
  59. int ret;
  60. ret = misc_read(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
  61. if (ret) {
  62. dev_err(priv->dev, "mt7620_clk: failed to read CLKCFG1\n");
  63. return ret;
  64. }
  65. val &= ~clr;
  66. val |= set;
  67. ret = misc_write(priv->sysc, CLKCFG1_REG, &val, sizeof(val));
  68. if (ret) {
  69. dev_err(priv->dev, "mt7620_clk: failed to write CLKCFG1\n");
  70. return ret;
  71. }
  72. return 0;
  73. }
  74. static int mt7620_clk_enable(struct clk *clk)
  75. {
  76. struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
  77. if (clk->id > 30)
  78. return -1;
  79. return mt7620_clkcfg1_rmw(priv, 0, BIT(clk->id));
  80. }
  81. static int mt7620_clk_disable(struct clk *clk)
  82. {
  83. struct mt7620_clk_priv *priv = dev_get_priv(clk->dev);
  84. if (clk->id > 30)
  85. return -1;
  86. return mt7620_clkcfg1_rmw(priv, BIT(clk->id), 0);
  87. }
  88. const struct clk_ops mt7620_clk_ops = {
  89. .enable = mt7620_clk_enable,
  90. .disable = mt7620_clk_disable,
  91. .get_rate = mt7620_clk_get_rate,
  92. };
  93. static int mt7620_clk_probe(struct udevice *dev)
  94. {
  95. struct mt7620_clk_priv *priv = dev_get_priv(dev);
  96. struct ofnode_phandle_args sysc_args;
  97. int ret;
  98. ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "mediatek,sysc", NULL,
  99. 0, 0, &sysc_args);
  100. if (ret) {
  101. dev_err(dev, "mt7620_clk: sysc property not found\n");
  102. return ret;
  103. }
  104. ret = uclass_get_device_by_ofnode(UCLASS_MISC, sysc_args.node,
  105. &priv->sysc);
  106. if (ret) {
  107. dev_err(dev, "mt7620_clk: failed to sysc device\n");
  108. return ret;
  109. }
  110. ret = misc_ioctl(priv->sysc, MT7620_SYSC_IOCTL_GET_CLK,
  111. &priv->clks);
  112. if (ret) {
  113. dev_err(dev, "mt7620_clk: failed to get base clocks\n");
  114. return ret;
  115. }
  116. priv->dev = dev;
  117. return 0;
  118. }
  119. static const struct udevice_id mt7620_clk_ids[] = {
  120. { .compatible = "mediatek,mt7620-clk" },
  121. { }
  122. };
  123. U_BOOT_DRIVER(mt7620_clk) = {
  124. .name = "mt7620-clk",
  125. .id = UCLASS_CLK,
  126. .of_match = mt7620_clk_ids,
  127. .probe = mt7620_clk_probe,
  128. .priv_auto = sizeof(struct mt7620_clk_priv),
  129. .ops = &mt7620_clk_ops,
  130. .flags = DM_FLAG_PRE_RELOC,
  131. };