mpc83xx_clk.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. /**
  7. * enum ratio - Description of a core clock ratio
  8. * @RAT_UNK: Unknown ratio
  9. * @RAT_BYP: Bypass
  10. * @RAT_1_TO_8: Ratio 1:8
  11. * @RAT_1_TO_4: Ratio 1:4
  12. * @RAT_1_TO_2: Ratio 1:2
  13. * @RAT_1_TO_1: Ratio 1:1
  14. * @RAT_1_5_TO_1: Ratio 1.5:1
  15. * @RAT_2_TO_1: Ratio 2:1
  16. * @RAT_2_5_TO_1: Ratio 2.5:1
  17. * @RAT_3_TO_1: Ratio 3:1
  18. */
  19. #include <linux/bitops.h>
  20. enum ratio {
  21. RAT_UNK,
  22. RAT_BYP,
  23. RAT_1_TO_8,
  24. RAT_1_TO_4,
  25. RAT_1_TO_2,
  26. RAT_1_TO_1,
  27. RAT_1_5_TO_1,
  28. RAT_2_TO_1,
  29. RAT_2_5_TO_1,
  30. RAT_3_TO_1
  31. };
  32. /**
  33. * struct corecnf - Description for a core clock configuration
  34. * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
  35. * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
  36. */
  37. struct corecnf {
  38. int core_csb_ratio;
  39. int vco_divider;
  40. };
  41. /*
  42. * Table with all valid Core CSB frequency ratio / VCO divider combinations as
  43. * indexed by the COREPLL field of the SPMR
  44. */
  45. static const struct corecnf corecnf_tab[] = {
  46. {RAT_BYP, RAT_BYP}, /* 0x00 */
  47. {RAT_BYP, RAT_BYP}, /* 0x01 */
  48. {RAT_BYP, RAT_BYP}, /* 0x02 */
  49. {RAT_BYP, RAT_BYP}, /* 0x03 */
  50. {RAT_BYP, RAT_BYP}, /* 0x04 */
  51. {RAT_BYP, RAT_BYP}, /* 0x05 */
  52. {RAT_BYP, RAT_BYP}, /* 0x06 */
  53. {RAT_BYP, RAT_BYP}, /* 0x07 */
  54. {RAT_1_TO_1, RAT_1_TO_2}, /* 0x08 */
  55. {RAT_1_TO_1, RAT_1_TO_4}, /* 0x09 */
  56. {RAT_1_TO_1, RAT_1_TO_8}, /* 0x0A */
  57. {RAT_1_TO_1, RAT_1_TO_8}, /* 0x0B */
  58. {RAT_1_5_TO_1, RAT_1_TO_2}, /* 0x0C */
  59. {RAT_1_5_TO_1, RAT_1_TO_4}, /* 0x0D */
  60. {RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0E */
  61. {RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0F */
  62. {RAT_2_TO_1, RAT_1_TO_2}, /* 0x10 */
  63. {RAT_2_TO_1, RAT_1_TO_4}, /* 0x11 */
  64. {RAT_2_TO_1, RAT_1_TO_8}, /* 0x12 */
  65. {RAT_2_TO_1, RAT_1_TO_8}, /* 0x13 */
  66. {RAT_2_5_TO_1, RAT_1_TO_2}, /* 0x14 */
  67. {RAT_2_5_TO_1, RAT_1_TO_4}, /* 0x15 */
  68. {RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x16 */
  69. {RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x17 */
  70. {RAT_3_TO_1, RAT_1_TO_2}, /* 0x18 */
  71. {RAT_3_TO_1, RAT_1_TO_4}, /* 0x19 */
  72. {RAT_3_TO_1, RAT_1_TO_8}, /* 0x1A */
  73. {RAT_3_TO_1, RAT_1_TO_8}, /* 0x1B */
  74. };
  75. /**
  76. * enum reg_type - Register to read a field from
  77. * @REG_SCCR: Use the SCCR register
  78. * @REG_SPMR: Use the SPMR register
  79. */
  80. enum reg_type {
  81. REG_SCCR,
  82. REG_SPMR,
  83. };
  84. /**
  85. * enum mode_type - Description of how to read a specific frequency value
  86. * @TYPE_INVALID: Unknown type, will provoke error
  87. * @TYPE_SCCR_STANDARD: Read a field from the SCCR register, and use it
  88. * as a divider for the CSB clock to compute the
  89. * frequency
  90. * @TYPE_SCCR_ONOFF: The field describes a bit flag that can turn the
  91. * clock on or off
  92. * @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it
  93. * as a multiplier for the CSB clock to compute the
  94. * frequency
  95. * @TYPE_SPECIAL: The frequency is calculated in a non-standard way
  96. */
  97. enum mode_type {
  98. TYPE_INVALID = 0,
  99. TYPE_SCCR_STANDARD,
  100. TYPE_SCCR_ONOFF,
  101. TYPE_SPMR_DIRECT_MULTIPLY,
  102. TYPE_SPECIAL,
  103. };
  104. /* Map of each clock index to its human-readable name */
  105. static const char * const names[] = {
  106. [MPC83XX_CLK_CORE] = "Core",
  107. [MPC83XX_CLK_CSB] = "Coherent System Bus",
  108. [MPC83XX_CLK_QE] = "QE",
  109. [MPC83XX_CLK_BRG] = "BRG",
  110. [MPC83XX_CLK_LBIU] = "Local Bus Controller",
  111. [MPC83XX_CLK_LCLK] = "Local Bus",
  112. [MPC83XX_CLK_MEM] = "DDR",
  113. [MPC83XX_CLK_MEM_SEC] = "DDR Secondary",
  114. [MPC83XX_CLK_ENC] = "SEC",
  115. [MPC83XX_CLK_I2C1] = "I2C1",
  116. [MPC83XX_CLK_I2C2] = "I2C2",
  117. [MPC83XX_CLK_TDM] = "TDM",
  118. [MPC83XX_CLK_SDHC] = "SDHC",
  119. [MPC83XX_CLK_TSEC1] = "TSEC1",
  120. [MPC83XX_CLK_TSEC2] = "TSEC2",
  121. [MPC83XX_CLK_USBDR] = "USB DR",
  122. [MPC83XX_CLK_USBMPH] = "USB MPH",
  123. [MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
  124. [MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
  125. [MPC83XX_CLK_SATA] = "SATA",
  126. [MPC83XX_CLK_DMAC] = "DMAC",
  127. [MPC83XX_CLK_PCI] = "PCI",
  128. };
  129. /**
  130. * struct clk_mode - Structure for clock mode descriiptions
  131. * @low: The low bit of the data field to read for this mode (may not apply to
  132. * some modes)
  133. * @high: The high bit of the data field to read for this mode (may not apply to
  134. * some modes)
  135. * @type: The type of the mode description (one of enum mode_type)
  136. */
  137. struct clk_mode {
  138. u8 low;
  139. u8 high;
  140. int type;
  141. };
  142. /**
  143. * set_mode() - Build a clock mode description from data
  144. * @mode: The clock mode description to be filled out
  145. * @low: The low bit of the data field to read for this mode (may not apply to
  146. * some modes)
  147. * @high: The high bit of the data field to read for this mode (may not apply to
  148. * some modes)
  149. * @type: The type of the mode description (one of enum mode_type)
  150. *
  151. * Clock mode descriptions are a succinct description of how to read a specific
  152. * clock's rate from the hardware; usually by reading a specific field of a
  153. * register, such a s the SCCR register, but some types use different methods
  154. * for obtaining the clock rate.
  155. */
  156. static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
  157. {
  158. mode->low = low;
  159. mode->high = high;
  160. mode->type = type;
  161. }
  162. /**
  163. * retrieve_mode() - Get the clock mode description for a specific clock
  164. * @clk: The identifier of the clock for which the clock description should
  165. * be retrieved
  166. * @soc_type: The type of MPC83xx SoC for which the clock description should be
  167. * retrieved
  168. * @mode: Pointer to a clk_mode structure to be filled with data for the
  169. * clock
  170. *
  171. * Since some clock rate are stored in different places on different MPC83xx
  172. * SoCs, the SoC type has to be supplied along with the clock's identifier.
  173. *
  174. * Return: 0 if OK, -ve on error
  175. */
  176. static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
  177. {
  178. switch (clk) {
  179. case MPC83XX_CLK_CORE:
  180. case MPC83XX_CLK_CSB:
  181. case MPC83XX_CLK_QE:
  182. case MPC83XX_CLK_BRG:
  183. case MPC83XX_CLK_LCLK:
  184. case MPC83XX_CLK_I2C2:
  185. set_mode(mode, 0, 0, TYPE_SPECIAL);
  186. break;
  187. case MPC83XX_CLK_MEM:
  188. set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY);
  189. break;
  190. case MPC83XX_CLK_LBIU:
  191. case MPC83XX_CLK_MEM_SEC:
  192. set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY);
  193. break;
  194. case MPC83XX_CLK_TSEC1:
  195. set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
  196. break;
  197. case MPC83XX_CLK_TSEC2:
  198. if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
  199. set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
  200. else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
  201. set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
  202. break;
  203. case MPC83XX_CLK_SDHC:
  204. set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
  205. break;
  206. case MPC83XX_CLK_ENC:
  207. set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
  208. break;
  209. case MPC83XX_CLK_I2C1:
  210. if (soc_type == SOC_MPC8349)
  211. set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
  212. else /* I2C and ENC are the same register */
  213. set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
  214. break;
  215. case MPC83XX_CLK_PCIEXP1:
  216. set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
  217. break;
  218. case MPC83XX_CLK_PCIEXP2:
  219. set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
  220. break;
  221. case MPC83XX_CLK_USBDR:
  222. if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
  223. set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
  224. else
  225. set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
  226. break;
  227. case MPC83XX_CLK_USBMPH:
  228. set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
  229. break;
  230. case MPC83XX_CLK_PCI:
  231. set_mode(mode, 15, 15, TYPE_SCCR_ONOFF);
  232. break;
  233. case MPC83XX_CLK_DMAC:
  234. set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
  235. break;
  236. case MPC83XX_CLK_SATA:
  237. /* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
  238. if (soc_type == SOC_MPC8379) {
  239. set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
  240. set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
  241. set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
  242. set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
  243. } else {
  244. set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
  245. set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
  246. }
  247. break;
  248. case MPC83XX_CLK_TDM:
  249. set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
  250. break;
  251. default:
  252. debug("%s: Unknown clock type %d on soc type %d\n",
  253. __func__, clk, soc_type);
  254. set_mode(mode, 0, 0, TYPE_INVALID);
  255. return -EINVAL;
  256. }
  257. return 0;
  258. }
  259. /**
  260. * get_spmr() - Read the SPMR (System PLL Mode Register)
  261. * @im: Pointer to the MPC83xx main register map in question
  262. *
  263. * Return: The SPMR value as a 32-bit number.
  264. */
  265. static inline u32 get_spmr(immap_t *im)
  266. {
  267. u32 res = in_be32(&im->clk.spmr);
  268. return res;
  269. }
  270. /**
  271. * get_sccr() - Read the SCCR (System Clock Control Register)
  272. * @im: Pointer to the MPC83xx main register map in question
  273. *
  274. * Return: The SCCR value as a 32-bit number.
  275. */
  276. static inline u32 get_sccr(immap_t *im)
  277. {
  278. u32 res = in_be32(&im->clk.sccr);
  279. return res;
  280. }
  281. /**
  282. * get_lcrr() - Read the LCRR (Clock Ratio Register)
  283. * @im: Pointer to the MPC83xx main register map in question
  284. *
  285. * Return: The LCRR value as a 32-bit number.
  286. */
  287. static inline u32 get_lcrr(immap_t *im)
  288. {
  289. u32 res = in_be32(&im->im_lbc.lcrr);
  290. return res;
  291. }
  292. /**
  293. * get_pci_sync_in() - Read the PCI synchronization clock speed
  294. * @im: Pointer to the MPC83xx main register map in question
  295. *
  296. * Return: The PCI synchronization clock speed value as a 32-bit number.
  297. */
  298. static inline u32 get_pci_sync_in(immap_t *im)
  299. {
  300. u8 clkin_div;
  301. clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
  302. return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
  303. }
  304. /**
  305. * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
  306. * @im: Pointer to the MPC83xx main register map in question
  307. *
  308. * Return: The CSB clock speed value as a 32-bit number.
  309. */
  310. static inline u32 get_csb_clk(immap_t *im)
  311. {
  312. u8 spmf;
  313. spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  314. return CONFIG_SYS_CLK_FREQ * spmf;
  315. }
  316. /**
  317. * spmr_field() - Read a specific SPMR field
  318. * @im: Pointer to the MPC83xx main register map in question
  319. * @mask: A bitmask that describes the bitfield to be read
  320. *
  321. * Return: The value of the bit field as a 32-bit number.
  322. */
  323. static inline uint spmr_field(immap_t *im, u32 mask)
  324. {
  325. /* Extract shift from bitmask */
  326. uint shift = mask ? ffs(mask) - 1 : 0;
  327. return (get_spmr(im) & mask) >> shift;
  328. }
  329. /**
  330. * sccr_field() - Read a specific SCCR field
  331. * @im: Pointer to the MPC83xx main register map in question
  332. * @mask: A bitmask that describes the bitfield to be read
  333. *
  334. * Return: The value of the bit field as a 32-bit number.
  335. */
  336. static inline uint sccr_field(immap_t *im, u32 mask)
  337. {
  338. /* Extract shift from bitmask */
  339. uint shift = mask ? ffs(mask) - 1 : 0;
  340. return (get_sccr(im) & mask) >> shift;
  341. }
  342. /**
  343. * lcrr_field() - Read a specific LCRR field
  344. * @im: Pointer to the MPC83xx main register map in question
  345. * @mask: A bitmask that describes the bitfield to be read
  346. *
  347. * Return: The value of the bit field as a 32-bit number.
  348. */
  349. static inline uint lcrr_field(immap_t *im, u32 mask)
  350. {
  351. /* Extract shift from bitmask */
  352. uint shift = mask ? ffs(mask) - 1 : 0;
  353. return (get_lcrr(im) & mask) >> shift;
  354. }