mpc83xx_clk.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2017
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <clock_legacy.h>
  9. #include <command.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <vsprintf.h>
  13. #include <asm/global_data.h>
  14. #include <dm/lists.h>
  15. #include <dt-bindings/clk/mpc83xx-clk.h>
  16. #include <asm/arch/soc.h>
  17. #include <linux/bitops.h>
  18. #include "mpc83xx_clk.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. /**
  21. * struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock
  22. * driver
  23. * @speed: Array containing the speed values of all system clocks (initialized
  24. * once, then only read back)
  25. */
  26. struct mpc83xx_clk_priv {
  27. u32 speed[MPC83XX_CLK_COUNT];
  28. };
  29. /**
  30. * is_clk_valid() - Check if clock ID is valid for given clock device
  31. * @clk: The clock device for which to check a clock ID
  32. * @id: The clock ID to check
  33. *
  34. * Return: true if clock ID is valid for clock device, false if not
  35. */
  36. static inline bool is_clk_valid(struct udevice *clk, int id)
  37. {
  38. ulong type = dev_get_driver_data(clk);
  39. switch (id) {
  40. case MPC83XX_CLK_MEM:
  41. return true;
  42. case MPC83XX_CLK_MEM_SEC:
  43. return type == SOC_MPC8360;
  44. case MPC83XX_CLK_ENC:
  45. return (type == SOC_MPC8308) || (type == SOC_MPC8309);
  46. case MPC83XX_CLK_I2C1:
  47. return true;
  48. case MPC83XX_CLK_TDM:
  49. return type == SOC_MPC8315;
  50. case MPC83XX_CLK_SDHC:
  51. return mpc83xx_has_sdhc(type);
  52. case MPC83XX_CLK_TSEC1:
  53. case MPC83XX_CLK_TSEC2:
  54. return mpc83xx_has_tsec(type);
  55. case MPC83XX_CLK_USBDR:
  56. return type == SOC_MPC8360;
  57. case MPC83XX_CLK_USBMPH:
  58. return type == SOC_MPC8349;
  59. case MPC83XX_CLK_PCIEXP1:
  60. return mpc83xx_has_pcie1(type);
  61. case MPC83XX_CLK_PCIEXP2:
  62. return mpc83xx_has_pcie2(type);
  63. case MPC83XX_CLK_SATA:
  64. return mpc83xx_has_sata(type);
  65. case MPC83XX_CLK_DMAC:
  66. return (type == SOC_MPC8308) || (type == SOC_MPC8309);
  67. case MPC83XX_CLK_PCI:
  68. /*
  69. * FIXME: implement proper support for this.
  70. */
  71. return 0 && mpc83xx_has_pci(type);
  72. case MPC83XX_CLK_CSB:
  73. return true;
  74. case MPC83XX_CLK_I2C2:
  75. return mpc83xx_has_second_i2c(type);
  76. case MPC83XX_CLK_QE:
  77. case MPC83XX_CLK_BRG:
  78. return mpc83xx_has_quicc_engine(type) && (type != SOC_MPC8309);
  79. case MPC83XX_CLK_LCLK:
  80. case MPC83XX_CLK_LBIU:
  81. case MPC83XX_CLK_CORE:
  82. return true;
  83. }
  84. return false;
  85. }
  86. /**
  87. * init_single_clk() - Initialize a clock with a given ID
  88. * @dev: The clock device for which to initialize the clock
  89. * @clk: The clock ID
  90. *
  91. * The clock speed is read from the hardware's registers, and stored in the
  92. * private data structure of the driver. From there it is only retrieved, and
  93. * not set.
  94. *
  95. * Return: 0 if OK, -ve on error
  96. */
  97. static int init_single_clk(struct udevice *dev, int clk)
  98. {
  99. struct mpc83xx_clk_priv *priv = dev_get_priv(dev);
  100. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  101. ulong type = dev_get_driver_data(dev);
  102. struct clk_mode mode;
  103. ulong mask;
  104. u32 csb_clk = get_csb_clk(im);
  105. int ret;
  106. ret = retrieve_mode(clk, type, &mode);
  107. if (ret) {
  108. debug("%s: Could not retrieve mode for clk %d (ret = %d)\n",
  109. dev->name, clk, ret);
  110. return ret;
  111. }
  112. if (mode.type == TYPE_INVALID) {
  113. debug("%s: clock %d invalid\n", dev->name, clk);
  114. return -EINVAL;
  115. }
  116. if (mode.type == TYPE_SCCR_STANDARD) {
  117. mask = GENMASK(31 - mode.low, 31 - mode.high);
  118. switch (sccr_field(im, mask)) {
  119. case 0:
  120. priv->speed[clk] = 0;
  121. break;
  122. case 1:
  123. priv->speed[clk] = csb_clk;
  124. break;
  125. case 2:
  126. priv->speed[clk] = csb_clk / 2;
  127. break;
  128. case 3:
  129. priv->speed[clk] = csb_clk / 3;
  130. break;
  131. default:
  132. priv->speed[clk] = 0;
  133. }
  134. return 0;
  135. }
  136. if (mode.type == TYPE_SPMR_DIRECT_MULTIPLY) {
  137. mask = GENMASK(31 - mode.low, 31 - mode.high);
  138. priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask));
  139. return 0;
  140. }
  141. if (clk == MPC83XX_CLK_CSB || clk == MPC83XX_CLK_I2C2) {
  142. priv->speed[clk] = csb_clk; /* i2c-2 clk is equal to csb clk */
  143. return 0;
  144. }
  145. if (clk == MPC83XX_CLK_QE || clk == MPC83XX_CLK_BRG) {
  146. u32 pci_sync_in = get_pci_sync_in(im);
  147. u32 qepmf = spmr_field(im, SPMR_CEPMF);
  148. u32 qepdf = spmr_field(im, SPMR_CEPDF);
  149. u32 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
  150. if (clk == MPC83XX_CLK_QE)
  151. priv->speed[clk] = qe_clk;
  152. else
  153. priv->speed[clk] = qe_clk / 2;
  154. return 0;
  155. }
  156. if (clk == MPC83XX_CLK_LCLK || clk == MPC83XX_CLK_LBIU) {
  157. u32 lbiu_clk = csb_clk *
  158. (1 + spmr_field(im, SPMR_LBIUCM));
  159. u32 clkdiv = lcrr_field(im, LCRR_CLKDIV);
  160. if (clk == MPC83XX_CLK_LBIU)
  161. priv->speed[clk] = lbiu_clk;
  162. switch (clkdiv) {
  163. case 2:
  164. case 4:
  165. case 8:
  166. priv->speed[clk] = lbiu_clk / clkdiv;
  167. break;
  168. default:
  169. /* unknown lcrr */
  170. priv->speed[clk] = 0;
  171. }
  172. return 0;
  173. }
  174. if (clk == MPC83XX_CLK_CORE) {
  175. u8 corepll = spmr_field(im, SPMR_COREPLL);
  176. u32 corecnf_tab_index = ((corepll & 0x1F) << 2) |
  177. ((corepll & 0x60) >> 5);
  178. if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
  179. debug("%s: Core configuration index %02x too high; possible wrong value",
  180. dev->name, corecnf_tab_index);
  181. return -EINVAL;
  182. }
  183. switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
  184. case RAT_BYP:
  185. case RAT_1_TO_1:
  186. priv->speed[clk] = csb_clk;
  187. break;
  188. case RAT_1_5_TO_1:
  189. priv->speed[clk] = (3 * csb_clk) / 2;
  190. break;
  191. case RAT_2_TO_1:
  192. priv->speed[clk] = 2 * csb_clk;
  193. break;
  194. case RAT_2_5_TO_1:
  195. priv->speed[clk] = (5 * csb_clk) / 2;
  196. break;
  197. case RAT_3_TO_1:
  198. priv->speed[clk] = 3 * csb_clk;
  199. break;
  200. default:
  201. /* unknown core to csb ratio */
  202. priv->speed[clk] = 0;
  203. }
  204. return 0;
  205. }
  206. /* Unknown clk value -> error */
  207. debug("%s: clock %d invalid\n", dev->name, clk);
  208. return -EINVAL;
  209. }
  210. /**
  211. * init_all_clks() - Initialize all clocks of a clock device
  212. * @dev: The clock device whose clocks should be initialized
  213. *
  214. * Return: 0 if OK, -ve on error
  215. */
  216. static inline int init_all_clks(struct udevice *dev)
  217. {
  218. int i;
  219. for (i = 0; i < MPC83XX_CLK_COUNT; i++) {
  220. int ret;
  221. if (!is_clk_valid(dev, i))
  222. continue;
  223. ret = init_single_clk(dev, i);
  224. if (ret) {
  225. debug("%s: Failed to initialize %s clock\n",
  226. dev->name, names[i]);
  227. return ret;
  228. }
  229. }
  230. return 0;
  231. }
  232. static int mpc83xx_clk_request(struct clk *clock)
  233. {
  234. /* Reject requests of clocks that are not available */
  235. if (is_clk_valid(clock->dev, clock->id))
  236. return 0;
  237. else
  238. return -ENODEV;
  239. }
  240. static ulong mpc83xx_clk_get_rate(struct clk *clk)
  241. {
  242. struct mpc83xx_clk_priv *priv = dev_get_priv(clk->dev);
  243. if (clk->id >= MPC83XX_CLK_COUNT) {
  244. debug("%s: clock index %lu invalid\n", __func__, clk->id);
  245. return 0;
  246. }
  247. return priv->speed[clk->id];
  248. }
  249. static int mpc83xx_clk_enable(struct clk *clk)
  250. {
  251. /* MPC83xx clocks are always enabled */
  252. return 0;
  253. }
  254. int get_clocks(void)
  255. {
  256. /* Empty implementation to keep the prototype in common.h happy */
  257. return 0;
  258. }
  259. int get_serial_clock(void)
  260. {
  261. struct mpc83xx_clk_priv *priv;
  262. struct udevice *clk;
  263. int ret;
  264. ret = uclass_first_device_err(UCLASS_CLK, &clk);
  265. if (ret) {
  266. debug("%s: Could not get clock device\n", __func__);
  267. return ret;
  268. }
  269. priv = dev_get_priv(clk);
  270. return priv->speed[MPC83XX_CLK_CSB];
  271. }
  272. const struct clk_ops mpc83xx_clk_ops = {
  273. .request = mpc83xx_clk_request,
  274. .get_rate = mpc83xx_clk_get_rate,
  275. .enable = mpc83xx_clk_enable,
  276. };
  277. static const struct udevice_id mpc83xx_clk_match[] = {
  278. { .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 },
  279. { .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 },
  280. { .compatible = "fsl,mpc8313-clk", .data = SOC_MPC8313 },
  281. { .compatible = "fsl,mpc8315-clk", .data = SOC_MPC8315 },
  282. { .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
  283. { .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 },
  284. { .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
  285. { .compatible = "fsl,mpc8379-clk", .data = SOC_MPC8379 },
  286. { /* sentinel */ }
  287. };
  288. static int mpc83xx_clk_probe(struct udevice *dev)
  289. {
  290. struct mpc83xx_clk_priv *priv = dev_get_priv(dev);
  291. ulong type;
  292. int ret;
  293. ret = init_all_clks(dev);
  294. if (ret) {
  295. debug("%s: Could not initialize all clocks (ret = %d)\n",
  296. dev->name, ret);
  297. return ret;
  298. }
  299. type = dev_get_driver_data(dev);
  300. if (mpc83xx_has_sdhc(type))
  301. gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC];
  302. gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE];
  303. gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1];
  304. if (mpc83xx_has_second_i2c(type))
  305. gd->arch.i2c2_clk = priv->speed[MPC83XX_CLK_I2C2];
  306. gd->mem_clk = priv->speed[MPC83XX_CLK_MEM];
  307. if (mpc83xx_has_pci(type))
  308. gd->pci_clk = priv->speed[MPC83XX_CLK_PCI];
  309. gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE];
  310. gd->bus_clk = priv->speed[MPC83XX_CLK_CSB];
  311. return 0;
  312. }
  313. static int mpc83xx_clk_bind(struct udevice *dev)
  314. {
  315. int ret;
  316. struct udevice *sys_child;
  317. /*
  318. * Since there is no corresponding device tree entry, and since the
  319. * clock driver has to be present in either case, bind the sysreset
  320. * driver here.
  321. */
  322. ret = device_bind_driver(dev, "mpc83xx_sysreset", "sysreset",
  323. &sys_child);
  324. if (ret)
  325. debug("%s: No sysreset driver: ret=%d\n",
  326. dev->name, ret);
  327. return 0;
  328. }
  329. U_BOOT_DRIVER(mpc83xx_clk) = {
  330. .name = "mpc83xx_clk",
  331. .id = UCLASS_CLK,
  332. .of_match = mpc83xx_clk_match,
  333. .ops = &mpc83xx_clk_ops,
  334. .probe = mpc83xx_clk_probe,
  335. .priv_auto = sizeof(struct mpc83xx_clk_priv),
  336. .bind = mpc83xx_clk_bind,
  337. };
  338. static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
  339. char *const argv[])
  340. {
  341. int i;
  342. char buf[32];
  343. struct udevice *clk;
  344. int ret;
  345. struct mpc83xx_clk_priv *priv;
  346. ret = uclass_first_device_err(UCLASS_CLK, &clk);
  347. if (ret) {
  348. debug("%s: Could not get clock device\n", __func__);
  349. return ret;
  350. }
  351. for (i = 0; i < MPC83XX_CLK_COUNT; i++) {
  352. if (!is_clk_valid(clk, i))
  353. continue;
  354. priv = dev_get_priv(clk);
  355. printf("%s = %s MHz\n", names[i], strmhz(buf, priv->speed[i]));
  356. }
  357. return 0;
  358. }
  359. U_BOOT_CMD(clocks, 1, 1, do_clocks,
  360. "display values of SoC's clocks",
  361. ""
  362. );