mpfs_clk_cfg.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Microchip Technology Inc.
  4. * Padmarao Begari <padmarao.begari@microchip.com>
  5. */
  6. #include <common.h>
  7. #include <clk.h>
  8. #include <clk-uclass.h>
  9. #include <asm/io.h>
  10. #include <dm/device.h>
  11. #include <dm/devres.h>
  12. #include <dm/uclass.h>
  13. #include <dt-bindings/clock/microchip-mpfs-clock.h>
  14. #include <linux/err.h>
  15. #include "mpfs_clk.h"
  16. #define MPFS_CFG_CLOCK "mpfs_cfg_clock"
  17. #define REG_CLOCK_CONFIG_CR 0x08
  18. /* CPU and AXI clock divisors */
  19. static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
  20. { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
  21. { 0, 0 }
  22. };
  23. /* AHB clock divisors */
  24. static const struct clk_div_table mpfs_div_ahb_table[] = {
  25. { 1, 2 }, { 2, 4}, { 3, 8 },
  26. { 0, 0 }
  27. };
  28. /**
  29. * struct mpfs_cfg_clock - per instance of configuration clock
  30. * @id: index of a configuration clock
  31. * @name: name of a configuration clock
  32. * @shift: shift to the divider bit field of a configuration clock
  33. * @width: width of the divider bit field of a configation clock
  34. * @table: clock divider table instance
  35. * @flags: common clock framework flags
  36. */
  37. struct mpfs_cfg_clock {
  38. unsigned int id;
  39. const char *name;
  40. u8 shift;
  41. u8 width;
  42. const struct clk_div_table *table;
  43. unsigned long flags;
  44. };
  45. /**
  46. * struct mpfs_cfg_hw_clock - hardware configuration clock (cpu, axi, ahb)
  47. * @cfg: configuration clock instance
  48. * @sys_base: base address of the mpfs system register
  49. * @prate: the pll clock rate
  50. * @hw: clock instance
  51. */
  52. struct mpfs_cfg_hw_clock {
  53. struct mpfs_cfg_clock cfg;
  54. void __iomem *sys_base;
  55. u32 prate;
  56. struct clk hw;
  57. };
  58. #define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
  59. static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw)
  60. {
  61. struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
  62. struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
  63. void __iomem *base_addr = cfg_hw->sys_base;
  64. unsigned long rate;
  65. u32 val;
  66. val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
  67. val &= clk_div_mask(cfg->width);
  68. rate = cfg_hw->prate / (1u << val);
  69. hw->rate = rate;
  70. return rate;
  71. }
  72. static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)
  73. {
  74. struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
  75. struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
  76. void __iomem *base_addr = cfg_hw->sys_base;
  77. u32 val;
  78. int divider_setting;
  79. divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags);
  80. if (divider_setting < 0)
  81. return divider_setting;
  82. val = readl(base_addr + REG_CLOCK_CONFIG_CR);
  83. val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
  84. val |= divider_setting << cfg->shift;
  85. writel(val, base_addr + REG_CLOCK_CONFIG_CR);
  86. return clk_get_rate(hw);
  87. }
  88. #define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \
  89. .cfg.id = _id, \
  90. .cfg.name = _name, \
  91. .cfg.shift = _shift, \
  92. .cfg.width = _width, \
  93. .cfg.table = _table, \
  94. .cfg.flags = _flags, \
  95. }
  96. static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
  97. CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, mpfs_div_cpu_axi_table, 0),
  98. CLK_CFG(CLK_AXI, "clk_axi", 2, 2, mpfs_div_cpu_axi_table, 0),
  99. CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
  100. };
  101. int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
  102. const char *parent_name)
  103. {
  104. int ret;
  105. int i, id, num_clks;
  106. const char *name;
  107. struct clk *hw;
  108. num_clks = ARRAY_SIZE(mpfs_cfg_clks);
  109. for (i = 0; i < num_clks; i++) {
  110. hw = &mpfs_cfg_clks[i].hw;
  111. mpfs_cfg_clks[i].sys_base = base;
  112. mpfs_cfg_clks[i].prate = clk_rate;
  113. name = mpfs_cfg_clks[i].cfg.name;
  114. ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent_name);
  115. if (ret)
  116. ERR_PTR(ret);
  117. id = mpfs_cfg_clks[i].cfg.id;
  118. clk_dm(id, hw);
  119. }
  120. return 0;
  121. }
  122. const struct clk_ops mpfs_cfg_clk_ops = {
  123. .set_rate = mpfs_cfg_clk_set_rate,
  124. .get_rate = mpfs_cfg_clk_recalc_rate,
  125. };
  126. U_BOOT_DRIVER(mpfs_cfg_clock) = {
  127. .name = MPFS_CFG_CLOCK,
  128. .id = UCLASS_CLK,
  129. .ops = &mpfs_cfg_clk_ops,
  130. };