clk-mtk.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2018 MediaTek Inc.
  4. * Author: Ryder Lee <ryder.lee@mediatek.com>
  5. */
  6. #ifndef __DRV_CLK_MTK_H
  7. #define __DRV_CLK_MTK_H
  8. #include <linux/bitops.h>
  9. #define CLK_XTAL 0
  10. #define MHZ (1000 * 1000)
  11. #define HAVE_RST_BAR BIT(0)
  12. #define CLK_DOMAIN_SCPSYS BIT(0)
  13. #define CLK_MUX_SETCLR_UPD BIT(1)
  14. #define CLK_GATE_SETCLR BIT(0)
  15. #define CLK_GATE_SETCLR_INV BIT(1)
  16. #define CLK_GATE_NO_SETCLR BIT(2)
  17. #define CLK_GATE_NO_SETCLR_INV BIT(3)
  18. #define CLK_GATE_MASK GENMASK(3, 0)
  19. #define CLK_PARENT_APMIXED BIT(4)
  20. #define CLK_PARENT_TOPCKGEN BIT(5)
  21. #define CLK_PARENT_MASK GENMASK(5, 4)
  22. #define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
  23. /* struct mtk_pll_data - hardware-specific PLLs data */
  24. struct mtk_pll_data {
  25. const int id;
  26. u32 reg;
  27. u32 pwr_reg;
  28. u32 en_mask;
  29. u32 pd_reg;
  30. int pd_shift;
  31. u32 flags;
  32. u32 rst_bar_mask;
  33. u64 fmax;
  34. u64 fmin;
  35. int pcwbits;
  36. int pcwibits;
  37. u32 pcw_reg;
  38. int pcw_shift;
  39. u32 pcw_chg_reg;
  40. };
  41. /**
  42. * struct mtk_fixed_clk - fixed clocks
  43. *
  44. * @id: index of clocks
  45. * @parent: index of parnet clocks
  46. * @rate: fixed rate
  47. */
  48. struct mtk_fixed_clk {
  49. const int id;
  50. const int parent;
  51. unsigned long rate;
  52. };
  53. #define FIXED_CLK(_id, _parent, _rate) { \
  54. .id = _id, \
  55. .parent = _parent, \
  56. .rate = _rate, \
  57. }
  58. /**
  59. * struct mtk_fixed_factor - fixed multiplier and divider clocks
  60. *
  61. * @id: index of clocks
  62. * @parent: index of parnet clocks
  63. * @mult: multiplier
  64. * @div: divider
  65. * @flag: hardware-specific flags
  66. */
  67. struct mtk_fixed_factor {
  68. const int id;
  69. const int parent;
  70. u32 mult;
  71. u32 div;
  72. u32 flags;
  73. };
  74. #define FACTOR(_id, _parent, _mult, _div, _flags) { \
  75. .id = _id, \
  76. .parent = _parent, \
  77. .mult = _mult, \
  78. .div = _div, \
  79. .flags = _flags, \
  80. }
  81. /**
  82. * struct mtk_composite - aggregate clock of mux, divider and gate clocks
  83. *
  84. * @id: index of clocks
  85. * @parent: index of parnet clocks
  86. * @mux_reg: hardware-specific mux register
  87. * @gate_reg: hardware-specific gate register
  88. * @mux_mask: mask to the mux bit field
  89. * @mux_shift: shift to the mux bit field
  90. * @gate_shift: shift to the gate bit field
  91. * @num_parents: number of parent clocks
  92. * @flags: hardware-specific flags
  93. */
  94. struct mtk_composite {
  95. const int id;
  96. const int *parent;
  97. u32 mux_reg;
  98. u32 mux_set_reg;
  99. u32 mux_clr_reg;
  100. u32 upd_reg;
  101. u32 gate_reg;
  102. u32 mux_mask;
  103. signed char mux_shift;
  104. signed char upd_shift;
  105. signed char gate_shift;
  106. signed char num_parents;
  107. u16 flags;
  108. };
  109. #define MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, \
  110. _flags) { \
  111. .id = _id, \
  112. .mux_reg = _reg, \
  113. .mux_shift = _shift, \
  114. .mux_mask = BIT(_width) - 1, \
  115. .gate_reg = _reg, \
  116. .gate_shift = _gate, \
  117. .parent = _parents, \
  118. .num_parents = ARRAY_SIZE(_parents), \
  119. .flags = _flags, \
  120. }
  121. #define MUX_GATE(_id, _parents, _reg, _shift, _width, _gate) \
  122. MUX_GATE_FLAGS(_id, _parents, _reg, _shift, _width, _gate, 0)
  123. #define MUX(_id, _parents, _reg, _shift, _width) { \
  124. .id = _id, \
  125. .mux_reg = _reg, \
  126. .mux_shift = _shift, \
  127. .mux_mask = BIT(_width) - 1, \
  128. .gate_shift = -1, \
  129. .parent = _parents, \
  130. .num_parents = ARRAY_SIZE(_parents), \
  131. .flags = 0, \
  132. }
  133. #define MUX_CLR_SET_UPD_FLAGS(_id, _parents, _mux_ofs, _mux_set_ofs,\
  134. _mux_clr_ofs, _shift, _width, _gate, \
  135. _upd_ofs, _upd, _flags) { \
  136. .id = _id, \
  137. .mux_reg = _mux_ofs, \
  138. .mux_set_reg = _mux_set_ofs, \
  139. .mux_clr_reg = _mux_clr_ofs, \
  140. .upd_reg = _upd_ofs, \
  141. .upd_shift = _upd, \
  142. .mux_shift = _shift, \
  143. .mux_mask = BIT(_width) - 1, \
  144. .gate_reg = _mux_ofs, \
  145. .gate_shift = _gate, \
  146. .parent = _parents, \
  147. .num_parents = ARRAY_SIZE(_parents), \
  148. .flags = _flags, \
  149. }
  150. struct mtk_gate_regs {
  151. u32 sta_ofs;
  152. u32 clr_ofs;
  153. u32 set_ofs;
  154. };
  155. /**
  156. * struct mtk_gate - gate clocks
  157. *
  158. * @id: index of gate clocks
  159. * @parent: index of parnet clocks
  160. * @regs: hardware-specific mux register
  161. * @shift: shift to the gate bit field
  162. * @flags: hardware-specific flags
  163. */
  164. struct mtk_gate {
  165. const int id;
  166. const int parent;
  167. const struct mtk_gate_regs *regs;
  168. int shift;
  169. u32 flags;
  170. };
  171. /* struct mtk_clk_tree - clock tree */
  172. struct mtk_clk_tree {
  173. unsigned long xtal_rate;
  174. unsigned long xtal2_rate;
  175. const int fdivs_offs;
  176. const int muxes_offs;
  177. const struct mtk_pll_data *plls;
  178. const struct mtk_fixed_clk *fclks;
  179. const struct mtk_fixed_factor *fdivs;
  180. const struct mtk_composite *muxes;
  181. };
  182. struct mtk_clk_priv {
  183. void __iomem *base;
  184. const struct mtk_clk_tree *tree;
  185. };
  186. struct mtk_cg_priv {
  187. void __iomem *base;
  188. const struct mtk_clk_tree *tree;
  189. const struct mtk_gate *gates;
  190. };
  191. extern const struct clk_ops mtk_clk_apmixedsys_ops;
  192. extern const struct clk_ops mtk_clk_topckgen_ops;
  193. extern const struct clk_ops mtk_clk_gate_ops;
  194. int mtk_common_clk_init(struct udevice *dev,
  195. const struct mtk_clk_tree *tree);
  196. int mtk_common_clk_gate_init(struct udevice *dev,
  197. const struct mtk_clk_tree *tree,
  198. const struct mtk_gate *gates);
  199. #endif /* __DRV_CLK_MTK_H */