clk-mt8518.c 38 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek clock driver for MT8518 SoC
  4. *
  5. * Copyright (C) 2019 BayLibre, SAS
  6. * Author: Chen Zhong <chen.zhong@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <asm/io.h>
  11. #include <dt-bindings/clock/mt8518-clk.h>
  12. #include <linux/bitops.h>
  13. #include "clk-mtk.h"
  14. #define MT8518_PLL_FMAX (3000UL * MHZ)
  15. #define MT8518_CON0_RST_BAR BIT(27)
  16. /* apmixedsys */
  17. #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  18. _pd_shift, _pcw_reg, _pcw_shift) { \
  19. .id = _id, \
  20. .reg = _reg, \
  21. .pwr_reg = _pwr_reg, \
  22. .en_mask = _en_mask, \
  23. .rst_bar_mask = MT8518_CON0_RST_BAR, \
  24. .fmax = MT8518_PLL_FMAX, \
  25. .flags = _flags, \
  26. .pcwbits = _pcwbits, \
  27. .pd_reg = _pd_reg, \
  28. .pd_shift = _pd_shift, \
  29. .pcw_reg = _pcw_reg, \
  30. .pcw_shift = _pcw_shift, \
  31. }
  32. static const struct mtk_pll_data apmixed_plls[] = {
  33. PLL(CLK_APMIXED_ARMPLL, 0x0100, 0x0110, 0x00000001,
  34. 0, 21, 0x0104, 24, 0x0104, 0),
  35. PLL(CLK_APMIXED_MAINPLL, 0x0120, 0x0130, 0x00000001,
  36. HAVE_RST_BAR, 21, 0x0124, 24, 0x0124, 0),
  37. PLL(CLK_APMIXED_UNIVPLL, 0x0140, 0x0150, 0x30000001,
  38. HAVE_RST_BAR, 7, 0x0144, 24, 0x0144, 0),
  39. PLL(CLK_APMIXED_MMPLL, 0x0160, 0x0170, 0x00000001,
  40. 0, 21, 0x0164, 24, 0x0164, 0),
  41. PLL(CLK_APMIXED_APLL1, 0x0180, 0x0190, 0x00000001,
  42. 0, 31, 0x0180, 1, 0x0184, 0),
  43. PLL(CLK_APMIXED_APLL2, 0x01A0, 0x01B0, 0x00000001,
  44. 0, 31, 0x01A0, 1, 0x01A4, 0),
  45. PLL(CLK_APMIXED_TVDPLL, 0x01C0, 0x01D0, 0x00000001,
  46. 0, 21, 0x01C4, 24, 0x01C4, 0),
  47. };
  48. /* topckgen */
  49. #define FACTOR0(_id, _parent, _mult, _div) \
  50. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  51. #define FACTOR1(_id, _parent, _mult, _div) \
  52. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  53. #define FACTOR2(_id, _parent, _mult, _div) \
  54. FACTOR(_id, _parent, _mult, _div, 0)
  55. static const struct mtk_fixed_clk top_fixed_clks[] = {
  56. FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
  57. FIXED_CLK(CLK_TOP_FQ_TRNG_OUT0, CLK_TOP_CLK_NULL, 500000000),
  58. FIXED_CLK(CLK_TOP_FQ_TRNG_OUT1, CLK_TOP_CLK_NULL, 500000000),
  59. FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
  60. };
  61. static const struct mtk_fixed_factor top_fixed_divs[] = {
  62. FACTOR2(CLK_TOP_DMPLL, CLK_XTAL, 1, 1),
  63. FACTOR0(CLK_TOP_MAINPLL_D4, CLK_APMIXED_MAINPLL, 1, 4),
  64. FACTOR0(CLK_TOP_MAINPLL_D8, CLK_APMIXED_MAINPLL, 1, 8),
  65. FACTOR0(CLK_TOP_MAINPLL_D16, CLK_APMIXED_MAINPLL, 1, 16),
  66. FACTOR0(CLK_TOP_MAINPLL_D11, CLK_APMIXED_MAINPLL, 1, 11),
  67. FACTOR0(CLK_TOP_MAINPLL_D22, CLK_APMIXED_MAINPLL, 1, 22),
  68. FACTOR0(CLK_TOP_MAINPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
  69. FACTOR0(CLK_TOP_MAINPLL_D6, CLK_APMIXED_MAINPLL, 1, 6),
  70. FACTOR0(CLK_TOP_MAINPLL_D12, CLK_APMIXED_MAINPLL, 1, 12),
  71. FACTOR0(CLK_TOP_MAINPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  72. FACTOR0(CLK_TOP_MAINPLL_D10, CLK_APMIXED_MAINPLL, 1, 10),
  73. FACTOR0(CLK_TOP_MAINPLL_D20, CLK_APMIXED_MAINPLL, 1, 20),
  74. FACTOR0(CLK_TOP_MAINPLL_D40, CLK_APMIXED_MAINPLL, 1, 40),
  75. FACTOR0(CLK_TOP_MAINPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  76. FACTOR0(CLK_TOP_MAINPLL_D14, CLK_APMIXED_MAINPLL, 1, 14),
  77. FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
  78. FACTOR0(CLK_TOP_UNIVPLL_D4, CLK_APMIXED_UNIVPLL, 1, 4),
  79. FACTOR0(CLK_TOP_UNIVPLL_D8, CLK_APMIXED_UNIVPLL, 1, 8),
  80. FACTOR0(CLK_TOP_UNIVPLL_D16, CLK_APMIXED_UNIVPLL, 1, 16),
  81. FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
  82. FACTOR0(CLK_TOP_UNIVPLL_D6, CLK_APMIXED_UNIVPLL, 1, 6),
  83. FACTOR0(CLK_TOP_UNIVPLL_D12, CLK_APMIXED_UNIVPLL, 1, 12),
  84. FACTOR0(CLK_TOP_UNIVPLL_D24, CLK_APMIXED_UNIVPLL, 1, 24),
  85. FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
  86. FACTOR0(CLK_TOP_UNIVPLL_D20, CLK_APMIXED_UNIVPLL, 1, 20),
  87. FACTOR0(CLK_TOP_UNIVPLL_D10, CLK_APMIXED_UNIVPLL, 1, 10),
  88. FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
  89. FACTOR0(CLK_TOP_USB20_48M, CLK_APMIXED_UNIVPLL, 1, 26),
  90. FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
  91. FACTOR1(CLK_TOP_APLL1_D4, CLK_TOP_APLL1, 1, 4),
  92. FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
  93. FACTOR1(CLK_TOP_APLL2_D2, CLK_TOP_APLL2, 1, 2),
  94. FACTOR1(CLK_TOP_APLL2_D3, CLK_TOP_APLL2, 1, 3),
  95. FACTOR1(CLK_TOP_APLL2_D4, CLK_TOP_APLL2, 1, 4),
  96. FACTOR1(CLK_TOP_APLL2_D8, CLK_TOP_APLL2, 1, 8),
  97. FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
  98. FACTOR2(CLK_TOP_CLK26M_D2, CLK_XTAL, 1, 2),
  99. FACTOR2(CLK_TOP_CLK26M_D4, CLK_XTAL, 1, 4),
  100. FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
  101. FACTOR2(CLK_TOP_CLK26M_D793, CLK_XTAL, 1, 793),
  102. FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
  103. FACTOR1(CLK_TOP_TVDPLL_D2, CLK_TOP_TVDPLL, 1, 2),
  104. FACTOR1(CLK_TOP_TVDPLL_D4, CLK_TOP_TVDPLL, 1, 4),
  105. FACTOR1(CLK_TOP_TVDPLL_D8, CLK_TOP_TVDPLL, 1, 8),
  106. FACTOR1(CLK_TOP_TVDPLL_D16, CLK_TOP_TVDPLL, 1, 16),
  107. FACTOR1(CLK_TOP_USB20_CLK480M, CLK_TOP_CLK_NULL, 1, 1),
  108. FACTOR1(CLK_TOP_RG_APLL1_D2, CLK_TOP_APLL1_SRC_SEL, 1, 2),
  109. FACTOR1(CLK_TOP_RG_APLL1_D4, CLK_TOP_APLL1_SRC_SEL, 1, 4),
  110. FACTOR1(CLK_TOP_RG_APLL1_D8, CLK_TOP_APLL1_SRC_SEL, 1, 8),
  111. FACTOR1(CLK_TOP_RG_APLL1_D16, CLK_TOP_APLL1_SRC_SEL, 1, 16),
  112. FACTOR1(CLK_TOP_RG_APLL1_D3, CLK_TOP_APLL1_SRC_SEL, 1, 3),
  113. FACTOR1(CLK_TOP_RG_APLL2_D2, CLK_TOP_APLL2_SRC_SEL, 1, 2),
  114. FACTOR1(CLK_TOP_RG_APLL2_D4, CLK_TOP_APLL2_SRC_SEL, 1, 4),
  115. FACTOR1(CLK_TOP_RG_APLL2_D8, CLK_TOP_APLL2_SRC_SEL, 1, 8),
  116. FACTOR1(CLK_TOP_RG_APLL2_D16, CLK_TOP_APLL2_SRC_SEL, 1, 16),
  117. FACTOR1(CLK_TOP_RG_APLL2_D3, CLK_TOP_APLL2_SRC_SEL, 1, 3),
  118. FACTOR1(CLK_TOP_NFI1X_INFRA_BCLK, CLK_TOP_NFI2X_SEL, 1, 2),
  119. FACTOR1(CLK_TOP_AHB_INFRA_D2, CLK_TOP_AXIBUS_SEL, 1, 2),
  120. };
  121. static const int uart0_parents[] = {
  122. CLK_TOP_CLK26M,
  123. CLK_TOP_UNIVPLL_D24
  124. };
  125. static const int emi1x_parents[] = {
  126. CLK_TOP_CLK26M,
  127. CLK_TOP_DMPLL
  128. };
  129. static const int emi_ddrphy_parents[] = {
  130. CLK_TOP_EMI1X_SEL,
  131. CLK_TOP_EMI1X_SEL
  132. };
  133. static const int msdc1_parents[] = {
  134. CLK_TOP_CLK_NULL,
  135. CLK_TOP_CLK26M,
  136. CLK_TOP_UNIVPLL_D6,
  137. CLK_TOP_CLK_NULL,
  138. CLK_TOP_MAINPLL_D8,
  139. CLK_TOP_CLK_NULL,
  140. CLK_TOP_CLK_NULL,
  141. CLK_TOP_CLK_NULL,
  142. CLK_TOP_UNIVPLL_D8,
  143. CLK_TOP_CLK_NULL,
  144. CLK_TOP_CLK_NULL,
  145. CLK_TOP_CLK_NULL,
  146. CLK_TOP_CLK_NULL,
  147. CLK_TOP_CLK_NULL,
  148. CLK_TOP_CLK_NULL,
  149. CLK_TOP_CLK_NULL,
  150. CLK_TOP_MAINPLL_D16,
  151. CLK_TOP_CLK_NULL,
  152. CLK_TOP_CLK_NULL,
  153. CLK_TOP_CLK_NULL,
  154. CLK_TOP_CLK_NULL,
  155. CLK_TOP_CLK_NULL,
  156. CLK_TOP_CLK_NULL,
  157. CLK_TOP_CLK_NULL,
  158. CLK_TOP_CLK_NULL,
  159. CLK_TOP_CLK_NULL,
  160. CLK_TOP_CLK_NULL,
  161. CLK_TOP_CLK_NULL,
  162. CLK_TOP_CLK_NULL,
  163. CLK_TOP_CLK_NULL,
  164. CLK_TOP_CLK_NULL,
  165. CLK_TOP_CLK_NULL,
  166. CLK_TOP_MMPLL_D2,
  167. CLK_TOP_CLK_NULL,
  168. CLK_TOP_CLK_NULL,
  169. CLK_TOP_CLK_NULL,
  170. CLK_TOP_CLK_NULL,
  171. CLK_TOP_CLK_NULL,
  172. CLK_TOP_CLK_NULL,
  173. CLK_TOP_CLK_NULL,
  174. CLK_TOP_CLK_NULL,
  175. CLK_TOP_CLK_NULL,
  176. CLK_TOP_CLK_NULL,
  177. CLK_TOP_CLK_NULL,
  178. CLK_TOP_CLK_NULL,
  179. CLK_TOP_CLK_NULL,
  180. CLK_TOP_CLK_NULL,
  181. CLK_TOP_CLK_NULL,
  182. CLK_TOP_CLK_NULL,
  183. CLK_TOP_CLK_NULL,
  184. CLK_TOP_CLK_NULL,
  185. CLK_TOP_CLK_NULL,
  186. CLK_TOP_CLK_NULL,
  187. CLK_TOP_CLK_NULL,
  188. CLK_TOP_CLK_NULL,
  189. CLK_TOP_CLK_NULL,
  190. CLK_TOP_CLK_NULL,
  191. CLK_TOP_CLK_NULL,
  192. CLK_TOP_CLK_NULL,
  193. CLK_TOP_CLK_NULL,
  194. CLK_TOP_CLK_NULL,
  195. CLK_TOP_CLK_NULL,
  196. CLK_TOP_CLK_NULL,
  197. CLK_TOP_CLK_NULL,
  198. CLK_TOP_MAINPLL_D12
  199. };
  200. static const int pwm_mm_parents[] = {
  201. CLK_TOP_CLK26M,
  202. CLK_TOP_UNIVPLL_D12
  203. };
  204. static const int pmicspi_parents[] = {
  205. CLK_TOP_UNIVPLL_D20,
  206. CLK_TOP_USB20_48M,
  207. CLK_TOP_UNIVPLL_D16,
  208. CLK_TOP_CLK26M,
  209. CLK_TOP_CLK26M_D2
  210. };
  211. static const int nfi2x_parents[] = {
  212. CLK_TOP_CLK26M,
  213. CLK_TOP_MAINPLL_D4,
  214. CLK_TOP_MAINPLL_D5,
  215. CLK_TOP_MAINPLL_D6,
  216. CLK_TOP_MAINPLL_D7,
  217. CLK_TOP_MAINPLL_D8,
  218. CLK_TOP_MAINPLL_D10,
  219. CLK_TOP_MAINPLL_D12
  220. };
  221. static const int ddrphycfg_parents[] = {
  222. CLK_TOP_CLK26M,
  223. CLK_TOP_MAINPLL_D16
  224. };
  225. static const int smi_parents[] = {
  226. CLK_TOP_CLK_NULL,
  227. CLK_TOP_CLK26M,
  228. CLK_TOP_CLK_NULL,
  229. CLK_TOP_CLK_NULL,
  230. CLK_TOP_CLK_NULL,
  231. CLK_TOP_CLK_NULL,
  232. CLK_TOP_CLK_NULL,
  233. CLK_TOP_CLK_NULL,
  234. CLK_TOP_CLK_NULL,
  235. CLK_TOP_UNIVPLL_D4,
  236. CLK_TOP_MAINPLL_D7,
  237. CLK_TOP_CLK_NULL,
  238. CLK_TOP_MAINPLL_D14
  239. };
  240. static const int usb_parents[] = {
  241. CLK_TOP_CLK_NULL,
  242. CLK_TOP_CLK26M,
  243. CLK_TOP_UNIVPLL_D16,
  244. CLK_TOP_CLK_NULL,
  245. CLK_TOP_MAINPLL_D20
  246. };
  247. static const int spinor_parents[] = {
  248. CLK_TOP_CLK26M_D2,
  249. CLK_TOP_CLK26M,
  250. CLK_TOP_MAINPLL_D40,
  251. CLK_TOP_UNIVPLL_D24,
  252. CLK_TOP_UNIVPLL_D20,
  253. CLK_TOP_MAINPLL_D20,
  254. CLK_TOP_MAINPLL_D16,
  255. CLK_TOP_UNIVPLL_D12
  256. };
  257. static const int eth_parents[] = {
  258. CLK_TOP_CLK26M,
  259. CLK_TOP_MAINPLL_D40,
  260. CLK_TOP_UNIVPLL_D24,
  261. CLK_TOP_UNIVPLL_D20,
  262. CLK_TOP_MAINPLL_D20
  263. };
  264. static const int aud1_parents[] = {
  265. CLK_TOP_CLK26M,
  266. CLK_TOP_APLL1_SRC_SEL
  267. };
  268. static const int aud2_parents[] = {
  269. CLK_TOP_CLK26M,
  270. CLK_TOP_APLL2_SRC_SEL
  271. };
  272. static const int i2c_parents[] = {
  273. CLK_TOP_CLK26M,
  274. CLK_TOP_USB20_48M,
  275. CLK_TOP_UNIVPLL_D12,
  276. CLK_TOP_UNIVPLL_D10,
  277. CLK_TOP_UNIVPLL_D8
  278. };
  279. static const int aud_i2s0_m_parents[] = {
  280. CLK_TOP_AUD1,
  281. CLK_TOP_AUD2
  282. };
  283. static const int aud_spdifin_parents[] = {
  284. CLK_TOP_CLK26M,
  285. CLK_TOP_UNIVPLL_D2,
  286. CLK_TOP_TVDPLL
  287. };
  288. static const int dbg_atclk_parents[] = {
  289. CLK_TOP_CLK_NULL,
  290. CLK_TOP_CLK26M,
  291. CLK_TOP_MAINPLL_D5,
  292. CLK_TOP_CLK_NULL,
  293. CLK_TOP_UNIVPLL_D5
  294. };
  295. static const int png_sys_parents[] = {
  296. CLK_TOP_CLK26M,
  297. CLK_TOP_UNIVPLL_D8,
  298. CLK_TOP_MAINPLL_D7,
  299. CLK_TOP_MAINPLL_D6,
  300. CLK_TOP_MAINPLL_D5,
  301. CLK_TOP_UNIVPLL_D3
  302. };
  303. static const int sej_13m_parents[] = {
  304. CLK_TOP_CLK26M,
  305. CLK_TOP_CLK26M_D2
  306. };
  307. static const int imgrz_sys_parents[] = {
  308. CLK_TOP_CLK26M,
  309. CLK_TOP_MAINPLL_D6,
  310. CLK_TOP_MAINPLL_D7,
  311. CLK_TOP_MAINPLL_D5,
  312. CLK_TOP_UNIVPLL_D4,
  313. CLK_TOP_UNIVPLL_D10,
  314. CLK_TOP_UNIVPLL_D5,
  315. CLK_TOP_UNIVPLL_D6
  316. };
  317. static const int graph_eclk_parents[] = {
  318. CLK_TOP_CLK26M,
  319. CLK_TOP_MAINPLL_D6,
  320. CLK_TOP_UNIVPLL_D8,
  321. CLK_TOP_UNIVPLL_D16,
  322. CLK_TOP_MAINPLL_D7,
  323. CLK_TOP_UNIVPLL_D4,
  324. CLK_TOP_UNIVPLL_D10,
  325. CLK_TOP_UNIVPLL_D24,
  326. CLK_TOP_MAINPLL_D8
  327. };
  328. static const int fdbi_parents[] = {
  329. CLK_TOP_CLK26M,
  330. CLK_TOP_MAINPLL_D12,
  331. CLK_TOP_MAINPLL_D14,
  332. CLK_TOP_MAINPLL_D16,
  333. CLK_TOP_UNIVPLL_D10,
  334. CLK_TOP_UNIVPLL_D12,
  335. CLK_TOP_UNIVPLL_D16,
  336. CLK_TOP_UNIVPLL_D24,
  337. CLK_TOP_TVDPLL_D2,
  338. CLK_TOP_TVDPLL_D4,
  339. CLK_TOP_TVDPLL_D8,
  340. CLK_TOP_TVDPLL_D16
  341. };
  342. static const int faudio_parents[] = {
  343. CLK_TOP_CLK26M,
  344. CLK_TOP_UNIVPLL_D24,
  345. CLK_TOP_APLL1_D4,
  346. CLK_TOP_APLL2_D4
  347. };
  348. static const int fa2sys_parents[] = {
  349. CLK_TOP_CLK26M,
  350. CLK_TOP_APLL1_SRC_SEL,
  351. CLK_TOP_RG_APLL1_D2,
  352. CLK_TOP_RG_APLL1_D4,
  353. CLK_TOP_RG_APLL1_D8,
  354. CLK_TOP_RG_APLL1_D16,
  355. CLK_TOP_CLK26M_D2,
  356. CLK_TOP_RG_APLL1_D3
  357. };
  358. static const int fa1sys_parents[] = {
  359. CLK_TOP_CLK26M,
  360. CLK_TOP_APLL2_SRC_SEL,
  361. CLK_TOP_RG_APLL2_D2,
  362. CLK_TOP_RG_APLL2_D4,
  363. CLK_TOP_RG_APLL2_D8,
  364. CLK_TOP_RG_APLL2_D16,
  365. CLK_TOP_CLK26M_D2,
  366. CLK_TOP_RG_APLL2_D3
  367. };
  368. static const int fasm_m_parents[] = {
  369. CLK_TOP_CLK26M,
  370. CLK_TOP_UNIVPLL_D12,
  371. CLK_TOP_UNIVPLL_D6,
  372. CLK_TOP_MAINPLL_D7
  373. };
  374. static const int fecc_ck_parents[] = {
  375. CLK_TOP_CLK_NULL,
  376. CLK_TOP_CLK_NULL,
  377. CLK_TOP_CLK_NULL,
  378. CLK_TOP_CLK_NULL,
  379. CLK_TOP_CLK_NULL,
  380. CLK_TOP_CLK_NULL,
  381. CLK_TOP_CLK_NULL,
  382. CLK_TOP_CLK_NULL,
  383. CLK_TOP_CLK_NULL,
  384. CLK_TOP_CLK26M,
  385. CLK_TOP_UNIVPLL_D6,
  386. CLK_TOP_CLK_NULL,
  387. CLK_TOP_UNIVPLL_D4,
  388. CLK_TOP_CLK_NULL,
  389. CLK_TOP_CLK_NULL,
  390. CLK_TOP_CLK_NULL,
  391. CLK_TOP_UNIVPLL_D3,
  392. CLK_TOP_CLK_NULL,
  393. CLK_TOP_CLK_NULL,
  394. CLK_TOP_CLK_NULL,
  395. CLK_TOP_CLK_NULL,
  396. CLK_TOP_CLK_NULL,
  397. CLK_TOP_CLK_NULL,
  398. CLK_TOP_CLK_NULL,
  399. CLK_TOP_CLK_NULL,
  400. CLK_TOP_CLK_NULL,
  401. CLK_TOP_CLK_NULL,
  402. CLK_TOP_CLK_NULL,
  403. CLK_TOP_CLK_NULL,
  404. CLK_TOP_CLK_NULL,
  405. CLK_TOP_CLK_NULL,
  406. CLK_TOP_CLK_NULL,
  407. CLK_TOP_MAINPLL_D3
  408. };
  409. static const int pe2_mac_parents[] = {
  410. CLK_TOP_CLK26M,
  411. CLK_TOP_MAINPLL_D11,
  412. CLK_TOP_MAINPLL_D16,
  413. CLK_TOP_UNIVPLL_D12,
  414. CLK_TOP_UNIVPLL_D10
  415. };
  416. static const int cmsys_parents[] = {
  417. CLK_TOP_CLK26M,
  418. CLK_TOP_UNIVPLL_D5,
  419. CLK_TOP_UNIVPLL_D6,
  420. CLK_TOP_MAINPLL_D5,
  421. CLK_TOP_APLL2,
  422. CLK_TOP_APLL2_D2,
  423. CLK_TOP_APLL2_D4,
  424. CLK_TOP_APLL2_D3
  425. };
  426. static const int gcpu_parents[] = {
  427. CLK_TOP_CLK26M,
  428. CLK_TOP_MAINPLL_D4,
  429. CLK_TOP_MAINPLL_D5,
  430. CLK_TOP_MAINPLL_D6,
  431. CLK_TOP_MAINPLL_D7,
  432. CLK_TOP_UNIVPLL_D4,
  433. CLK_TOP_UNIVPLL_D10,
  434. CLK_TOP_UNIVPLL_D3
  435. };
  436. static const int spis_ck_parents[] = {
  437. CLK_TOP_CLK_NULL,
  438. CLK_TOP_CLK26M,
  439. CLK_TOP_UNIVPLL_D12,
  440. CLK_TOP_CLK_NULL,
  441. CLK_TOP_UNIVPLL_D8,
  442. CLK_TOP_CLK_NULL,
  443. CLK_TOP_CLK_NULL,
  444. CLK_TOP_CLK_NULL,
  445. CLK_TOP_UNIVPLL_D6,
  446. CLK_TOP_CLK_NULL,
  447. CLK_TOP_CLK_NULL,
  448. CLK_TOP_CLK_NULL,
  449. CLK_TOP_CLK_NULL,
  450. CLK_TOP_CLK_NULL,
  451. CLK_TOP_CLK_NULL,
  452. CLK_TOP_CLK_NULL,
  453. CLK_TOP_UNIVPLL_D5,
  454. CLK_TOP_CLK_NULL,
  455. CLK_TOP_CLK_NULL,
  456. CLK_TOP_CLK_NULL,
  457. CLK_TOP_CLK_NULL,
  458. CLK_TOP_CLK_NULL,
  459. CLK_TOP_CLK_NULL,
  460. CLK_TOP_CLK_NULL,
  461. CLK_TOP_CLK_NULL,
  462. CLK_TOP_CLK_NULL,
  463. CLK_TOP_CLK_NULL,
  464. CLK_TOP_CLK_NULL,
  465. CLK_TOP_CLK_NULL,
  466. CLK_TOP_CLK_NULL,
  467. CLK_TOP_CLK_NULL,
  468. CLK_TOP_CLK_NULL,
  469. CLK_TOP_UNIVPLL_D4,
  470. CLK_TOP_CLK_NULL,
  471. CLK_TOP_CLK_NULL,
  472. CLK_TOP_CLK_NULL,
  473. CLK_TOP_CLK_NULL,
  474. CLK_TOP_CLK_NULL,
  475. CLK_TOP_CLK_NULL,
  476. CLK_TOP_CLK_NULL,
  477. CLK_TOP_CLK_NULL,
  478. CLK_TOP_CLK_NULL,
  479. CLK_TOP_CLK_NULL,
  480. CLK_TOP_CLK_NULL,
  481. CLK_TOP_CLK_NULL,
  482. CLK_TOP_CLK_NULL,
  483. CLK_TOP_CLK_NULL,
  484. CLK_TOP_CLK_NULL,
  485. CLK_TOP_CLK_NULL,
  486. CLK_TOP_CLK_NULL,
  487. CLK_TOP_CLK_NULL,
  488. CLK_TOP_CLK_NULL,
  489. CLK_TOP_CLK_NULL,
  490. CLK_TOP_CLK_NULL,
  491. CLK_TOP_CLK_NULL,
  492. CLK_TOP_CLK_NULL,
  493. CLK_TOP_CLK_NULL,
  494. CLK_TOP_CLK_NULL,
  495. CLK_TOP_CLK_NULL,
  496. CLK_TOP_CLK_NULL,
  497. CLK_TOP_CLK_NULL,
  498. CLK_TOP_CLK_NULL,
  499. CLK_TOP_CLK_NULL,
  500. CLK_TOP_CLK_NULL,
  501. CLK_TOP_MAINPLL_D4,
  502. CLK_TOP_CLK_NULL,
  503. CLK_TOP_CLK_NULL,
  504. CLK_TOP_CLK_NULL,
  505. CLK_TOP_CLK_NULL,
  506. CLK_TOP_CLK_NULL,
  507. CLK_TOP_CLK_NULL,
  508. CLK_TOP_CLK_NULL,
  509. CLK_TOP_CLK_NULL,
  510. CLK_TOP_CLK_NULL,
  511. CLK_TOP_CLK_NULL,
  512. CLK_TOP_CLK_NULL,
  513. CLK_TOP_CLK_NULL,
  514. CLK_TOP_CLK_NULL,
  515. CLK_TOP_CLK_NULL,
  516. CLK_TOP_CLK_NULL,
  517. CLK_TOP_CLK_NULL,
  518. CLK_TOP_CLK_NULL,
  519. CLK_TOP_CLK_NULL,
  520. CLK_TOP_CLK_NULL,
  521. CLK_TOP_CLK_NULL,
  522. CLK_TOP_CLK_NULL,
  523. CLK_TOP_CLK_NULL,
  524. CLK_TOP_CLK_NULL,
  525. CLK_TOP_CLK_NULL,
  526. CLK_TOP_CLK_NULL,
  527. CLK_TOP_CLK_NULL,
  528. CLK_TOP_CLK_NULL,
  529. CLK_TOP_CLK_NULL,
  530. CLK_TOP_CLK_NULL,
  531. CLK_TOP_CLK_NULL,
  532. CLK_TOP_CLK_NULL,
  533. CLK_TOP_CLK_NULL,
  534. CLK_TOP_CLK_NULL,
  535. CLK_TOP_CLK_NULL,
  536. CLK_TOP_CLK_NULL,
  537. CLK_TOP_CLK_NULL,
  538. CLK_TOP_CLK_NULL,
  539. CLK_TOP_CLK_NULL,
  540. CLK_TOP_CLK_NULL,
  541. CLK_TOP_CLK_NULL,
  542. CLK_TOP_CLK_NULL,
  543. CLK_TOP_CLK_NULL,
  544. CLK_TOP_CLK_NULL,
  545. CLK_TOP_CLK_NULL,
  546. CLK_TOP_CLK_NULL,
  547. CLK_TOP_CLK_NULL,
  548. CLK_TOP_CLK_NULL,
  549. CLK_TOP_CLK_NULL,
  550. CLK_TOP_CLK_NULL,
  551. CLK_TOP_CLK_NULL,
  552. CLK_TOP_CLK_NULL,
  553. CLK_TOP_CLK_NULL,
  554. CLK_TOP_CLK_NULL,
  555. CLK_TOP_CLK_NULL,
  556. CLK_TOP_CLK_NULL,
  557. CLK_TOP_CLK_NULL,
  558. CLK_TOP_CLK_NULL,
  559. CLK_TOP_CLK_NULL,
  560. CLK_TOP_CLK_NULL,
  561. CLK_TOP_CLK_NULL,
  562. CLK_TOP_CLK_NULL,
  563. CLK_TOP_CLK_NULL,
  564. CLK_TOP_CLK_NULL,
  565. CLK_TOP_UNIVPLL_D3
  566. };
  567. static const int apll1_ref_parents[] = {
  568. CLK_TOP_CLK_NULL,
  569. CLK_TOP_CLK_NULL,
  570. CLK_TOP_CLK_NULL,
  571. CLK_TOP_CLK_NULL,
  572. CLK_TOP_CLK_NULL,
  573. CLK_TOP_CLK_NULL
  574. };
  575. static const int int_32k_parents[] = {
  576. CLK_TOP_CLK32K,
  577. CLK_TOP_CLK26M_D793
  578. };
  579. static const int apll1_src_parents[] = {
  580. CLK_TOP_APLL1,
  581. CLK_TOP_CLK_NULL,
  582. CLK_TOP_CLK_NULL,
  583. CLK_TOP_CLK_NULL
  584. };
  585. static const int apll2_src_parents[] = {
  586. CLK_TOP_APLL2,
  587. CLK_TOP_CLK_NULL,
  588. CLK_TOP_CLK_NULL,
  589. CLK_TOP_CLK_NULL
  590. };
  591. static const int faud_intbus_parents[] = {
  592. CLK_TOP_CLK_NULL,
  593. CLK_TOP_CLK26M,
  594. CLK_TOP_MAINPLL_D11,
  595. CLK_TOP_CLK_NULL,
  596. CLK_TOP_CLK26M,
  597. CLK_TOP_CLK_NULL,
  598. CLK_TOP_CLK_NULL,
  599. CLK_TOP_CLK_NULL,
  600. CLK_TOP_UNIVPLL_D10,
  601. CLK_TOP_CLK_NULL,
  602. CLK_TOP_CLK_NULL,
  603. CLK_TOP_CLK_NULL,
  604. CLK_TOP_CLK_NULL,
  605. CLK_TOP_CLK_NULL,
  606. CLK_TOP_CLK_NULL,
  607. CLK_TOP_CLK_NULL,
  608. CLK_TOP_RG_APLL2_D8,
  609. CLK_TOP_CLK_NULL,
  610. CLK_TOP_CLK_NULL,
  611. CLK_TOP_CLK_NULL,
  612. CLK_TOP_CLK_NULL,
  613. CLK_TOP_CLK_NULL,
  614. CLK_TOP_CLK_NULL,
  615. CLK_TOP_CLK_NULL,
  616. CLK_TOP_CLK_NULL,
  617. CLK_TOP_CLK_NULL,
  618. CLK_TOP_CLK_NULL,
  619. CLK_TOP_CLK_NULL,
  620. CLK_TOP_CLK_NULL,
  621. CLK_TOP_CLK_NULL,
  622. CLK_TOP_CLK_NULL,
  623. CLK_TOP_CLK_NULL,
  624. CLK_TOP_CLK26M_D2,
  625. CLK_TOP_CLK_NULL,
  626. CLK_TOP_CLK_NULL,
  627. CLK_TOP_CLK_NULL,
  628. CLK_TOP_CLK_NULL,
  629. CLK_TOP_CLK_NULL,
  630. CLK_TOP_CLK_NULL,
  631. CLK_TOP_CLK_NULL,
  632. CLK_TOP_CLK_NULL,
  633. CLK_TOP_CLK_NULL,
  634. CLK_TOP_CLK_NULL,
  635. CLK_TOP_CLK_NULL,
  636. CLK_TOP_CLK_NULL,
  637. CLK_TOP_CLK_NULL,
  638. CLK_TOP_CLK_NULL,
  639. CLK_TOP_CLK_NULL,
  640. CLK_TOP_CLK_NULL,
  641. CLK_TOP_CLK_NULL,
  642. CLK_TOP_CLK_NULL,
  643. CLK_TOP_CLK_NULL,
  644. CLK_TOP_CLK_NULL,
  645. CLK_TOP_CLK_NULL,
  646. CLK_TOP_CLK_NULL,
  647. CLK_TOP_CLK_NULL,
  648. CLK_TOP_CLK_NULL,
  649. CLK_TOP_CLK_NULL,
  650. CLK_TOP_CLK_NULL,
  651. CLK_TOP_CLK_NULL,
  652. CLK_TOP_CLK_NULL,
  653. CLK_TOP_CLK_NULL,
  654. CLK_TOP_CLK_NULL,
  655. CLK_TOP_CLK_NULL,
  656. CLK_TOP_RG_APLL1_D8,
  657. CLK_TOP_CLK_NULL,
  658. CLK_TOP_CLK_NULL,
  659. CLK_TOP_CLK_NULL,
  660. CLK_TOP_CLK_NULL,
  661. CLK_TOP_CLK_NULL,
  662. CLK_TOP_CLK_NULL,
  663. CLK_TOP_CLK_NULL,
  664. CLK_TOP_CLK_NULL,
  665. CLK_TOP_CLK_NULL,
  666. CLK_TOP_CLK_NULL,
  667. CLK_TOP_CLK_NULL,
  668. CLK_TOP_CLK_NULL,
  669. CLK_TOP_CLK_NULL,
  670. CLK_TOP_CLK_NULL,
  671. CLK_TOP_CLK_NULL,
  672. CLK_TOP_CLK_NULL,
  673. CLK_TOP_CLK_NULL,
  674. CLK_TOP_CLK_NULL,
  675. CLK_TOP_CLK_NULL,
  676. CLK_TOP_CLK_NULL,
  677. CLK_TOP_CLK_NULL,
  678. CLK_TOP_CLK_NULL,
  679. CLK_TOP_CLK_NULL,
  680. CLK_TOP_CLK_NULL,
  681. CLK_TOP_CLK_NULL,
  682. CLK_TOP_CLK_NULL,
  683. CLK_TOP_CLK_NULL,
  684. CLK_TOP_CLK_NULL,
  685. CLK_TOP_CLK_NULL,
  686. CLK_TOP_CLK_NULL,
  687. CLK_TOP_CLK_NULL,
  688. CLK_TOP_CLK_NULL,
  689. CLK_TOP_CLK_NULL,
  690. CLK_TOP_CLK_NULL,
  691. CLK_TOP_CLK_NULL,
  692. CLK_TOP_CLK_NULL,
  693. CLK_TOP_CLK_NULL,
  694. CLK_TOP_CLK_NULL,
  695. CLK_TOP_CLK_NULL,
  696. CLK_TOP_CLK_NULL,
  697. CLK_TOP_CLK_NULL,
  698. CLK_TOP_CLK_NULL,
  699. CLK_TOP_CLK_NULL,
  700. CLK_TOP_CLK_NULL,
  701. CLK_TOP_CLK_NULL,
  702. CLK_TOP_CLK_NULL,
  703. CLK_TOP_CLK_NULL,
  704. CLK_TOP_CLK_NULL,
  705. CLK_TOP_CLK_NULL,
  706. CLK_TOP_CLK_NULL,
  707. CLK_TOP_CLK_NULL,
  708. CLK_TOP_CLK_NULL,
  709. CLK_TOP_CLK_NULL,
  710. CLK_TOP_CLK_NULL,
  711. CLK_TOP_CLK_NULL,
  712. CLK_TOP_CLK_NULL,
  713. CLK_TOP_CLK_NULL,
  714. CLK_TOP_CLK_NULL,
  715. CLK_TOP_CLK_NULL,
  716. CLK_TOP_CLK_NULL,
  717. CLK_TOP_CLK_NULL,
  718. CLK_TOP_CLK_NULL,
  719. CLK_TOP_CLK_NULL,
  720. CLK_TOP_UNIVPLL_D20
  721. };
  722. static const int axibus_parents[] = {
  723. CLK_TOP_CLK_NULL,
  724. CLK_TOP_CLK26M,
  725. CLK_TOP_MAINPLL_D11,
  726. CLK_TOP_CLK_NULL,
  727. CLK_TOP_MAINPLL_D12,
  728. CLK_TOP_CLK_NULL,
  729. CLK_TOP_CLK_NULL,
  730. CLK_TOP_CLK_NULL,
  731. CLK_TOP_UNIVPLL_D10,
  732. CLK_TOP_CLK_NULL,
  733. CLK_TOP_CLK_NULL,
  734. CLK_TOP_CLK_NULL,
  735. CLK_TOP_CLK_NULL,
  736. CLK_TOP_CLK_NULL,
  737. CLK_TOP_CLK_NULL,
  738. CLK_TOP_CLK_NULL,
  739. CLK_TOP_CLK26M_D2,
  740. CLK_TOP_CLK_NULL,
  741. CLK_TOP_CLK_NULL,
  742. CLK_TOP_CLK_NULL,
  743. CLK_TOP_CLK_NULL,
  744. CLK_TOP_CLK_NULL,
  745. CLK_TOP_CLK_NULL,
  746. CLK_TOP_CLK_NULL,
  747. CLK_TOP_CLK_NULL,
  748. CLK_TOP_CLK_NULL,
  749. CLK_TOP_CLK_NULL,
  750. CLK_TOP_CLK_NULL,
  751. CLK_TOP_CLK_NULL,
  752. CLK_TOP_CLK_NULL,
  753. CLK_TOP_CLK_NULL,
  754. CLK_TOP_CLK_NULL,
  755. CLK_TOP_APLL2_D8
  756. };
  757. static const int hapll1_parents[] = {
  758. CLK_TOP_CLK26M,
  759. CLK_TOP_APLL1_SRC_SEL,
  760. CLK_TOP_RG_APLL1_D2,
  761. CLK_TOP_RG_APLL1_D4,
  762. CLK_TOP_RG_APLL1_D8,
  763. CLK_TOP_RG_APLL1_D16,
  764. CLK_TOP_CLK26M_D2,
  765. CLK_TOP_CLK26M_D8,
  766. CLK_TOP_RG_APLL1_D3
  767. };
  768. static const int hapll2_parents[] = {
  769. CLK_TOP_CLK26M,
  770. CLK_TOP_APLL2_SRC_SEL,
  771. CLK_TOP_RG_APLL2_D2,
  772. CLK_TOP_RG_APLL2_D4,
  773. CLK_TOP_RG_APLL2_D8,
  774. CLK_TOP_RG_APLL2_D16,
  775. CLK_TOP_CLK26M_D2,
  776. CLK_TOP_CLK26M_D4,
  777. CLK_TOP_RG_APLL2_D3
  778. };
  779. static const int spinfi_parents[] = {
  780. CLK_TOP_CLK26M,
  781. CLK_TOP_UNIVPLL_D24,
  782. CLK_TOP_UNIVPLL_D20,
  783. CLK_TOP_MAINPLL_D22,
  784. CLK_TOP_UNIVPLL_D16,
  785. CLK_TOP_MAINPLL_D16,
  786. CLK_TOP_UNIVPLL_D12,
  787. CLK_TOP_UNIVPLL_D10,
  788. CLK_TOP_MAINPLL_D11
  789. };
  790. static const int msdc0_parents[] = {
  791. CLK_TOP_CLK_NULL,
  792. CLK_TOP_CLK26M,
  793. CLK_TOP_UNIVPLL_D6,
  794. CLK_TOP_CLK_NULL,
  795. CLK_TOP_MAINPLL_D8,
  796. CLK_TOP_CLK_NULL,
  797. CLK_TOP_CLK_NULL,
  798. CLK_TOP_CLK_NULL,
  799. CLK_TOP_UNIVPLL_D8,
  800. CLK_TOP_CLK_NULL,
  801. CLK_TOP_CLK_NULL,
  802. CLK_TOP_CLK_NULL,
  803. CLK_TOP_CLK_NULL,
  804. CLK_TOP_CLK_NULL,
  805. CLK_TOP_CLK_NULL,
  806. CLK_TOP_CLK_NULL,
  807. CLK_TOP_MAINPLL_D16,
  808. CLK_TOP_CLK_NULL,
  809. CLK_TOP_CLK_NULL,
  810. CLK_TOP_CLK_NULL,
  811. CLK_TOP_CLK_NULL,
  812. CLK_TOP_CLK_NULL,
  813. CLK_TOP_CLK_NULL,
  814. CLK_TOP_CLK_NULL,
  815. CLK_TOP_CLK_NULL,
  816. CLK_TOP_CLK_NULL,
  817. CLK_TOP_CLK_NULL,
  818. CLK_TOP_CLK_NULL,
  819. CLK_TOP_CLK_NULL,
  820. CLK_TOP_CLK_NULL,
  821. CLK_TOP_CLK_NULL,
  822. CLK_TOP_CLK_NULL,
  823. CLK_TOP_MAINPLL_D12,
  824. CLK_TOP_CLK_NULL,
  825. CLK_TOP_CLK_NULL,
  826. CLK_TOP_CLK_NULL,
  827. CLK_TOP_CLK_NULL,
  828. CLK_TOP_CLK_NULL,
  829. CLK_TOP_CLK_NULL,
  830. CLK_TOP_CLK_NULL,
  831. CLK_TOP_CLK_NULL,
  832. CLK_TOP_CLK_NULL,
  833. CLK_TOP_CLK_NULL,
  834. CLK_TOP_CLK_NULL,
  835. CLK_TOP_CLK_NULL,
  836. CLK_TOP_CLK_NULL,
  837. CLK_TOP_CLK_NULL,
  838. CLK_TOP_CLK_NULL,
  839. CLK_TOP_CLK_NULL,
  840. CLK_TOP_CLK_NULL,
  841. CLK_TOP_CLK_NULL,
  842. CLK_TOP_CLK_NULL,
  843. CLK_TOP_CLK_NULL,
  844. CLK_TOP_CLK_NULL,
  845. CLK_TOP_CLK_NULL,
  846. CLK_TOP_CLK_NULL,
  847. CLK_TOP_CLK_NULL,
  848. CLK_TOP_CLK_NULL,
  849. CLK_TOP_CLK_NULL,
  850. CLK_TOP_CLK_NULL,
  851. CLK_TOP_CLK_NULL,
  852. CLK_TOP_CLK_NULL,
  853. CLK_TOP_CLK_NULL,
  854. CLK_TOP_CLK_NULL,
  855. CLK_APMIXED_MMPLL,
  856. CLK_TOP_CLK_NULL,
  857. CLK_TOP_CLK_NULL,
  858. CLK_TOP_CLK_NULL,
  859. CLK_TOP_CLK_NULL,
  860. CLK_TOP_CLK_NULL,
  861. CLK_TOP_CLK_NULL,
  862. CLK_TOP_CLK_NULL,
  863. CLK_TOP_CLK_NULL,
  864. CLK_TOP_CLK_NULL,
  865. CLK_TOP_CLK_NULL,
  866. CLK_TOP_CLK_NULL,
  867. CLK_TOP_CLK_NULL,
  868. CLK_TOP_CLK_NULL,
  869. CLK_TOP_CLK_NULL,
  870. CLK_TOP_CLK_NULL,
  871. CLK_TOP_CLK_NULL,
  872. CLK_TOP_CLK_NULL,
  873. CLK_TOP_CLK_NULL,
  874. CLK_TOP_CLK_NULL,
  875. CLK_TOP_CLK_NULL,
  876. CLK_TOP_CLK_NULL,
  877. CLK_TOP_CLK_NULL,
  878. CLK_TOP_CLK_NULL,
  879. CLK_TOP_CLK_NULL,
  880. CLK_TOP_CLK_NULL,
  881. CLK_TOP_CLK_NULL,
  882. CLK_TOP_CLK_NULL,
  883. CLK_TOP_CLK_NULL,
  884. CLK_TOP_CLK_NULL,
  885. CLK_TOP_CLK_NULL,
  886. CLK_TOP_CLK_NULL,
  887. CLK_TOP_CLK_NULL,
  888. CLK_TOP_CLK_NULL,
  889. CLK_TOP_CLK_NULL,
  890. CLK_TOP_CLK_NULL,
  891. CLK_TOP_CLK_NULL,
  892. CLK_TOP_CLK_NULL,
  893. CLK_TOP_CLK_NULL,
  894. CLK_TOP_CLK_NULL,
  895. CLK_TOP_CLK_NULL,
  896. CLK_TOP_CLK_NULL,
  897. CLK_TOP_CLK_NULL,
  898. CLK_TOP_CLK_NULL,
  899. CLK_TOP_CLK_NULL,
  900. CLK_TOP_CLK_NULL,
  901. CLK_TOP_CLK_NULL,
  902. CLK_TOP_CLK_NULL,
  903. CLK_TOP_CLK_NULL,
  904. CLK_TOP_CLK_NULL,
  905. CLK_TOP_CLK_NULL,
  906. CLK_TOP_CLK_NULL,
  907. CLK_TOP_CLK_NULL,
  908. CLK_TOP_CLK_NULL,
  909. CLK_TOP_CLK_NULL,
  910. CLK_TOP_CLK_NULL,
  911. CLK_TOP_CLK_NULL,
  912. CLK_TOP_CLK_NULL,
  913. CLK_TOP_CLK_NULL,
  914. CLK_TOP_CLK_NULL,
  915. CLK_TOP_CLK_NULL,
  916. CLK_TOP_CLK_NULL,
  917. CLK_TOP_CLK_NULL,
  918. CLK_TOP_CLK_NULL,
  919. CLK_TOP_MMPLL_D2
  920. };
  921. static const int msdc0_clk50_parents[] = {
  922. CLK_TOP_CLK_NULL,
  923. CLK_TOP_CLK_NULL,
  924. CLK_TOP_CLK_NULL,
  925. CLK_TOP_CLK_NULL,
  926. CLK_TOP_CLK_NULL,
  927. CLK_TOP_CLK_NULL,
  928. CLK_TOP_CLK_NULL,
  929. CLK_TOP_CLK_NULL,
  930. CLK_TOP_CLK_NULL,
  931. CLK_TOP_CLK26M,
  932. CLK_TOP_UNIVPLL_D6,
  933. CLK_TOP_CLK_NULL,
  934. CLK_TOP_MAINPLL_D8,
  935. CLK_TOP_CLK_NULL,
  936. CLK_TOP_CLK_NULL,
  937. CLK_TOP_CLK_NULL,
  938. CLK_TOP_UNIVPLL_D8,
  939. CLK_TOP_CLK_NULL,
  940. CLK_TOP_CLK_NULL,
  941. CLK_TOP_CLK_NULL,
  942. CLK_TOP_CLK_NULL,
  943. CLK_TOP_CLK_NULL,
  944. CLK_TOP_CLK_NULL,
  945. CLK_TOP_CLK_NULL,
  946. CLK_TOP_CLK_NULL,
  947. CLK_TOP_CLK_NULL,
  948. CLK_TOP_CLK_NULL,
  949. CLK_TOP_CLK_NULL,
  950. CLK_TOP_CLK_NULL,
  951. CLK_TOP_CLK_NULL,
  952. CLK_TOP_CLK_NULL,
  953. CLK_TOP_CLK_NULL,
  954. CLK_TOP_MAINPLL_D6
  955. };
  956. static const int msdc2_parents[] = {
  957. CLK_TOP_CLK_NULL,
  958. CLK_TOP_CLK26M,
  959. CLK_TOP_UNIVPLL_D6,
  960. CLK_TOP_CLK_NULL,
  961. CLK_TOP_MAINPLL_D8,
  962. CLK_TOP_CLK_NULL,
  963. CLK_TOP_CLK_NULL,
  964. CLK_TOP_CLK_NULL,
  965. CLK_TOP_UNIVPLL_D8,
  966. CLK_TOP_CLK_NULL,
  967. CLK_TOP_CLK_NULL,
  968. CLK_TOP_CLK_NULL,
  969. CLK_TOP_CLK_NULL,
  970. CLK_TOP_CLK_NULL,
  971. CLK_TOP_CLK_NULL,
  972. CLK_TOP_CLK_NULL,
  973. CLK_TOP_MAINPLL_D16,
  974. CLK_TOP_CLK_NULL,
  975. CLK_TOP_CLK_NULL,
  976. CLK_TOP_CLK_NULL,
  977. CLK_TOP_CLK_NULL,
  978. CLK_TOP_CLK_NULL,
  979. CLK_TOP_CLK_NULL,
  980. CLK_TOP_CLK_NULL,
  981. CLK_TOP_CLK_NULL,
  982. CLK_TOP_CLK_NULL,
  983. CLK_TOP_CLK_NULL,
  984. CLK_TOP_CLK_NULL,
  985. CLK_TOP_CLK_NULL,
  986. CLK_TOP_CLK_NULL,
  987. CLK_TOP_CLK_NULL,
  988. CLK_TOP_CLK_NULL,
  989. CLK_TOP_MMPLL_D2,
  990. CLK_TOP_CLK_NULL,
  991. CLK_TOP_CLK_NULL,
  992. CLK_TOP_CLK_NULL,
  993. CLK_TOP_CLK_NULL,
  994. CLK_TOP_CLK_NULL,
  995. CLK_TOP_CLK_NULL,
  996. CLK_TOP_CLK_NULL,
  997. CLK_TOP_CLK_NULL,
  998. CLK_TOP_CLK_NULL,
  999. CLK_TOP_CLK_NULL,
  1000. CLK_TOP_CLK_NULL,
  1001. CLK_TOP_CLK_NULL,
  1002. CLK_TOP_CLK_NULL,
  1003. CLK_TOP_CLK_NULL,
  1004. CLK_TOP_CLK_NULL,
  1005. CLK_TOP_CLK_NULL,
  1006. CLK_TOP_CLK_NULL,
  1007. CLK_TOP_CLK_NULL,
  1008. CLK_TOP_CLK_NULL,
  1009. CLK_TOP_CLK_NULL,
  1010. CLK_TOP_CLK_NULL,
  1011. CLK_TOP_CLK_NULL,
  1012. CLK_TOP_CLK_NULL,
  1013. CLK_TOP_CLK_NULL,
  1014. CLK_TOP_CLK_NULL,
  1015. CLK_TOP_CLK_NULL,
  1016. CLK_TOP_CLK_NULL,
  1017. CLK_TOP_CLK_NULL,
  1018. CLK_TOP_CLK_NULL,
  1019. CLK_TOP_CLK_NULL,
  1020. CLK_TOP_CLK_NULL,
  1021. CLK_TOP_MAINPLL_D12,
  1022. CLK_TOP_CLK_NULL,
  1023. CLK_TOP_CLK_NULL,
  1024. CLK_TOP_CLK_NULL,
  1025. CLK_TOP_CLK_NULL,
  1026. CLK_TOP_CLK_NULL,
  1027. CLK_TOP_CLK_NULL,
  1028. CLK_TOP_CLK_NULL,
  1029. CLK_TOP_CLK_NULL,
  1030. CLK_TOP_CLK_NULL,
  1031. CLK_TOP_CLK_NULL,
  1032. CLK_TOP_CLK_NULL,
  1033. CLK_TOP_CLK_NULL,
  1034. CLK_TOP_CLK_NULL,
  1035. CLK_TOP_CLK_NULL,
  1036. CLK_TOP_CLK_NULL,
  1037. CLK_TOP_CLK_NULL,
  1038. CLK_TOP_CLK_NULL,
  1039. CLK_TOP_CLK_NULL,
  1040. CLK_TOP_CLK_NULL,
  1041. CLK_TOP_CLK_NULL,
  1042. CLK_TOP_CLK_NULL,
  1043. CLK_TOP_CLK_NULL,
  1044. CLK_TOP_CLK_NULL,
  1045. CLK_TOP_CLK_NULL,
  1046. CLK_TOP_CLK_NULL,
  1047. CLK_TOP_CLK_NULL,
  1048. CLK_TOP_CLK_NULL,
  1049. CLK_TOP_CLK_NULL,
  1050. CLK_TOP_CLK_NULL,
  1051. CLK_TOP_CLK_NULL,
  1052. CLK_TOP_CLK_NULL,
  1053. CLK_TOP_CLK_NULL,
  1054. CLK_TOP_CLK_NULL,
  1055. CLK_TOP_CLK_NULL,
  1056. CLK_TOP_CLK_NULL,
  1057. CLK_TOP_CLK_NULL,
  1058. CLK_TOP_CLK_NULL,
  1059. CLK_TOP_CLK_NULL,
  1060. CLK_TOP_CLK_NULL,
  1061. CLK_TOP_CLK_NULL,
  1062. CLK_TOP_CLK_NULL,
  1063. CLK_TOP_CLK_NULL,
  1064. CLK_TOP_CLK_NULL,
  1065. CLK_TOP_CLK_NULL,
  1066. CLK_TOP_CLK_NULL,
  1067. CLK_TOP_CLK_NULL,
  1068. CLK_TOP_CLK_NULL,
  1069. CLK_TOP_CLK_NULL,
  1070. CLK_TOP_CLK_NULL,
  1071. CLK_TOP_CLK_NULL,
  1072. CLK_TOP_CLK_NULL,
  1073. CLK_TOP_CLK_NULL,
  1074. CLK_TOP_CLK_NULL,
  1075. CLK_TOP_CLK_NULL,
  1076. CLK_TOP_CLK_NULL,
  1077. CLK_TOP_CLK_NULL,
  1078. CLK_TOP_CLK_NULL,
  1079. CLK_TOP_CLK_NULL,
  1080. CLK_TOP_CLK_NULL,
  1081. CLK_TOP_CLK_NULL,
  1082. CLK_TOP_CLK_NULL,
  1083. CLK_TOP_CLK_NULL,
  1084. CLK_TOP_CLK_NULL,
  1085. CLK_APMIXED_MMPLL
  1086. };
  1087. static const int disp_dpi_ck_parents[] = {
  1088. CLK_TOP_CLK_NULL,
  1089. CLK_TOP_CLK_NULL,
  1090. CLK_TOP_CLK_NULL,
  1091. CLK_TOP_CLK_NULL,
  1092. CLK_TOP_CLK_NULL,
  1093. CLK_TOP_CLK_NULL,
  1094. CLK_TOP_CLK_NULL,
  1095. CLK_TOP_CLK_NULL,
  1096. CLK_TOP_CLK_NULL,
  1097. CLK_TOP_CLK26M,
  1098. CLK_TOP_TVDPLL_D2,
  1099. CLK_TOP_CLK_NULL,
  1100. CLK_TOP_TVDPLL_D4,
  1101. CLK_TOP_CLK_NULL,
  1102. CLK_TOP_CLK_NULL,
  1103. CLK_TOP_CLK_NULL,
  1104. CLK_TOP_TVDPLL_D8,
  1105. CLK_TOP_CLK_NULL,
  1106. CLK_TOP_CLK_NULL,
  1107. CLK_TOP_CLK_NULL,
  1108. CLK_TOP_CLK_NULL,
  1109. CLK_TOP_CLK_NULL,
  1110. CLK_TOP_CLK_NULL,
  1111. CLK_TOP_CLK_NULL,
  1112. CLK_TOP_CLK_NULL,
  1113. CLK_TOP_CLK_NULL,
  1114. CLK_TOP_CLK_NULL,
  1115. CLK_TOP_CLK_NULL,
  1116. CLK_TOP_CLK_NULL,
  1117. CLK_TOP_CLK_NULL,
  1118. CLK_TOP_CLK_NULL,
  1119. CLK_TOP_CLK_NULL,
  1120. CLK_TOP_TVDPLL_D16
  1121. };
  1122. static const struct mtk_composite top_muxes[] = {
  1123. /* CLK_MUX_SEL0 */
  1124. MUX(CLK_TOP_UART0_SEL, uart0_parents, 0x000, 0, 1),
  1125. MUX(CLK_TOP_EMI1X_SEL, emi1x_parents, 0x000, 1, 1),
  1126. MUX(CLK_TOP_EMI_DDRPHY_SEL, emi_ddrphy_parents, 0x000, 2, 1),
  1127. MUX(CLK_TOP_MSDC1_SEL, msdc1_parents, 0x000, 4, 8),
  1128. MUX(CLK_TOP_PWM_MM_SEL, pwm_mm_parents, 0x000, 18, 1),
  1129. MUX(CLK_TOP_UART1_SEL, uart0_parents, 0x000, 19, 1),
  1130. MUX(CLK_TOP_SPM_52M_SEL, uart0_parents, 0x000, 22, 1),
  1131. MUX(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x000, 23, 3),
  1132. /* CLK_MUX_SEL1 */
  1133. MUX(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0x004, 0, 3),
  1134. MUX(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x004, 15, 1),
  1135. MUX(CLK_TOP_SMI_SEL, smi_parents, 0x004, 16, 4),
  1136. MUX(CLK_TOP_USB_SEL, usb_parents, 0x004, 20, 3),
  1137. /* CLK_MUX_SEL8 */
  1138. MUX(CLK_TOP_SPINOR_SEL, spinor_parents, 0x040, 0, 3),
  1139. MUX(CLK_TOP_ETH_SEL, eth_parents, 0x040, 6, 3),
  1140. MUX(CLK_TOP_AUD1_SEL, aud1_parents, 0x040, 22, 1),
  1141. MUX(CLK_TOP_AUD2_SEL, aud2_parents, 0x040, 23, 1),
  1142. MUX(CLK_TOP_I2C_SEL, i2c_parents, 0x040, 28, 3),
  1143. /* CLK_SEL_9 */
  1144. MUX(CLK_TOP_AUD_I2S0_M_SEL, aud_i2s0_m_parents, 0x044, 12, 1),
  1145. MUX(CLK_TOP_AUD_I2S3_M_SEL, aud_i2s0_m_parents, 0x044, 15, 1),
  1146. MUX(CLK_TOP_AUD_I2S4_M_SEL, aud_i2s0_m_parents, 0x044, 16, 1),
  1147. MUX(CLK_TOP_AUD_I2S6_M_SEL, aud_i2s0_m_parents, 0x044, 18, 1),
  1148. /* CLK_MUX_SEL13 */
  1149. MUX(CLK_TOP_PWM_SEL, pwm_mm_parents, 0x07c, 0, 1),
  1150. MUX(CLK_TOP_AUD_SPDIFIN_SEL, aud_spdifin_parents, 0x07c, 2, 2),
  1151. MUX(CLK_TOP_UART2_SEL, uart0_parents, 0x07c, 4, 1),
  1152. MUX(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents, 0x07c, 7, 3),
  1153. MUX(CLK_TOP_PNG_SYS_SEL, png_sys_parents, 0x07c, 16, 3),
  1154. MUX(CLK_TOP_SEJ_13M_SEL, sej_13m_parents, 0x07c, 22, 1),
  1155. /* CLK_MUX_SEL14 */
  1156. MUX(CLK_TOP_IMGRZ_SYS_SEL, imgrz_sys_parents, 0xc0, 0, 3),
  1157. MUX(CLK_TOP_GRAPH_ECLK_SEL, graph_eclk_parents, 0xc0, 8, 4),
  1158. MUX(CLK_TOP_FDBI_SEL, fdbi_parents, 0xc0, 12, 4),
  1159. MUX(CLK_TOP_FAUDIO_SEL, faudio_parents, 0xc0, 16, 2),
  1160. MUX(CLK_TOP_FA2SYS_SEL, fa2sys_parents, 0xc0, 24, 3),
  1161. MUX(CLK_TOP_FA1SYS_SEL, fa1sys_parents, 0xc0, 27, 3),
  1162. MUX(CLK_TOP_FASM_M_SEL, fasm_m_parents, 0xc0, 30, 2),
  1163. /* CLK_MUX_SEL15 */
  1164. MUX(CLK_TOP_FASM_H_SEL, fasm_m_parents, 0xC4, 0, 2),
  1165. MUX(CLK_TOP_FASM_L_SEL, fasm_m_parents, 0xC4, 2, 2),
  1166. MUX(CLK_TOP_FECC_CK_SEL, fecc_ck_parents, 0xC4, 18, 6),
  1167. MUX(CLK_TOP_PE2_MAC_SEL, pe2_mac_parents, 0xC4, 24, 3),
  1168. MUX(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xC4, 28, 3),
  1169. /* CLK_MUX_SEL16 */
  1170. MUX(CLK_TOP_GCPU_SEL, gcpu_parents, 0xC8, 0, 3),
  1171. MUX(CLK_TOP_SPIS_CK_SEL, spis_ck_parents, 0xC8, 4, 8),
  1172. /* CLK_MUX_SEL17 */
  1173. MUX(CLK_TOP_APLL1_REF_SEL, apll1_ref_parents, 0xCC, 6, 3),
  1174. MUX(CLK_TOP_APLL2_REF_SEL, apll1_ref_parents, 0xCC, 9, 3),
  1175. MUX(CLK_TOP_INT_32K_SEL, int_32k_parents, 0xCC, 12, 1),
  1176. MUX(CLK_TOP_APLL1_SRC_SEL, apll1_src_parents, 0xCC, 13, 2),
  1177. MUX(CLK_TOP_APLL2_SRC_SEL, apll2_src_parents, 0xCC, 15, 2),
  1178. /* CLK_MUX_SEL19 */
  1179. MUX(CLK_TOP_FAUD_INTBUS_SEL, faud_intbus_parents, 0xD4, 8, 8),
  1180. MUX(CLK_TOP_AXIBUS_SEL, axibus_parents, 0xD4, 24, 8),
  1181. /* CLK_MUX_SEL21 */
  1182. MUX(CLK_TOP_HAPLL1_SEL, hapll1_parents, 0xDC, 0, 4),
  1183. MUX(CLK_TOP_HAPLL2_SEL, hapll2_parents, 0xDC, 4, 4),
  1184. MUX(CLK_TOP_SPINFI_SEL, spinfi_parents, 0xDC, 8, 4),
  1185. /* CLK_MUX_SEL22 */
  1186. MUX(CLK_TOP_MSDC0_SEL, msdc0_parents, 0xF4, 0, 8),
  1187. MUX(CLK_TOP_MSDC0_CLK50_SEL, msdc0_clk50_parents, 0xF4, 8, 6),
  1188. MUX(CLK_TOP_MSDC2_SEL, msdc2_parents, 0xF4, 15, 8),
  1189. MUX(CLK_TOP_MSDC2_CLK50_SEL, msdc0_clk50_parents, 0xF4, 23, 6),
  1190. /* CLK_MUX_SEL23 */
  1191. MUX(CLK_TOP_DISP_DPI_CK_SEL, disp_dpi_ck_parents, 0xF8, 0, 6),
  1192. MUX(CLK_TOP_SPI1_SEL, spis_ck_parents, 0xF8, 6, 8),
  1193. MUX(CLK_TOP_SPI2_SEL, spis_ck_parents, 0xF8, 14, 8),
  1194. MUX(CLK_TOP_SPI3_SEL, spis_ck_parents, 0xF8, 22, 8),
  1195. };
  1196. static const struct mtk_gate_regs top0_cg_regs = {
  1197. .set_ofs = 0x50,
  1198. .clr_ofs = 0x80,
  1199. .sta_ofs = 0x20,
  1200. };
  1201. static const struct mtk_gate_regs top1_cg_regs = {
  1202. .set_ofs = 0x54,
  1203. .clr_ofs = 0x84,
  1204. .sta_ofs = 0x24,
  1205. };
  1206. static const struct mtk_gate_regs top2_cg_regs = {
  1207. .set_ofs = 0x6c,
  1208. .clr_ofs = 0x9c,
  1209. .sta_ofs = 0x3c,
  1210. };
  1211. static const struct mtk_gate_regs top3_cg_regs = {
  1212. .set_ofs = 0x44,
  1213. .clr_ofs = 0x44,
  1214. .sta_ofs = 0x44,
  1215. };
  1216. static const struct mtk_gate_regs top4_cg_regs = {
  1217. .set_ofs = 0xa0,
  1218. .clr_ofs = 0xb0,
  1219. .sta_ofs = 0x70,
  1220. };
  1221. static const struct mtk_gate_regs top5_cg_regs = {
  1222. .set_ofs = 0x120,
  1223. .clr_ofs = 0x140,
  1224. .sta_ofs = 0xe0,
  1225. };
  1226. static const struct mtk_gate_regs top6_cg_regs = {
  1227. .set_ofs = 0x128,
  1228. .clr_ofs = 0x148,
  1229. .sta_ofs = 0xe8,
  1230. };
  1231. static const struct mtk_gate_regs top7_cg_regs = {
  1232. .set_ofs = 0x12c,
  1233. .clr_ofs = 0x14c,
  1234. .sta_ofs = 0xec,
  1235. };
  1236. #define GATE_TOP0(_id, _parent, _shift) { \
  1237. .id = _id, \
  1238. .parent = _parent, \
  1239. .regs = &top0_cg_regs, \
  1240. .shift = _shift, \
  1241. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1242. }
  1243. #define GATE_TOP1(_id, _parent, _shift) { \
  1244. .id = _id, \
  1245. .parent = _parent, \
  1246. .regs = &top1_cg_regs, \
  1247. .shift = _shift, \
  1248. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1249. }
  1250. #define GATE_TOP2(_id, _parent, _shift) { \
  1251. .id = _id, \
  1252. .parent = _parent, \
  1253. .regs = &top2_cg_regs, \
  1254. .shift = _shift, \
  1255. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1256. }
  1257. #define GATE_TOP2_I(_id, _parent, _shift) { \
  1258. .id = _id, \
  1259. .parent = _parent, \
  1260. .regs = &top2_cg_regs, \
  1261. .shift = _shift, \
  1262. .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  1263. }
  1264. #define GATE_TOP3(_id, _parent, _shift) { \
  1265. .id = _id, \
  1266. .parent = _parent, \
  1267. .regs = &top3_cg_regs, \
  1268. .shift = _shift, \
  1269. .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
  1270. }
  1271. #define GATE_TOP4(_id, _parent, _shift) { \
  1272. .id = _id, \
  1273. .parent = _parent, \
  1274. .regs = &top4_cg_regs, \
  1275. .shift = _shift, \
  1276. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1277. }
  1278. #define GATE_TOP5(_id, _parent, _shift) { \
  1279. .id = _id, \
  1280. .parent = _parent, \
  1281. .regs = &top5_cg_regs, \
  1282. .shift = _shift, \
  1283. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1284. }
  1285. #define GATE_TOP5_I(_id, _parent, _shift) { \
  1286. .id = _id, \
  1287. .parent = _parent, \
  1288. .regs = &top5_cg_regs, \
  1289. .shift = _shift, \
  1290. .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  1291. }
  1292. #define GATE_TOP6(_id, _parent, _shift) { \
  1293. .id = _id, \
  1294. .parent = _parent, \
  1295. .regs = &top6_cg_regs, \
  1296. .shift = _shift, \
  1297. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  1298. }
  1299. #define GATE_TOP7(_id, _parent, _shift) { \
  1300. .id = _id, \
  1301. .parent = _parent, \
  1302. .regs = &top7_cg_regs, \
  1303. .shift = _shift, \
  1304. .flags = CLK_GATE_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  1305. }
  1306. static const struct mtk_gate top_clks[] = {
  1307. /* TOP0 */
  1308. GATE_TOP0(CLK_TOP_PWM_MM, CLK_TOP_PWM_MM_SEL, 0),
  1309. GATE_TOP0(CLK_TOP_SMI, CLK_TOP_SMI_SEL, 9),
  1310. GATE_TOP0(CLK_TOP_SPI2, CLK_TOP_SPI2_SEL, 10),
  1311. GATE_TOP0(CLK_TOP_SPI3, CLK_TOP_SPI3_SEL, 11),
  1312. GATE_TOP0(CLK_TOP_SPINFI, CLK_TOP_SPINFI_SEL, 12),
  1313. GATE_TOP0(CLK_TOP_26M_DEBUG, CLK_TOP_CLK26M, 16),
  1314. GATE_TOP0(CLK_TOP_USB_48M_DEBUG, CLK_TOP_USB20_48M, 17),
  1315. GATE_TOP0(CLK_TOP_52M_DEBUG, CLK_TOP_UNIVPLL_D24, 18),
  1316. GATE_TOP0(CLK_TOP_32K_DEBUG, CLK_TOP_INT_32K_SEL, 19),
  1317. /* TOP1 */
  1318. GATE_TOP1(CLK_TOP_THERM, CLK_TOP_AXIBUS_SEL, 1),
  1319. GATE_TOP1(CLK_TOP_APDMA, CLK_TOP_AXIBUS_SEL, 2),
  1320. GATE_TOP1(CLK_TOP_I2C0, CLK_TOP_AHB_INFRA_D2, 3),
  1321. GATE_TOP1(CLK_TOP_I2C1, CLK_TOP_AHB_INFRA_D2, 4),
  1322. GATE_TOP1(CLK_TOP_AUXADC1, CLK_TOP_CLK26M, 5),
  1323. GATE_TOP1(CLK_TOP_NFI, CLK_TOP_NFI1X_INFRA_BCLK, 6),
  1324. GATE_TOP1(CLK_TOP_NFIECC, CLK_TOP_AXIBUS_SEL, 7),
  1325. GATE_TOP1(CLK_TOP_DEBUGSYS, CLK_TOP_DBG_ATCLK_SEL, 8),
  1326. GATE_TOP1(CLK_TOP_PWM, CLK_TOP_AXIBUS_SEL, 9),
  1327. GATE_TOP1(CLK_TOP_UART0, CLK_TOP_UART0_SEL, 10),
  1328. GATE_TOP1(CLK_TOP_UART1, CLK_TOP_UART1_SEL, 11),
  1329. GATE_TOP1(CLK_TOP_USB, CLK_TOP_USB_B, 13),
  1330. GATE_TOP1(CLK_TOP_FLASHIF_26M, CLK_TOP_CLK26M, 14),
  1331. GATE_TOP1(CLK_TOP_AUXADC2, CLK_TOP_CLK26M, 15),
  1332. GATE_TOP1(CLK_TOP_I2C2, CLK_TOP_AHB_INFRA_D2, 16),
  1333. GATE_TOP1(CLK_TOP_MSDC0, CLK_TOP_MSDC0_SEL, 17),
  1334. GATE_TOP1(CLK_TOP_MSDC1, CLK_TOP_MSDC1_SEL, 18),
  1335. GATE_TOP1(CLK_TOP_NFI2X, CLK_TOP_NFI2X_SEL, 19),
  1336. GATE_TOP1(CLK_TOP_MEMSLP_DLYER, CLK_TOP_CLK26M, 22),
  1337. GATE_TOP1(CLK_TOP_SPI, CLK_TOP_SPI1_SEL, 23),
  1338. GATE_TOP1(CLK_TOP_APXGPT, CLK_TOP_CLK26M, 24),
  1339. GATE_TOP1(CLK_TOP_PMICWRAP_MD, CLK_TOP_CLK26M, 27),
  1340. GATE_TOP1(CLK_TOP_PMICWRAP_CONN, CLK_TOP_PMICSPI_SEL, 28),
  1341. GATE_TOP1(CLK_TOP_PMIC_SYSCK, CLK_TOP_CLK26M, 29),
  1342. GATE_TOP1(CLK_TOP_AUX_ADC, CLK_TOP_CLK26M, 30),
  1343. GATE_TOP1(CLK_TOP_AUX_TP, CLK_TOP_CLK26M, 31),
  1344. /* TOP2 */
  1345. GATE_TOP2(CLK_TOP_RBIST, CLK_TOP_UNIVPLL_D12, 1),
  1346. GATE_TOP2(CLK_TOP_NFI_BUS, CLK_TOP_AXIBUS_SEL, 2),
  1347. GATE_TOP2(CLK_TOP_GCE, CLK_TOP_AXIBUS_SEL, 4),
  1348. GATE_TOP2(CLK_TOP_TRNG, CLK_TOP_AXIBUS_SEL, 5),
  1349. GATE_TOP2(CLK_TOP_PWM_B, CLK_TOP_PWM_SEL, 8),
  1350. GATE_TOP2(CLK_TOP_PWM1_FB, CLK_TOP_PWM_SEL, 9),
  1351. GATE_TOP2(CLK_TOP_PWM2_FB, CLK_TOP_PWM_SEL, 10),
  1352. GATE_TOP2(CLK_TOP_PWM3_FB, CLK_TOP_PWM_SEL, 11),
  1353. GATE_TOP2(CLK_TOP_PWM4_FB, CLK_TOP_PWM_SEL, 12),
  1354. GATE_TOP2(CLK_TOP_PWM5_FB, CLK_TOP_PWM_SEL, 13),
  1355. GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, CLK_TOP_AXIBUS_SEL, 15),
  1356. GATE_TOP2(CLK_TOP_CQDMA, CLK_TOP_AXIBUS_SEL, 17),
  1357. GATE_TOP2(CLK_TOP_66M_ETH, CLK_TOP_AXIBUS_SEL, 19),
  1358. GATE_TOP2(CLK_TOP_133M_ETH, CLK_TOP_AXIBUS_SEL, 20),
  1359. GATE_TOP2(CLK_TOP_FLASHIF_AXI, CLK_TOP_SPI1_SEL, 23),
  1360. GATE_TOP2(CLK_TOP_USBIF, CLK_TOP_AXIBUS_SEL, 24),
  1361. GATE_TOP2(CLK_TOP_UART2, CLK_TOP_RG_UART2, 25),
  1362. GATE_TOP2(CLK_TOP_GCPU_B, CLK_TOP_AXIBUS_SEL, 27),
  1363. GATE_TOP2_I(CLK_TOP_MSDC0_B, CLK_TOP_MSDC0, 28),
  1364. GATE_TOP2_I(CLK_TOP_MSDC1_B, CLK_TOP_MSDC1, 29),
  1365. GATE_TOP2_I(CLK_TOP_MSDC2_B, CLK_TOP_MSDC2, 30),
  1366. GATE_TOP2(CLK_TOP_USB_B, CLK_TOP_USB_SEL, 31),
  1367. /* TOP3 */
  1368. GATE_TOP3(CLK_TOP_APLL12_DIV0, CLK_TOP_APLL12_CK_DIV0, 0),
  1369. GATE_TOP3(CLK_TOP_APLL12_DIV3, CLK_TOP_APLL12_CK_DIV3, 3),
  1370. GATE_TOP3(CLK_TOP_APLL12_DIV4, CLK_TOP_APLL12_CK_DIV4, 4),
  1371. GATE_TOP3(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
  1372. /* TOP4 */
  1373. GATE_TOP4(CLK_TOP_SPINOR, CLK_TOP_SPINOR_SEL, 0),
  1374. GATE_TOP4(CLK_TOP_MSDC2, CLK_TOP_MSDC2_SEL, 1),
  1375. GATE_TOP4(CLK_TOP_ETH, CLK_TOP_ETH_SEL, 2),
  1376. GATE_TOP4(CLK_TOP_AUD1, CLK_TOP_AUD1_SEL, 8),
  1377. GATE_TOP4(CLK_TOP_AUD2, CLK_TOP_AUD2_SEL, 9),
  1378. GATE_TOP4(CLK_TOP_I2C, CLK_TOP_I2C_SEL, 12),
  1379. GATE_TOP4(CLK_TOP_PWM_INFRA, CLK_TOP_PWM_SEL, 13),
  1380. GATE_TOP4(CLK_TOP_AUD_SPDIF_IN, CLK_TOP_AUD_SPDIFIN_SEL, 14),
  1381. GATE_TOP4(CLK_TOP_RG_UART2, CLK_TOP_UART2_SEL, 15),
  1382. GATE_TOP4(CLK_TOP_DBG_AT, CLK_TOP_DBG_ATCLK_SEL, 17),
  1383. /* TOP5 */
  1384. GATE_TOP5_I(CLK_TOP_IMGRZ_SYS, CLK_TOP_IMGRZ_SYS_SEL, 0),
  1385. GATE_TOP5_I(CLK_TOP_PNG_SYS, CLK_TOP_PNG_SYS_SEL, 1),
  1386. GATE_TOP5_I(CLK_TOP_GRAPH_E, CLK_TOP_GRAPH_ECLK_SEL, 2),
  1387. GATE_TOP5_I(CLK_TOP_FDBI, CLK_TOP_FDBI_SEL, 3),
  1388. GATE_TOP5_I(CLK_TOP_FAUDIO, CLK_TOP_FAUDIO_SEL, 4),
  1389. GATE_TOP5_I(CLK_TOP_FAUD_INTBUS, CLK_TOP_FAUD_INTBUS_SEL, 5),
  1390. GATE_TOP5_I(CLK_TOP_HAPLL1, CLK_TOP_HAPLL1_SEL, 6),
  1391. GATE_TOP5_I(CLK_TOP_HAPLL2, CLK_TOP_HAPLL2_SEL, 7),
  1392. GATE_TOP5_I(CLK_TOP_FA2SYS, CLK_TOP_FA2SYS_SEL, 8),
  1393. GATE_TOP5_I(CLK_TOP_FA1SYS, CLK_TOP_FA1SYS_SEL, 9),
  1394. GATE_TOP5_I(CLK_TOP_FASM_L, CLK_TOP_FASM_L_SEL, 10),
  1395. GATE_TOP5_I(CLK_TOP_FASM_M, CLK_TOP_FASM_M_SEL, 11),
  1396. GATE_TOP5_I(CLK_TOP_FASM_H, CLK_TOP_FASM_H_SEL, 12),
  1397. GATE_TOP5_I(CLK_TOP_FECC, CLK_TOP_FECC_CK_SEL, 23),
  1398. GATE_TOP5_I(CLK_TOP_PE2_MAC, CLK_TOP_PE2_MAC_SEL, 24),
  1399. GATE_TOP5_I(CLK_TOP_CMSYS, CLK_TOP_CMSYS_SEL, 25),
  1400. GATE_TOP5_I(CLK_TOP_GCPU, CLK_TOP_GCPU_SEL, 26),
  1401. GATE_TOP5(CLK_TOP_SPIS, CLK_TOP_SPIS_CK_SEL, 27),
  1402. /* TOP6 */
  1403. GATE_TOP6(CLK_TOP_I2C3, CLK_TOP_AHB_INFRA_D2, 0),
  1404. GATE_TOP6(CLK_TOP_SPI_SLV_B, CLK_TOP_SPIS_CK_SEL, 1),
  1405. GATE_TOP6(CLK_TOP_SPI_SLV_BUS, CLK_TOP_AXIBUS_SEL, 2),
  1406. GATE_TOP6(CLK_TOP_PCIE_MAC_BUS, CLK_TOP_AXIBUS_SEL, 3),
  1407. GATE_TOP6(CLK_TOP_CMSYS_BUS, CLK_TOP_AXIBUS_SEL, 4),
  1408. GATE_TOP6(CLK_TOP_ECC_B, CLK_TOP_AXIBUS_SEL, 5),
  1409. GATE_TOP6(CLK_TOP_PCIE_PHY_BUS, CLK_TOP_CLK26M, 6),
  1410. GATE_TOP6(CLK_TOP_PCIE_AUX, CLK_TOP_CLK26M, 7),
  1411. /* TOP7 */
  1412. GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
  1413. };
  1414. static const struct mtk_clk_tree mt8518_clk_tree = {
  1415. .xtal_rate = 26 * MHZ,
  1416. .xtal2_rate = 26 * MHZ,
  1417. .fdivs_offs = CLK_TOP_DMPLL,
  1418. .muxes_offs = CLK_TOP_UART0_SEL,
  1419. .plls = apmixed_plls,
  1420. .fclks = top_fixed_clks,
  1421. .fdivs = top_fixed_divs,
  1422. .muxes = top_muxes,
  1423. };
  1424. static int mt8518_apmixedsys_probe(struct udevice *dev)
  1425. {
  1426. return mtk_common_clk_init(dev, &mt8518_clk_tree);
  1427. }
  1428. static int mt8518_topckgen_probe(struct udevice *dev)
  1429. {
  1430. return mtk_common_clk_init(dev, &mt8518_clk_tree);
  1431. }
  1432. static int mt8518_topckgen_cg_probe(struct udevice *dev)
  1433. {
  1434. return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks);
  1435. }
  1436. static const struct udevice_id mt8518_apmixed_compat[] = {
  1437. { .compatible = "mediatek,mt8518-apmixedsys", },
  1438. { }
  1439. };
  1440. static const struct udevice_id mt8518_topckgen_compat[] = {
  1441. { .compatible = "mediatek,mt8518-topckgen", },
  1442. { }
  1443. };
  1444. static const struct udevice_id mt8518_topckgen_cg_compat[] = {
  1445. { .compatible = "mediatek,mt8518-topckgen-cg", },
  1446. { }
  1447. };
  1448. U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
  1449. .name = "mt8518-apmixedsys",
  1450. .id = UCLASS_CLK,
  1451. .of_match = mt8518_apmixed_compat,
  1452. .probe = mt8518_apmixedsys_probe,
  1453. .priv_auto = sizeof(struct mtk_clk_priv),
  1454. .ops = &mtk_clk_apmixedsys_ops,
  1455. .flags = DM_FLAG_PRE_RELOC,
  1456. };
  1457. U_BOOT_DRIVER(mtk_clk_topckgen) = {
  1458. .name = "mt8518-topckgen",
  1459. .id = UCLASS_CLK,
  1460. .of_match = mt8518_topckgen_compat,
  1461. .probe = mt8518_topckgen_probe,
  1462. .priv_auto = sizeof(struct mtk_clk_priv),
  1463. .ops = &mtk_clk_topckgen_ops,
  1464. .flags = DM_FLAG_PRE_RELOC,
  1465. };
  1466. U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
  1467. .name = "mt8518-topckgen-cg",
  1468. .id = UCLASS_CLK,
  1469. .of_match = mt8518_topckgen_cg_compat,
  1470. .probe = mt8518_topckgen_cg_probe,
  1471. .priv_auto = sizeof(struct mtk_cg_priv),
  1472. .ops = &mtk_clk_gate_ops,
  1473. .flags = DM_FLAG_PRE_RELOC,
  1474. };