clk-mt8512.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek clock driver for MT8512 SoC
  4. *
  5. * Copyright (C) 2019 BayLibre, SAS
  6. * Author: Chen Zhong <chen.zhong@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <asm/io.h>
  11. #include <dt-bindings/clock/mt8512-clk.h>
  12. #include <linux/bitops.h>
  13. #include "clk-mtk.h"
  14. #define MT8512_PLL_FMAX (3800UL * MHZ)
  15. #define MT8512_PLL_FMIN (1500UL * MHZ)
  16. #define MT8512_CON0_RST_BAR BIT(23)
  17. /* apmixedsys */
  18. #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  19. _pd_shift, _pcw_reg, _pcw_shift, _pcw_chg_reg) { \
  20. .id = _id, \
  21. .reg = _reg, \
  22. .pwr_reg = _pwr_reg, \
  23. .en_mask = _en_mask, \
  24. .rst_bar_mask = MT8512_CON0_RST_BAR, \
  25. .fmax = MT8512_PLL_FMAX, \
  26. .fmin = MT8512_PLL_FMIN, \
  27. .flags = _flags, \
  28. .pcwbits = _pcwbits, \
  29. .pcwibits = 8, \
  30. .pd_reg = _pd_reg, \
  31. .pd_shift = _pd_shift, \
  32. .pcw_reg = _pcw_reg, \
  33. .pcw_shift = _pcw_shift, \
  34. .pcw_chg_reg = _pcw_chg_reg, \
  35. }
  36. static const struct mtk_pll_data apmixed_plls[] = {
  37. PLL(CLK_APMIXED_ARMPLL, 0x030C, 0x0318, 0x00000001,
  38. 0, 22, 0x0310, 24, 0x0310, 0, 0),
  39. PLL(CLK_APMIXED_MAINPLL, 0x0228, 0x0234, 0x00000001,
  40. HAVE_RST_BAR, 22, 0x022C, 24, 0x022C, 0, 0),
  41. PLL(CLK_APMIXED_UNIVPLL2, 0x0208, 0x0214, 0x00000001,
  42. HAVE_RST_BAR, 22, 0x020C, 24, 0x020C, 0, 0),
  43. PLL(CLK_APMIXED_MSDCPLL, 0x0350, 0x035C, 0x00000001,
  44. 0, 22, 0x0354, 24, 0x0354, 0, 0),
  45. PLL(CLK_APMIXED_APLL1, 0x031C, 0x032C, 0x00000001,
  46. 0, 32, 0x0320, 24, 0x0324, 0, 0x0320),
  47. PLL(CLK_APMIXED_APLL2, 0x0360, 0x0370, 0x00000001,
  48. 0, 32, 0x0364, 24, 0x0368, 0, 0x0364),
  49. PLL(CLK_APMIXED_IPPLL, 0x0374, 0x0380, 0x00000001,
  50. 0, 22, 0x0378, 24, 0x0378, 0, 0),
  51. PLL(CLK_APMIXED_DSPPLL, 0x0390, 0x039C, 0x00000001,
  52. 0, 22, 0x0394, 24, 0x0394, 0, 0),
  53. PLL(CLK_APMIXED_TCONPLL, 0x03A0, 0x03AC, 0x00000001,
  54. 0, 22, 0x03A4, 24, 0x03A4, 0, 0),
  55. };
  56. /* topckgen */
  57. #define FACTOR0(_id, _parent, _mult, _div) \
  58. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  59. #define FACTOR1(_id, _parent, _mult, _div) \
  60. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  61. #define FACTOR2(_id, _parent, _mult, _div) \
  62. FACTOR(_id, _parent, _mult, _div, 0)
  63. static const struct mtk_fixed_clk top_fixed_clks[] = {
  64. FIXED_CLK(CLK_TOP_CLK_NULL, CLK_XTAL, 26000000),
  65. FIXED_CLK(CLK_TOP_CLK32K, CLK_XTAL, 32000),
  66. };
  67. static const struct mtk_fixed_factor top_fixed_divs[] = {
  68. FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
  69. FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
  70. FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
  71. FACTOR0(CLK_TOP_SYSPLL1_D16, CLK_APMIXED_MAINPLL, 1, 32),
  72. FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
  73. FACTOR0(CLK_TOP_SYSPLL2_D2, CLK_APMIXED_MAINPLL, 1, 6),
  74. FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
  75. FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
  76. FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  77. FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
  78. FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  79. FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
  80. FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL2, 1, 2),
  81. FACTOR1(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
  82. FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
  83. FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
  84. FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
  85. FACTOR1(CLK_TOP_UNIVPLL_D3, CLK_TOP_UNIVPLL, 1, 3),
  86. FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
  87. FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
  88. FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
  89. FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
  90. FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
  91. FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
  92. FACTOR0(CLK_TOP_TCONPLL_D2, CLK_APMIXED_TCONPLL, 1, 2),
  93. FACTOR0(CLK_TOP_TCONPLL_D4, CLK_APMIXED_TCONPLL, 1, 4),
  94. FACTOR0(CLK_TOP_TCONPLL_D8, CLK_APMIXED_TCONPLL, 1, 8),
  95. FACTOR0(CLK_TOP_TCONPLL_D16, CLK_APMIXED_TCONPLL, 1, 16),
  96. FACTOR0(CLK_TOP_TCONPLL_D32, CLK_APMIXED_TCONPLL, 1, 32),
  97. FACTOR0(CLK_TOP_TCONPLL_D64, CLK_APMIXED_TCONPLL, 1, 64),
  98. FACTOR1(CLK_TOP_USB20_192M, CLK_TOP_UNIVPLL, 2, 13),
  99. FACTOR1(CLK_TOP_USB20_192M_D2, CLK_TOP_USB20_192M, 1, 2),
  100. FACTOR1(CLK_TOP_USB20_192M_D4_T, CLK_TOP_USB20_192M, 1, 4),
  101. FACTOR0(CLK_TOP_APLL1, CLK_APMIXED_APLL1, 1, 1),
  102. FACTOR0(CLK_TOP_APLL1_D2, CLK_APMIXED_APLL1, 1, 2),
  103. FACTOR0(CLK_TOP_APLL1_D3, CLK_APMIXED_APLL1, 1, 3),
  104. FACTOR0(CLK_TOP_APLL1_D4, CLK_APMIXED_APLL1, 1, 4),
  105. FACTOR0(CLK_TOP_APLL1_D8, CLK_APMIXED_APLL1, 1, 8),
  106. FACTOR0(CLK_TOP_APLL1_D16, CLK_APMIXED_APLL1, 1, 16),
  107. FACTOR0(CLK_TOP_APLL2, CLK_APMIXED_APLL2, 1, 1),
  108. FACTOR0(CLK_TOP_APLL2_D2, CLK_APMIXED_APLL2, 1, 2),
  109. FACTOR0(CLK_TOP_APLL2_D3, CLK_APMIXED_APLL2, 1, 3),
  110. FACTOR0(CLK_TOP_APLL2_D4, CLK_APMIXED_APLL2, 1, 4),
  111. FACTOR0(CLK_TOP_APLL2_D8, CLK_APMIXED_APLL2, 1, 8),
  112. FACTOR0(CLK_TOP_APLL2_D16, CLK_APMIXED_APLL2, 1, 16),
  113. FACTOR2(CLK_TOP_CLK26M, CLK_XTAL, 1, 1),
  114. FACTOR2(CLK_TOP_SYS_26M_D2, CLK_XTAL, 1, 2),
  115. FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
  116. FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
  117. FACTOR0(CLK_TOP_DSPPLL, CLK_APMIXED_DSPPLL, 1, 1),
  118. FACTOR0(CLK_TOP_DSPPLL_D2, CLK_APMIXED_DSPPLL, 1, 2),
  119. FACTOR0(CLK_TOP_DSPPLL_D4, CLK_APMIXED_DSPPLL, 1, 4),
  120. FACTOR0(CLK_TOP_DSPPLL_D8, CLK_APMIXED_DSPPLL, 1, 8),
  121. FACTOR0(CLK_TOP_IPPLL, CLK_APMIXED_IPPLL, 1, 1),
  122. FACTOR0(CLK_TOP_IPPLL_D2, CLK_APMIXED_IPPLL, 1, 2),
  123. FACTOR1(CLK_TOP_NFI2X_CK_D2, CLK_TOP_NFI2X_SEL, 1, 2),
  124. };
  125. static const int axi_parents[] = {
  126. CLK_TOP_CLK26M,
  127. CLK_TOP_SYSPLL1_D4,
  128. CLK_TOP_UNIVPLL3_D2,
  129. CLK_TOP_SYSPLL1_D8,
  130. CLK_TOP_SYS_26M_D2,
  131. CLK_TOP_CLK32K
  132. };
  133. static const int mem_parents[] = {
  134. CLK_TOP_DSPPLL,
  135. CLK_TOP_IPPLL,
  136. CLK_TOP_CLK26M,
  137. CLK_TOP_UNIVPLL_D3
  138. };
  139. static const int uart_parents[] = {
  140. CLK_TOP_CLK26M,
  141. CLK_TOP_UNIVPLL2_D8
  142. };
  143. static const int spi_parents[] = {
  144. CLK_TOP_CLK26M,
  145. CLK_TOP_UNIVPLL2_D2,
  146. CLK_TOP_SYSPLL2_D2,
  147. CLK_TOP_UNIVPLL1_D4,
  148. CLK_TOP_SYSPLL1_D4,
  149. CLK_TOP_UNIVPLL3_D2,
  150. CLK_TOP_UNIVPLL2_D4,
  151. CLK_TOP_SYSPLL4_D2
  152. };
  153. static const int spis_parents[] = {
  154. CLK_TOP_CLK26M,
  155. CLK_TOP_UNIVPLL_D3,
  156. CLK_TOP_SYSPLL_D3,
  157. CLK_TOP_UNIVPLL1_D2,
  158. CLK_TOP_UNIVPLL2_D2,
  159. CLK_TOP_UNIVPLL1_D4,
  160. CLK_TOP_UNIVPLL2_D4,
  161. CLK_TOP_SYSPLL4_D2
  162. };
  163. static const int msdc50_0_hc_parents[] = {
  164. CLK_TOP_CLK26M,
  165. CLK_TOP_SYSPLL1_D2,
  166. CLK_TOP_UNIVPLL1_D4,
  167. CLK_TOP_SYSPLL2_D2
  168. };
  169. static const int msdc50_0_parents[] = {
  170. CLK_TOP_CLK26M,
  171. CLK_TOP_MSDCPLL_D2,
  172. CLK_TOP_UNIVPLL2_D2,
  173. CLK_TOP_SYSPLL2_D2,
  174. CLK_TOP_UNIVPLL1_D4,
  175. CLK_TOP_SYSPLL1_D4,
  176. CLK_TOP_SYSPLL2_D4,
  177. CLK_TOP_UNIVPLL2_D8
  178. };
  179. static const int msdc50_2_parents[] = {
  180. CLK_TOP_CLK26M,
  181. CLK_TOP_MSDCPLL,
  182. CLK_TOP_UNIVPLL_D3,
  183. CLK_TOP_UNIVPLL1_D2,
  184. CLK_TOP_SYSPLL1_D2,
  185. CLK_TOP_UNIVPLL2_D2,
  186. CLK_TOP_SYSPLL2_D2,
  187. CLK_TOP_UNIVPLL1_D4
  188. };
  189. static const int audio_parents[] = {
  190. CLK_TOP_CLK26M,
  191. CLK_TOP_UNIVPLL2_D8,
  192. CLK_TOP_APLL1_D4,
  193. CLK_TOP_APLL2_D4
  194. };
  195. static const int aud_intbus_parents[] = {
  196. CLK_TOP_CLK26M,
  197. CLK_TOP_SYSPLL1_D4,
  198. CLK_TOP_UNIVPLL3_D2,
  199. CLK_TOP_APLL2_D8,
  200. CLK_TOP_SYS_26M_D2,
  201. CLK_TOP_APLL1_D8,
  202. CLK_TOP_UNIVPLL3_D4
  203. };
  204. static const int hapll1_parents[] = {
  205. CLK_TOP_CLK26M,
  206. CLK_TOP_APLL1,
  207. CLK_TOP_APLL1_D2,
  208. CLK_TOP_APLL1_D3,
  209. CLK_TOP_APLL1_D4,
  210. CLK_TOP_APLL1_D8,
  211. CLK_TOP_APLL1_D16,
  212. CLK_TOP_SYS_26M_D2
  213. };
  214. static const int hapll2_parents[] = {
  215. CLK_TOP_CLK26M,
  216. CLK_TOP_APLL2,
  217. CLK_TOP_APLL2_D2,
  218. CLK_TOP_APLL2_D3,
  219. CLK_TOP_APLL2_D4,
  220. CLK_TOP_APLL2_D8,
  221. CLK_TOP_APLL2_D16,
  222. CLK_TOP_SYS_26M_D2
  223. };
  224. static const int asm_l_parents[] = {
  225. CLK_TOP_CLK26M,
  226. CLK_TOP_UNIVPLL2_D4,
  227. CLK_TOP_UNIVPLL2_D2,
  228. CLK_TOP_SYSPLL_D5
  229. };
  230. static const int aud_spdif_parents[] = {
  231. CLK_TOP_CLK26M,
  232. CLK_TOP_UNIVPLL_D2,
  233. CLK_TOP_DSPPLL
  234. };
  235. static const int aud_1_parents[] = {
  236. CLK_TOP_CLK26M,
  237. CLK_TOP_APLL1
  238. };
  239. static const int aud_2_parents[] = {
  240. CLK_TOP_CLK26M,
  241. CLK_TOP_APLL2
  242. };
  243. static const int ssusb_sys_parents[] = {
  244. CLK_TOP_CLK26M,
  245. CLK_TOP_UNIVPLL3_D4,
  246. CLK_TOP_UNIVPLL2_D4,
  247. CLK_TOP_UNIVPLL3_D2
  248. };
  249. static const int spm_parents[] = {
  250. CLK_TOP_CLK26M,
  251. CLK_TOP_SYSPLL1_D8
  252. };
  253. static const int i2c_parents[] = {
  254. CLK_TOP_CLK26M,
  255. CLK_TOP_SYS_26M_D2,
  256. CLK_TOP_UNIVPLL3_D4,
  257. CLK_TOP_UNIVPLL3_D2,
  258. CLK_TOP_SYSPLL1_D8,
  259. CLK_TOP_SYSPLL2_D8,
  260. CLK_TOP_CLK32K
  261. };
  262. static const int pwm_parents[] = {
  263. CLK_TOP_CLK26M,
  264. CLK_TOP_UNIVPLL3_D4,
  265. CLK_TOP_SYSPLL1_D8,
  266. CLK_TOP_UNIVPLL2_D4,
  267. CLK_TOP_SYS_26M_D2,
  268. CLK_TOP_CLK32K
  269. };
  270. static const int dsp_parents[] = {
  271. CLK_TOP_CLK26M,
  272. CLK_TOP_DSPPLL,
  273. CLK_TOP_DSPPLL_D2,
  274. CLK_TOP_DSPPLL_D4,
  275. CLK_TOP_DSPPLL_D8,
  276. CLK_TOP_APLL2_D4,
  277. CLK_TOP_SYS_26M_D2,
  278. CLK_TOP_CLK32K
  279. };
  280. static const int nfi2x_parents[] = {
  281. CLK_TOP_CLK26M,
  282. CLK_TOP_SYSPLL2_D2,
  283. CLK_TOP_SYSPLL_D7,
  284. CLK_TOP_SYSPLL_D3,
  285. CLK_TOP_SYSPLL2_D4,
  286. CLK_TOP_MSDCPLL_D2,
  287. CLK_TOP_UNIVPLL1_D2,
  288. CLK_TOP_UNIVPLL_D5
  289. };
  290. static const int spinfi_parents[] = {
  291. CLK_TOP_CLK26M,
  292. CLK_TOP_UNIVPLL2_D8,
  293. CLK_TOP_UNIVPLL3_D4,
  294. CLK_TOP_SYSPLL1_D8,
  295. CLK_TOP_SYSPLL4_D2,
  296. CLK_TOP_SYSPLL2_D4,
  297. CLK_TOP_UNIVPLL2_D4,
  298. CLK_TOP_UNIVPLL3_D2
  299. };
  300. static const int ecc_parents[] = {
  301. CLK_TOP_CLK26M,
  302. CLK_TOP_SYSPLL_D5,
  303. CLK_TOP_SYSPLL_D3,
  304. CLK_TOP_UNIVPLL_D3
  305. };
  306. static const int gcpu_parents[] = {
  307. CLK_TOP_CLK26M,
  308. CLK_TOP_UNIVPLL_D3,
  309. CLK_TOP_SYSPLL_D3,
  310. CLK_TOP_UNIVPLL1_D2,
  311. CLK_TOP_SYSPLL1_D2,
  312. CLK_TOP_UNIVPLL2_D2
  313. };
  314. static const int gcpu_cpm_parents[] = {
  315. CLK_TOP_CLK26M,
  316. CLK_TOP_UNIVPLL2_D2,
  317. CLK_TOP_SYSPLL2_D2,
  318. CLK_TOP_UNIVPLL1_D4
  319. };
  320. static const int mbist_diag_parents[] = {
  321. CLK_TOP_CLK26M,
  322. CLK_TOP_SYS_26M_D2
  323. };
  324. static const int ip0_nna_parents[] = {
  325. CLK_TOP_CLK26M,
  326. CLK_TOP_DSPPLL,
  327. CLK_TOP_DSPPLL_D2,
  328. CLK_TOP_DSPPLL_D4,
  329. CLK_TOP_IPPLL,
  330. CLK_TOP_SYS_26M_D2,
  331. CLK_TOP_IPPLL_D2,
  332. CLK_TOP_MSDCPLL_D2
  333. };
  334. static const int ip2_wfst_parents[] = {
  335. CLK_TOP_CLK26M,
  336. CLK_TOP_UNIVPLL_D3,
  337. CLK_TOP_UNIVPLL1_D2,
  338. CLK_TOP_UNIVPLL2_D2,
  339. CLK_TOP_IPPLL,
  340. CLK_TOP_IPPLL_D2,
  341. CLK_TOP_SYS_26M_D2,
  342. CLK_TOP_MSDCPLL
  343. };
  344. static const int sflash_parents[] = {
  345. CLK_TOP_CLK26M,
  346. CLK_TOP_SYSPLL1_D16,
  347. CLK_TOP_SYSPLL2_D8,
  348. CLK_TOP_SYSPLL3_D4,
  349. CLK_TOP_UNIVPLL3_D4,
  350. CLK_TOP_UNIVPLL1_D8,
  351. CLK_TOP_USB20_192M_D2,
  352. CLK_TOP_UNIVPLL2_D4
  353. };
  354. static const int sram_parents[] = {
  355. CLK_TOP_CLK26M,
  356. CLK_TOP_DSPPLL,
  357. CLK_TOP_UNIVPLL_D3,
  358. CLK_TOP_SYSPLL1_D2,
  359. CLK_TOP_APLL1,
  360. CLK_TOP_APLL2,
  361. CLK_TOP_SYSPLL1_D4,
  362. CLK_TOP_SYS_26M_D2
  363. };
  364. static const int mm_parents[] = {
  365. CLK_TOP_CLK26M,
  366. CLK_TOP_SYSPLL_D3,
  367. CLK_TOP_SYSPLL1_D2,
  368. CLK_TOP_SYSPLL_D5,
  369. CLK_TOP_SYSPLL1_D4,
  370. CLK_TOP_UNIVPLL_D5,
  371. CLK_TOP_UNIVPLL1_D2,
  372. CLK_TOP_UNIVPLL_D3
  373. };
  374. static const int dpi0_parents[] = {
  375. CLK_TOP_CLK26M,
  376. CLK_TOP_TCONPLL_D2,
  377. CLK_TOP_TCONPLL_D4,
  378. CLK_TOP_TCONPLL_D8,
  379. CLK_TOP_TCONPLL_D16,
  380. CLK_TOP_TCONPLL_D32,
  381. CLK_TOP_TCONPLL_D64
  382. };
  383. static const int dbg_atclk_parents[] = {
  384. CLK_TOP_CLK26M,
  385. CLK_TOP_UNIVPLL1_D2,
  386. CLK_TOP_UNIVPLL_D5
  387. };
  388. static const int occ_104m_parents[] = {
  389. CLK_TOP_UNIVPLL2_D4,
  390. CLK_TOP_UNIVPLL2_D8
  391. };
  392. static const int occ_68m_parents[] = {
  393. CLK_TOP_SYSPLL1_D8,
  394. CLK_TOP_UNIVPLL2_D8
  395. };
  396. static const int occ_182m_parents[] = {
  397. CLK_TOP_SYSPLL2_D2,
  398. CLK_TOP_UNIVPLL1_D4,
  399. CLK_TOP_UNIVPLL2_D8
  400. };
  401. static const struct mtk_composite top_muxes[] = {
  402. /* CLK_CFG_0 */
  403. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, axi_parents,
  404. 0x040, 0x044, 0x048, 0, 3, 7,
  405. 0x4, 0, CLK_MUX_SETCLR_UPD),
  406. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, mem_parents,
  407. 0x040, 0x044, 0x048, 8, 2, 15,
  408. 0x4, 1, CLK_MUX_SETCLR_UPD),
  409. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_UART_SEL, uart_parents,
  410. 0x040, 0x044, 0x048, 16, 1, 23,
  411. 0x4, 2, CLK_MUX_SETCLR_UPD),
  412. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPI_SEL, spi_parents,
  413. 0x040, 0x044, 0x048, 24, 3, 31,
  414. 0x4, 3, CLK_MUX_SETCLR_UPD),
  415. /* CLK_CFG_1 */
  416. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPIS_SEL, spis_parents,
  417. 0x050, 0x054, 0x058, 0, 3, 7,
  418. 0x4, 4, CLK_MUX_SETCLR_UPD),
  419. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_HC_SEL, msdc50_0_hc_parents,
  420. 0x050, 0x054, 0x058, 8, 2, 15,
  421. 0x4, 5, CLK_MUX_SETCLR_UPD),
  422. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC2_2_HC_SEL, msdc50_0_hc_parents,
  423. 0x050, 0x054, 0x058, 16, 2, 23,
  424. 0x4, 6, CLK_MUX_SETCLR_UPD),
  425. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_0_SEL, msdc50_0_parents,
  426. 0x050, 0x054, 0x058, 24, 3, 31,
  427. 0x4, 7, CLK_MUX_SETCLR_UPD),
  428. /* CLK_CFG_2 */
  429. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC50_2_SEL, msdc50_2_parents,
  430. 0x060, 0x064, 0x068, 0, 3, 7,
  431. 0x4, 8, CLK_MUX_SETCLR_UPD),
  432. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MSDC30_1_SEL, msdc50_0_parents,
  433. 0x060, 0x064, 0x068, 8, 3, 15,
  434. 0x4, 9, CLK_MUX_SETCLR_UPD),
  435. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUDIO_SEL, audio_parents,
  436. 0x060, 0x064, 0x068, 16, 2, 23,
  437. 0x4, 10, CLK_MUX_SETCLR_UPD),
  438. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents,
  439. 0x060, 0x064, 0x068, 24, 3, 31,
  440. 0x4, 11, CLK_MUX_SETCLR_UPD),
  441. /* CLK_CFG_3 */
  442. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL1_SEL, hapll1_parents,
  443. 0x070, 0x074, 0x078, 0, 3, 7,
  444. 0x4, 12, CLK_MUX_SETCLR_UPD),
  445. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_HAPLL2_SEL, hapll2_parents,
  446. 0x070, 0x074, 0x078, 8, 3, 15,
  447. 0x4, 13, CLK_MUX_SETCLR_UPD),
  448. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A2SYS_SEL, hapll1_parents,
  449. 0x070, 0x074, 0x078, 16, 3, 23,
  450. 0x4, 14, CLK_MUX_SETCLR_UPD),
  451. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_A1SYS_SEL, hapll2_parents,
  452. 0x070, 0x074, 0x078, 24, 3, 31,
  453. 0x4, 15, CLK_MUX_SETCLR_UPD),
  454. /* CLK_CFG_4 */
  455. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_L_SEL, asm_l_parents,
  456. 0x080, 0x084, 0x088, 0, 2, 7,
  457. 0x4, 16, CLK_MUX_SETCLR_UPD),
  458. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_M_SEL, asm_l_parents,
  459. 0x080, 0x084, 0x088, 8, 2, 15,
  460. 0x4, 17, CLK_MUX_SETCLR_UPD),
  461. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ASM_H_SEL, asm_l_parents,
  462. 0x080, 0x084, 0x088, 16, 2, 23,
  463. 0x4, 18, CLK_MUX_SETCLR_UPD),
  464. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_SPDIF_SEL, aud_spdif_parents,
  465. 0x080, 0x084, 0x088, 24, 2, 31,
  466. 0x4, 19, CLK_MUX_SETCLR_UPD),
  467. /* CLK_CFG_5 */
  468. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_1_SEL, aud_1_parents,
  469. 0x090, 0x094, 0x098, 0, 1, 7,
  470. 0x4, 20, CLK_MUX_SETCLR_UPD),
  471. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_AUD_2_SEL, aud_2_parents,
  472. 0x090, 0x094, 0x098, 8, 1, 15,
  473. 0x4, 21, CLK_MUX_SETCLR_UPD),
  474. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_SYS_SEL, ssusb_sys_parents,
  475. 0x090, 0x094, 0x098, 16, 2, 23,
  476. 0x4, 22, CLK_MUX_SETCLR_UPD),
  477. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SSUSB_XHCI_SEL, ssusb_sys_parents,
  478. 0x090, 0x094, 0x098, 24, 2, 31,
  479. 0x4, 23, CLK_MUX_SETCLR_UPD),
  480. /* CLK_CFG_6 */
  481. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPM_SEL, spm_parents,
  482. 0x0a0, 0x0a4, 0x0a8, 0, 1, 7,
  483. 0x4, 24, CLK_MUX_SETCLR_UPD),
  484. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_I2C_SEL, i2c_parents,
  485. 0x0a0, 0x0a4, 0x0a8, 8, 3, 15,
  486. 0x4, 25, CLK_MUX_SETCLR_UPD),
  487. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_PWM_SEL, pwm_parents,
  488. 0x0a0, 0x0a4, 0x0a8, 16, 3, 23,
  489. 0x4, 26, CLK_MUX_SETCLR_UPD),
  490. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DSP_SEL, dsp_parents,
  491. 0x0a0, 0x0a4, 0x0a8, 24, 3, 31,
  492. 0x4, 27, CLK_MUX_SETCLR_UPD),
  493. /* CLK_CFG_7 */
  494. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_NFI2X_SEL, nfi2x_parents,
  495. 0x0b0, 0x0b4, 0x0b8, 0, 3, 7,
  496. 0x4, 28, CLK_MUX_SETCLR_UPD),
  497. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SPINFI_SEL, spinfi_parents,
  498. 0x0b0, 0x0b4, 0x0b8, 8, 3, 15,
  499. 0x4, 29, CLK_MUX_SETCLR_UPD),
  500. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_ECC_SEL, ecc_parents,
  501. 0x0b0, 0x0b4, 0x0b8, 16, 2, 23,
  502. 0x4, 30, CLK_MUX_SETCLR_UPD),
  503. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_SEL, gcpu_parents,
  504. 0x0b0, 0x0b4, 0x0b8, 24, 3, 31,
  505. 0x4, 31, CLK_MUX_SETCLR_UPD),
  506. /* CLK_CFG_8 */
  507. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_GCPU_CPM_SEL, gcpu_cpm_parents,
  508. 0x0c0, 0x0c4, 0x0c8, 0, 2, 7,
  509. 0x8, 0, CLK_MUX_SETCLR_UPD),
  510. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MBIST_DIAG_SEL, mbist_diag_parents,
  511. 0x0c0, 0x0c4, 0x0c8, 8, 1, 15,
  512. 0x8, 1, CLK_MUX_SETCLR_UPD),
  513. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP0_NNA_SEL, ip0_nna_parents,
  514. 0x0c0, 0x0c4, 0x0c8, 16, 3, 23,
  515. 0x8, 2, CLK_MUX_SETCLR_UPD),
  516. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP1_NNA_SEL, ip0_nna_parents,
  517. 0x0c0, 0x0c4, 0x0c8, 24, 3, 31,
  518. 0x8, 3, CLK_MUX_SETCLR_UPD),
  519. /* CLK_CFG_9 */
  520. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_IP2_WFST_SEL, ip2_wfst_parents,
  521. 0x0d0, 0x0d4, 0x0d8, 0, 3, 7,
  522. 0x8, 4, CLK_MUX_SETCLR_UPD),
  523. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SFLASH_SEL, sflash_parents,
  524. 0x0d0, 0x0d4, 0x0d8, 8, 3, 15,
  525. 0x8, 5, CLK_MUX_SETCLR_UPD),
  526. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_SRAM_SEL, sram_parents,
  527. 0x0d0, 0x0d4, 0x0d8, 16, 3, 23,
  528. 0x8, 6, CLK_MUX_SETCLR_UPD),
  529. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_MM_SEL, mm_parents,
  530. 0x0d0, 0x0d4, 0x0d8, 24, 3, 31,
  531. 0x8, 7, CLK_MUX_SETCLR_UPD),
  532. /* CLK_CFG_10 */
  533. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DPI0_SEL, dpi0_parents,
  534. 0x0e0, 0x0e4, 0x0e8, 0, 3, 7,
  535. 0x8, 8, CLK_MUX_SETCLR_UPD),
  536. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_DBG_ATCLK_SEL, dbg_atclk_parents,
  537. 0x0e0, 0x0e4, 0x0e8, 8, 2, 15,
  538. 0x8, 9, CLK_MUX_SETCLR_UPD),
  539. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_104M_SEL, occ_104m_parents,
  540. 0x0e0, 0x0e4, 0x0e8, 16, 1, 23,
  541. 0x8, 10, CLK_MUX_SETCLR_UPD),
  542. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_68M_SEL, occ_68m_parents,
  543. 0x0e0, 0x0e4, 0x0e8, 24, 1, 31,
  544. 0x8, 11, CLK_MUX_SETCLR_UPD),
  545. /* CLK_CFG_11 */
  546. MUX_CLR_SET_UPD_FLAGS(CLK_TOP_OCC_182M_SEL, occ_182m_parents,
  547. 0x0ec, 0x0f0, 0x0f4, 0, 2, 7,
  548. 0x8, 12, CLK_MUX_SETCLR_UPD),
  549. };
  550. static const struct mtk_gate_regs top0_cg_regs = {
  551. .set_ofs = 0x0,
  552. .clr_ofs = 0x0,
  553. .sta_ofs = 0x0,
  554. };
  555. static const struct mtk_gate_regs top1_cg_regs = {
  556. .set_ofs = 0x104,
  557. .clr_ofs = 0x104,
  558. .sta_ofs = 0x104,
  559. };
  560. #define GATE_TOP0(_id, _parent, _shift) { \
  561. .id = _id, \
  562. .parent = _parent, \
  563. .regs = &top0_cg_regs, \
  564. .shift = _shift, \
  565. .flags = CLK_GATE_NO_SETCLR | CLK_PARENT_TOPCKGEN, \
  566. }
  567. #define GATE_TOP1(_id, _parent, _shift) { \
  568. .id = _id, \
  569. .parent = _parent, \
  570. .regs = &top1_cg_regs, \
  571. .shift = _shift, \
  572. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  573. }
  574. static const struct mtk_gate top_clks[] = {
  575. /* TOP0 */
  576. GATE_TOP0(CLK_TOP_CONN_32K, CLK_TOP_CLK32K, 10),
  577. GATE_TOP0(CLK_TOP_CONN_26M, CLK_TOP_CLK26M, 11),
  578. GATE_TOP0(CLK_TOP_DSP_32K, CLK_TOP_CLK32K, 16),
  579. GATE_TOP0(CLK_TOP_DSP_26M, CLK_TOP_CLK26M, 17),
  580. /* TOP1 */
  581. GATE_TOP1(CLK_TOP_USB20_48M_EN, CLK_TOP_USB20_192M_D4_T, 8),
  582. GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, CLK_TOP_USB20_192M_D4_T, 9),
  583. GATE_TOP1(CLK_TOP_SSUSB_TOP_CK_EN, CLK_TOP_CLK_NULL, 22),
  584. GATE_TOP1(CLK_TOP_SSUSB_PHY_CK_EN, CLK_TOP_CLK_NULL, 23),
  585. };
  586. static const struct mtk_gate_regs infra0_cg_regs = {
  587. .set_ofs = 0x294,
  588. .clr_ofs = 0x294,
  589. .sta_ofs = 0x294,
  590. };
  591. static const struct mtk_gate_regs infra1_cg_regs = {
  592. .set_ofs = 0x80,
  593. .clr_ofs = 0x84,
  594. .sta_ofs = 0x90,
  595. };
  596. static const struct mtk_gate_regs infra2_cg_regs = {
  597. .set_ofs = 0x88,
  598. .clr_ofs = 0x8c,
  599. .sta_ofs = 0x94,
  600. };
  601. static const struct mtk_gate_regs infra3_cg_regs = {
  602. .set_ofs = 0xa4,
  603. .clr_ofs = 0xa8,
  604. .sta_ofs = 0xac,
  605. };
  606. static const struct mtk_gate_regs infra4_cg_regs = {
  607. .set_ofs = 0xc0,
  608. .clr_ofs = 0xc4,
  609. .sta_ofs = 0xc8,
  610. };
  611. static const struct mtk_gate_regs infra5_cg_regs = {
  612. .set_ofs = 0xd0,
  613. .clr_ofs = 0xd4,
  614. .sta_ofs = 0xd8,
  615. };
  616. #define GATE_INFRA0(_id, _parent, _shift) { \
  617. .id = _id, \
  618. .parent = _parent, \
  619. .regs = &infra0_cg_regs, \
  620. .shift = _shift, \
  621. .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
  622. }
  623. #define GATE_INFRA1(_id, _parent, _shift) { \
  624. .id = _id, \
  625. .parent = _parent, \
  626. .regs = &infra1_cg_regs, \
  627. .shift = _shift, \
  628. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  629. }
  630. #define GATE_INFRA2(_id, _parent, _shift) { \
  631. .id = _id, \
  632. .parent = _parent, \
  633. .regs = &infra2_cg_regs, \
  634. .shift = _shift, \
  635. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  636. }
  637. #define GATE_INFRA3(_id, _parent, _shift) { \
  638. .id = _id, \
  639. .parent = _parent, \
  640. .regs = &infra3_cg_regs, \
  641. .shift = _shift, \
  642. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  643. }
  644. #define GATE_INFRA4(_id, _parent, _shift) { \
  645. .id = _id, \
  646. .parent = _parent, \
  647. .regs = &infra4_cg_regs, \
  648. .shift = _shift, \
  649. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  650. }
  651. #define GATE_INFRA5(_id, _parent, _shift) { \
  652. .id = _id, \
  653. .parent = _parent, \
  654. .regs = &infra5_cg_regs, \
  655. .shift = _shift, \
  656. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  657. }
  658. static const struct mtk_gate infra_clks[] = {
  659. /* INFRA0 */
  660. GATE_INFRA0(CLK_INFRA_DSP_AXI, CLK_TOP_AXI_SEL, 8),
  661. /* INFRA1 */
  662. GATE_INFRA1(CLK_INFRA_APXGPT, CLK_TOP_AXI_SEL, 6),
  663. GATE_INFRA1(CLK_INFRA_ICUSB, CLK_TOP_AXI_SEL, 8),
  664. GATE_INFRA1(CLK_INFRA_GCE, CLK_TOP_AXI_SEL, 9),
  665. GATE_INFRA1(CLK_INFRA_THERM, CLK_TOP_AXI_SEL, 10),
  666. GATE_INFRA1(CLK_INFRA_PWM_HCLK, CLK_TOP_AXI_SEL, 15),
  667. GATE_INFRA1(CLK_INFRA_PWM1, CLK_TOP_PWM_SEL, 16),
  668. GATE_INFRA1(CLK_INFRA_PWM2, CLK_TOP_PWM_SEL, 17),
  669. GATE_INFRA1(CLK_INFRA_PWM3, CLK_TOP_PWM_SEL, 18),
  670. GATE_INFRA1(CLK_INFRA_PWM4, CLK_TOP_PWM_SEL, 19),
  671. GATE_INFRA1(CLK_INFRA_PWM5, CLK_TOP_PWM_SEL, 20),
  672. GATE_INFRA1(CLK_INFRA_PWM, CLK_TOP_PWM_SEL, 21),
  673. GATE_INFRA1(CLK_INFRA_UART0, CLK_TOP_UART_SEL, 22),
  674. GATE_INFRA1(CLK_INFRA_UART1, CLK_TOP_UART_SEL, 23),
  675. GATE_INFRA1(CLK_INFRA_UART2, CLK_TOP_UART_SEL, 24),
  676. GATE_INFRA1(CLK_INFRA_DSP_UART, CLK_TOP_UART_SEL, 26),
  677. GATE_INFRA1(CLK_INFRA_GCE_26M, CLK_TOP_CLK26M, 27),
  678. GATE_INFRA1(CLK_INFRA_CQDMA_FPC, CLK_TOP_AXI_SEL, 28),
  679. GATE_INFRA1(CLK_INFRA_BTIF, CLK_TOP_AXI_SEL, 31),
  680. /* INFRA2 */
  681. GATE_INFRA2(CLK_INFRA_SPI, CLK_TOP_SPI_SEL, 1),
  682. GATE_INFRA2(CLK_INFRA_MSDC0, CLK_TOP_MSDC50_0_HC_SEL, 2),
  683. GATE_INFRA2(CLK_INFRA_MSDC1, CLK_TOP_AXI_SEL, 4),
  684. GATE_INFRA2(CLK_INFRA_DVFSRC, CLK_TOP_CLK26M, 7),
  685. GATE_INFRA2(CLK_INFRA_GCPU, CLK_TOP_AXI_SEL, 8),
  686. GATE_INFRA2(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 9),
  687. GATE_INFRA2(CLK_INFRA_AUXADC, CLK_TOP_CLK26M, 10),
  688. GATE_INFRA2(CLK_INFRA_AUXADC_MD, CLK_TOP_CLK26M, 14),
  689. GATE_INFRA2(CLK_INFRA_AP_DMA, CLK_TOP_AXI_SEL, 18),
  690. GATE_INFRA2(CLK_INFRA_DEBUGSYS, CLK_TOP_AXI_SEL, 24),
  691. GATE_INFRA2(CLK_INFRA_AUDIO, CLK_TOP_AXI_SEL, 25),
  692. GATE_INFRA2(CLK_INFRA_FLASHIF, CLK_TOP_SFLASH_SEL, 29),
  693. /* INFRA3 */
  694. GATE_INFRA3(CLK_INFRA_PWM_FB6, CLK_TOP_PWM_SEL, 0),
  695. GATE_INFRA3(CLK_INFRA_PWM_FB7, CLK_TOP_PWM_SEL, 1),
  696. GATE_INFRA3(CLK_INFRA_AUD_ASRC, CLK_TOP_AXI_SEL, 3),
  697. GATE_INFRA3(CLK_INFRA_AUD_26M, CLK_TOP_CLK26M, 4),
  698. GATE_INFRA3(CLK_INFRA_SPIS, CLK_TOP_AXI_SEL, 6),
  699. GATE_INFRA3(CLK_INFRA_CQ_DMA, CLK_TOP_AXI_SEL, 27),
  700. /* INFRA4 */
  701. GATE_INFRA4(CLK_INFRA_AP_MSDC0, CLK_TOP_MSDC50_0_SEL, 7),
  702. GATE_INFRA4(CLK_INFRA_MD_MSDC0, CLK_TOP_MSDC50_0_SEL, 8),
  703. GATE_INFRA4(CLK_INFRA_MSDC0_SRC, CLK_TOP_MSDC50_0_SEL, 9),
  704. GATE_INFRA4(CLK_INFRA_MSDC1_SRC, CLK_TOP_MSDC30_1_SEL, 10),
  705. GATE_INFRA4(CLK_INFRA_IRRX_26M, CLK_TOP_AXI_SEL, 22),
  706. GATE_INFRA4(CLK_INFRA_IRRX_32K, CLK_TOP_CLK32K, 23),
  707. GATE_INFRA4(CLK_INFRA_I2C0_AXI, CLK_TOP_I2C_SEL, 24),
  708. GATE_INFRA4(CLK_INFRA_I2C1_AXI, CLK_TOP_I2C_SEL, 25),
  709. GATE_INFRA4(CLK_INFRA_I2C2_AXI, CLK_TOP_I2C_SEL, 26),
  710. /* INFRA5 */
  711. GATE_INFRA5(CLK_INFRA_NFI, CLK_TOP_NFI2X_CK_D2, 1),
  712. GATE_INFRA5(CLK_INFRA_NFIECC, CLK_TOP_NFI2X_CK_D2, 2),
  713. GATE_INFRA5(CLK_INFRA_NFI_HCLK, CLK_TOP_AXI_SEL, 3),
  714. GATE_INFRA5(CLK_INFRA_SUSB_133, CLK_TOP_AXI_SEL, 7),
  715. GATE_INFRA5(CLK_INFRA_USB_SYS, CLK_TOP_SSUSB_SYS_SEL, 9),
  716. GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
  717. };
  718. static const struct mtk_clk_tree mt8512_clk_tree = {
  719. .xtal_rate = 26 * MHZ,
  720. .xtal2_rate = 26 * MHZ,
  721. .fdivs_offs = CLK_TOP_SYSPLL1_D2,
  722. .muxes_offs = CLK_TOP_AXI_SEL,
  723. .plls = apmixed_plls,
  724. .fclks = top_fixed_clks,
  725. .fdivs = top_fixed_divs,
  726. .muxes = top_muxes,
  727. };
  728. static int mt8512_apmixedsys_probe(struct udevice *dev)
  729. {
  730. return mtk_common_clk_init(dev, &mt8512_clk_tree);
  731. }
  732. static int mt8512_topckgen_probe(struct udevice *dev)
  733. {
  734. return mtk_common_clk_init(dev, &mt8512_clk_tree);
  735. }
  736. static int mt8512_topckgen_cg_probe(struct udevice *dev)
  737. {
  738. return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks);
  739. }
  740. static int mt8512_infracfg_probe(struct udevice *dev)
  741. {
  742. return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks);
  743. }
  744. static const struct udevice_id mt8512_apmixed_compat[] = {
  745. { .compatible = "mediatek,mt8512-apmixedsys", },
  746. { }
  747. };
  748. static const struct udevice_id mt8512_topckgen_compat[] = {
  749. { .compatible = "mediatek,mt8512-topckgen", },
  750. { }
  751. };
  752. static const struct udevice_id mt8512_topckgen_cg_compat[] = {
  753. { .compatible = "mediatek,mt8512-topckgen-cg", },
  754. { }
  755. };
  756. static const struct udevice_id mt8512_infracfg_compat[] = {
  757. { .compatible = "mediatek,mt8512-infracfg", },
  758. { }
  759. };
  760. U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
  761. .name = "mt8512-apmixedsys",
  762. .id = UCLASS_CLK,
  763. .of_match = mt8512_apmixed_compat,
  764. .probe = mt8512_apmixedsys_probe,
  765. .priv_auto = sizeof(struct mtk_clk_priv),
  766. .ops = &mtk_clk_apmixedsys_ops,
  767. .flags = DM_FLAG_PRE_RELOC,
  768. };
  769. U_BOOT_DRIVER(mtk_clk_topckgen) = {
  770. .name = "mt8512-topckgen",
  771. .id = UCLASS_CLK,
  772. .of_match = mt8512_topckgen_compat,
  773. .probe = mt8512_topckgen_probe,
  774. .priv_auto = sizeof(struct mtk_clk_priv),
  775. .ops = &mtk_clk_topckgen_ops,
  776. .flags = DM_FLAG_PRE_RELOC,
  777. };
  778. U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
  779. .name = "mt8512-topckgen-cg",
  780. .id = UCLASS_CLK,
  781. .of_match = mt8512_topckgen_cg_compat,
  782. .probe = mt8512_topckgen_cg_probe,
  783. .priv_auto = sizeof(struct mtk_cg_priv),
  784. .ops = &mtk_clk_gate_ops,
  785. .flags = DM_FLAG_PRE_RELOC,
  786. };
  787. U_BOOT_DRIVER(mtk_clk_infracfg) = {
  788. .name = "mt8512-infracfg",
  789. .id = UCLASS_CLK,
  790. .of_match = mt8512_infracfg_compat,
  791. .probe = mt8512_infracfg_probe,
  792. .priv_auto = sizeof(struct mtk_cg_priv),
  793. .ops = &mtk_clk_gate_ops,
  794. .flags = DM_FLAG_PRE_RELOC,
  795. };