clk-mt7623.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * MediaTek clock driver for MT7623 SoC
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <asm/arch-mediatek/reset.h>
  12. #include <asm/io.h>
  13. #include <dt-bindings/clock/mt7623-clk.h>
  14. #include <linux/bitops.h>
  15. #include "clk-mtk.h"
  16. #define MT7623_CLKSQ_STB_CON0 0x18
  17. #define MT7623_PLL_ISO_CON0 0x24
  18. #define MT7623_PLL_FMAX (2000UL * MHZ)
  19. #define MT7623_CON0_RST_BAR BIT(27)
  20. #define MCU_AXI_DIV 0x60
  21. #define AXI_DIV_MSK GENMASK(4, 0)
  22. #define AXI_DIV_SEL(x) (x)
  23. /* apmixedsys */
  24. #define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
  25. _pd_shift, _pcw_reg, _pcw_shift) { \
  26. .id = _id, \
  27. .reg = _reg, \
  28. .pwr_reg = _pwr_reg, \
  29. .en_mask = _en_mask, \
  30. .rst_bar_mask = MT7623_CON0_RST_BAR, \
  31. .fmax = MT7623_PLL_FMAX, \
  32. .flags = _flags, \
  33. .pcwbits = _pcwbits, \
  34. .pd_reg = _pd_reg, \
  35. .pd_shift = _pd_shift, \
  36. .pcw_reg = _pcw_reg, \
  37. .pcw_shift = _pcw_shift, \
  38. }
  39. static const struct mtk_pll_data apmixed_plls[] = {
  40. PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x80000001, 0,
  41. 21, 0x204, 24, 0x204, 0),
  42. PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0xf0000001, HAVE_RST_BAR,
  43. 21, 0x210, 4, 0x214, 0),
  44. PLL(CLK_APMIXED_UNIVPLL, 0x220, 0x22c, 0xf3000001, HAVE_RST_BAR,
  45. 7, 0x220, 4, 0x224, 14),
  46. PLL(CLK_APMIXED_MMPLL, 0x230, 0x23c, 0x00000001, 0,
  47. 21, 0x230, 4, 0x234, 0),
  48. PLL(CLK_APMIXED_MSDCPLL, 0x240, 0x24c, 0x00000001, 0,
  49. 21, 0x240, 4, 0x244, 0),
  50. PLL(CLK_APMIXED_TVDPLL, 0x250, 0x25c, 0x00000001, 0,
  51. 21, 0x250, 4, 0x254, 0),
  52. PLL(CLK_APMIXED_AUD1PLL, 0x270, 0x27c, 0x00000001, 0,
  53. 31, 0x270, 4, 0x274, 0),
  54. PLL(CLK_APMIXED_TRGPLL, 0x280, 0x28c, 0x00000001, 0,
  55. 31, 0x280, 4, 0x284, 0),
  56. PLL(CLK_APMIXED_ETHPLL, 0x290, 0x29c, 0x00000001, 0,
  57. 31, 0x290, 4, 0x294, 0),
  58. PLL(CLK_APMIXED_VDECPLL, 0x2a0, 0x2ac, 0x00000001, 0,
  59. 31, 0x2a0, 4, 0x2a4, 0),
  60. PLL(CLK_APMIXED_HADDS2PLL, 0x2b0, 0x2bc, 0x00000001, 0,
  61. 31, 0x2b0, 4, 0x2b4, 0),
  62. PLL(CLK_APMIXED_AUD2PLL, 0x2c0, 0x2cc, 0x00000001, 0,
  63. 31, 0x2c0, 4, 0x2c4, 0),
  64. PLL(CLK_APMIXED_TVD2PLL, 0x2d0, 0x2dc, 0x00000001, 0,
  65. 21, 0x2d0, 4, 0x2d4, 0),
  66. };
  67. /* topckgen */
  68. #define FACTOR0(_id, _parent, _mult, _div) \
  69. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
  70. #define FACTOR1(_id, _parent, _mult, _div) \
  71. FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
  72. #define FACTOR2(_id, _parent, _mult, _div) \
  73. FACTOR(_id, _parent, _mult, _div, 0)
  74. static const struct mtk_fixed_clk top_fixed_clks[] = {
  75. FIXED_CLK(CLK_TOP_DPI, CLK_XTAL, 108 * MHZ),
  76. FIXED_CLK(CLK_TOP_DMPLL, CLK_XTAL, 400 * MHZ),
  77. FIXED_CLK(CLK_TOP_VENCPLL, CLK_XTAL, 295.75 * MHZ),
  78. FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, CLK_XTAL, 340 * MHZ),
  79. FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, CLK_XTAL, 340 * MHZ),
  80. FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, CLK_XTAL, 340 * MHZ),
  81. FIXED_CLK(CLK_TOP_HADDS2_FB, CLK_XTAL, 27 * MHZ),
  82. FIXED_CLK(CLK_TOP_WBG_DIG_416M, CLK_XTAL, 416 * MHZ),
  83. FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, CLK_XTAL, 143 * MHZ),
  84. FIXED_CLK(CLK_TOP_HDMI_SCL_RX, CLK_XTAL, 27 * MHZ),
  85. FIXED_CLK(CLK_TOP_32K_EXTERNAL, CLK_XTAL, 32000),
  86. FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, CLK_XTAL, 300 * MHZ),
  87. FIXED_CLK(CLK_TOP_AUD_EXT1, CLK_XTAL, 0),
  88. FIXED_CLK(CLK_TOP_AUD_EXT2, CLK_XTAL, 0),
  89. FIXED_CLK(CLK_TOP_NFI1X_PAD, CLK_XTAL, 0),
  90. };
  91. static const struct mtk_fixed_factor top_fixed_divs[] = {
  92. FACTOR0(CLK_TOP_SYSPLL, CLK_APMIXED_MAINPLL, 1, 1),
  93. FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
  94. FACTOR0(CLK_TOP_SYSPLL_D3, CLK_APMIXED_MAINPLL, 1, 3),
  95. FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
  96. FACTOR0(CLK_TOP_SYSPLL_D7, CLK_APMIXED_MAINPLL, 1, 7),
  97. FACTOR1(CLK_TOP_SYSPLL1_D2, CLK_TOP_SYSPLL_D2, 1, 2),
  98. FACTOR1(CLK_TOP_SYSPLL1_D4, CLK_TOP_SYSPLL_D2, 1, 4),
  99. FACTOR1(CLK_TOP_SYSPLL1_D8, CLK_TOP_SYSPLL_D2, 1, 8),
  100. FACTOR1(CLK_TOP_SYSPLL1_D16, CLK_TOP_SYSPLL_D2, 1, 16),
  101. FACTOR1(CLK_TOP_SYSPLL2_D2, CLK_TOP_SYSPLL_D3, 1, 2),
  102. FACTOR1(CLK_TOP_SYSPLL2_D4, CLK_TOP_SYSPLL_D3, 1, 4),
  103. FACTOR1(CLK_TOP_SYSPLL2_D8, CLK_TOP_SYSPLL_D3, 1, 8),
  104. FACTOR1(CLK_TOP_SYSPLL3_D2, CLK_TOP_SYSPLL_D5, 1, 2),
  105. FACTOR1(CLK_TOP_SYSPLL3_D4, CLK_TOP_SYSPLL_D5, 1, 4),
  106. FACTOR1(CLK_TOP_SYSPLL4_D2, CLK_TOP_SYSPLL_D7, 1, 2),
  107. FACTOR1(CLK_TOP_SYSPLL4_D4, CLK_TOP_SYSPLL_D7, 1, 4),
  108. FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIVPLL, 1, 1),
  109. FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_APMIXED_UNIVPLL, 1, 2),
  110. FACTOR0(CLK_TOP_UNIVPLL_D3, CLK_APMIXED_UNIVPLL, 1, 3),
  111. FACTOR0(CLK_TOP_UNIVPLL_D5, CLK_APMIXED_UNIVPLL, 1, 5),
  112. FACTOR0(CLK_TOP_UNIVPLL_D7, CLK_APMIXED_UNIVPLL, 1, 7),
  113. FACTOR0(CLK_TOP_UNIVPLL_D26, CLK_APMIXED_UNIVPLL, 1, 26),
  114. FACTOR0(CLK_TOP_UNIVPLL_D52, CLK_APMIXED_UNIVPLL, 1, 52),
  115. FACTOR0(CLK_TOP_UNIVPLL_D108, CLK_APMIXED_UNIVPLL, 1, 108),
  116. FACTOR0(CLK_TOP_USB_PHY48M, CLK_APMIXED_UNIVPLL, 1, 26),
  117. FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL_D2, 1, 2),
  118. FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL_D2, 1, 4),
  119. FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL_D2, 1, 8),
  120. FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL_D3, 1, 2),
  121. FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL_D3, 1, 4),
  122. FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL_D3, 1, 8),
  123. FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL_D3, 1, 16),
  124. FACTOR1(CLK_TOP_UNIVPLL2_D32, CLK_TOP_UNIVPLL_D3, 1, 32),
  125. FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL_D5, 1, 2),
  126. FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL_D5, 1, 4),
  127. FACTOR1(CLK_TOP_UNIVPLL3_D8, CLK_TOP_UNIVPLL_D5, 1, 8),
  128. FACTOR0(CLK_TOP_MSDCPLL, CLK_APMIXED_MSDCPLL, 1, 1),
  129. FACTOR0(CLK_TOP_MSDCPLL_D2, CLK_APMIXED_MSDCPLL, 1, 2),
  130. FACTOR0(CLK_TOP_MSDCPLL_D4, CLK_APMIXED_MSDCPLL, 1, 4),
  131. FACTOR0(CLK_TOP_MSDCPLL_D8, CLK_APMIXED_MSDCPLL, 1, 8),
  132. FACTOR0(CLK_TOP_MMPLL, CLK_APMIXED_MMPLL, 1, 1),
  133. FACTOR0(CLK_TOP_MMPLL_D2, CLK_APMIXED_MMPLL, 1, 2),
  134. FACTOR1(CLK_TOP_DMPLL_D2, CLK_TOP_DMPLL, 1, 2),
  135. FACTOR1(CLK_TOP_DMPLL_D4, CLK_TOP_DMPLL, 1, 4),
  136. FACTOR1(CLK_TOP_DMPLL_X2, CLK_TOP_DMPLL, 1, 1),
  137. FACTOR0(CLK_TOP_TVDPLL, CLK_APMIXED_TVDPLL, 1, 1),
  138. FACTOR0(CLK_TOP_TVDPLL_D2, CLK_APMIXED_TVDPLL, 1, 2),
  139. FACTOR0(CLK_TOP_TVDPLL_D4, CLK_APMIXED_TVDPLL, 1, 4),
  140. FACTOR0(CLK_TOP_VDECPLL, CLK_APMIXED_VDECPLL, 1, 1),
  141. FACTOR0(CLK_TOP_TVD2PLL, CLK_APMIXED_TVD2PLL, 1, 1),
  142. FACTOR0(CLK_TOP_TVD2PLL_D2, CLK_APMIXED_TVD2PLL, 1, 2),
  143. FACTOR1(CLK_TOP_MIPIPLL, CLK_TOP_DPI, 1, 1),
  144. FACTOR1(CLK_TOP_MIPIPLL_D2, CLK_TOP_DPI, 1, 2),
  145. FACTOR1(CLK_TOP_MIPIPLL_D4, CLK_TOP_DPI, 1, 4),
  146. FACTOR1(CLK_TOP_HDMIPLL, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 1),
  147. FACTOR1(CLK_TOP_HDMIPLL_D2, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 2),
  148. FACTOR1(CLK_TOP_HDMIPLL_D3, CLK_TOP_HDMITX_CLKDIG_CTS, 1, 3),
  149. FACTOR0(CLK_TOP_ARMPLL_1P3G, CLK_APMIXED_ARMPLL, 1, 1),
  150. FACTOR1(CLK_TOP_AUDPLL, CLK_TOP_AUDPLL_MUX_SEL, 1, 1),
  151. FACTOR1(CLK_TOP_AUDPLL_D4, CLK_TOP_AUDPLL_MUX_SEL, 1, 4),
  152. FACTOR1(CLK_TOP_AUDPLL_D8, CLK_TOP_AUDPLL_MUX_SEL, 1, 8),
  153. FACTOR1(CLK_TOP_AUDPLL_D16, CLK_TOP_AUDPLL_MUX_SEL, 1, 16),
  154. FACTOR1(CLK_TOP_AUDPLL_D24, CLK_TOP_AUDPLL_MUX_SEL, 1, 24),
  155. FACTOR0(CLK_TOP_AUD1PLL_98M, CLK_APMIXED_AUD1PLL, 1, 3),
  156. FACTOR0(CLK_TOP_AUD2PLL_90M, CLK_APMIXED_AUD2PLL, 1, 3),
  157. FACTOR0(CLK_TOP_HADDS2PLL_98M, CLK_APMIXED_HADDS2PLL, 1, 3),
  158. FACTOR0(CLK_TOP_HADDS2PLL_294M, CLK_APMIXED_HADDS2PLL, 1, 1),
  159. FACTOR0(CLK_TOP_ETHPLL_500M, CLK_APMIXED_ETHPLL, 1, 1),
  160. FACTOR2(CLK_TOP_CLK26M_D8, CLK_XTAL, 1, 8),
  161. FACTOR2(CLK_TOP_32K_INTERNAL, CLK_XTAL, 1, 793),
  162. FACTOR1(CLK_TOP_AXISEL_D4, CLK_TOP_AXI_SEL, 1, 4),
  163. FACTOR1(CLK_TOP_8BDAC, CLK_TOP_UNIVPLL_D2, 1, 1),
  164. };
  165. static const int axi_parents[] = {
  166. CLK_XTAL,
  167. CLK_TOP_SYSPLL1_D2,
  168. CLK_TOP_SYSPLL_D5,
  169. CLK_TOP_SYSPLL1_D4,
  170. CLK_TOP_UNIVPLL_D5,
  171. CLK_TOP_UNIVPLL2_D2,
  172. CLK_TOP_MMPLL_D2,
  173. CLK_TOP_DMPLL_D2
  174. };
  175. static const int mem_parents[] = {
  176. CLK_XTAL,
  177. CLK_TOP_DMPLL
  178. };
  179. static const int ddrphycfg_parents[] = {
  180. CLK_XTAL,
  181. CLK_TOP_SYSPLL1_D8
  182. };
  183. static const int mm_parents[] = {
  184. CLK_XTAL,
  185. CLK_TOP_VENCPLL,
  186. CLK_TOP_SYSPLL1_D2,
  187. CLK_TOP_SYSPLL1_D4,
  188. CLK_TOP_UNIVPLL_D5,
  189. CLK_TOP_UNIVPLL1_D2,
  190. CLK_TOP_UNIVPLL2_D2,
  191. CLK_TOP_DMPLL
  192. };
  193. static const int pwm_parents[] = {
  194. CLK_XTAL,
  195. CLK_TOP_UNIVPLL2_D4,
  196. CLK_TOP_UNIVPLL3_D2,
  197. CLK_TOP_UNIVPLL1_D4
  198. };
  199. static const int vdec_parents[] = {
  200. CLK_XTAL,
  201. CLK_TOP_VDECPLL,
  202. CLK_TOP_SYSPLL_D5,
  203. CLK_TOP_SYSPLL1_D4,
  204. CLK_TOP_UNIVPLL_D5,
  205. CLK_TOP_UNIVPLL2_D2,
  206. CLK_TOP_VENCPLL,
  207. CLK_TOP_MSDCPLL_D2,
  208. CLK_TOP_MMPLL_D2
  209. };
  210. static const int mfg_parents[] = {
  211. CLK_XTAL,
  212. CLK_TOP_MMPLL,
  213. CLK_TOP_DMPLL_X2,
  214. CLK_TOP_MSDCPLL,
  215. CLK_XTAL,
  216. CLK_TOP_SYSPLL_D3,
  217. CLK_TOP_UNIVPLL_D3,
  218. CLK_TOP_UNIVPLL1_D2
  219. };
  220. static const int camtg_parents[] = {
  221. CLK_XTAL,
  222. CLK_TOP_UNIVPLL_D26,
  223. CLK_TOP_UNIVPLL2_D2,
  224. CLK_TOP_SYSPLL3_D2,
  225. CLK_TOP_SYSPLL3_D4,
  226. CLK_TOP_MSDCPLL_D2,
  227. CLK_TOP_MMPLL_D2
  228. };
  229. static const int uart_parents[] = {
  230. CLK_XTAL,
  231. CLK_TOP_UNIVPLL2_D8
  232. };
  233. static const int spi_parents[] = {
  234. CLK_XTAL,
  235. CLK_TOP_SYSPLL3_D2,
  236. CLK_TOP_SYSPLL4_D2,
  237. CLK_TOP_UNIVPLL2_D4,
  238. CLK_TOP_UNIVPLL1_D8
  239. };
  240. static const int usb20_parents[] = {
  241. CLK_XTAL,
  242. CLK_TOP_UNIVPLL1_D8,
  243. CLK_TOP_UNIVPLL3_D4
  244. };
  245. static const int msdc30_parents[] = {
  246. CLK_XTAL,
  247. CLK_TOP_MSDCPLL_D2,
  248. CLK_TOP_SYSPLL2_D2,
  249. CLK_TOP_SYSPLL1_D4,
  250. CLK_TOP_UNIVPLL1_D4,
  251. CLK_TOP_UNIVPLL2_D4,
  252. };
  253. static const int aud_intbus_parents[] = {
  254. CLK_XTAL,
  255. CLK_TOP_SYSPLL1_D4,
  256. CLK_TOP_SYSPLL3_D2,
  257. CLK_TOP_SYSPLL4_D2,
  258. CLK_TOP_UNIVPLL3_D2,
  259. CLK_TOP_UNIVPLL2_D4
  260. };
  261. static const int pmicspi_parents[] = {
  262. CLK_XTAL,
  263. CLK_TOP_SYSPLL1_D8,
  264. CLK_TOP_SYSPLL2_D4,
  265. CLK_TOP_SYSPLL4_D2,
  266. CLK_TOP_SYSPLL3_D4,
  267. CLK_TOP_SYSPLL2_D8,
  268. CLK_TOP_SYSPLL1_D16,
  269. CLK_TOP_UNIVPLL3_D4,
  270. CLK_TOP_UNIVPLL_D26,
  271. CLK_TOP_DMPLL_D2,
  272. CLK_TOP_DMPLL_D4
  273. };
  274. static const int scp_parents[] = {
  275. CLK_XTAL,
  276. CLK_TOP_SYSPLL1_D8,
  277. CLK_TOP_DMPLL_D2,
  278. CLK_TOP_DMPLL_D4
  279. };
  280. static const int dpi0_tve_parents[] = {
  281. CLK_XTAL,
  282. CLK_TOP_MIPIPLL,
  283. CLK_TOP_MIPIPLL_D2,
  284. CLK_TOP_MIPIPLL_D4,
  285. CLK_XTAL,
  286. CLK_TOP_TVDPLL,
  287. CLK_TOP_TVDPLL_D2,
  288. CLK_TOP_TVDPLL_D4
  289. };
  290. static const int dpi1_parents[] = {
  291. CLK_XTAL,
  292. CLK_TOP_TVDPLL,
  293. CLK_TOP_TVDPLL_D2,
  294. CLK_TOP_TVDPLL_D4
  295. };
  296. static const int hdmi_parents[] = {
  297. CLK_XTAL,
  298. CLK_TOP_HDMIPLL,
  299. CLK_TOP_HDMIPLL_D2,
  300. CLK_TOP_HDMIPLL_D3
  301. };
  302. static const int apll_parents[] = {
  303. CLK_XTAL,
  304. CLK_TOP_AUDPLL,
  305. CLK_TOP_AUDPLL_D4,
  306. CLK_TOP_AUDPLL_D8,
  307. CLK_TOP_AUDPLL_D16,
  308. CLK_TOP_AUDPLL_D24,
  309. CLK_XTAL,
  310. CLK_XTAL
  311. };
  312. static const int rtc_parents[] = {
  313. CLK_TOP_32K_INTERNAL,
  314. CLK_TOP_32K_EXTERNAL,
  315. CLK_XTAL,
  316. CLK_TOP_UNIVPLL3_D8
  317. };
  318. static const int nfi2x_parents[] = {
  319. CLK_XTAL,
  320. CLK_TOP_SYSPLL2_D2,
  321. CLK_TOP_SYSPLL_D7,
  322. CLK_TOP_UNIVPLL3_D2,
  323. CLK_TOP_SYSPLL2_D4,
  324. CLK_TOP_UNIVPLL3_D4,
  325. CLK_TOP_SYSPLL4_D4,
  326. CLK_XTAL
  327. };
  328. static const int emmc_hclk_parents[] = {
  329. CLK_XTAL,
  330. CLK_TOP_SYSPLL1_D2,
  331. CLK_TOP_SYSPLL1_D4,
  332. CLK_TOP_SYSPLL2_D2
  333. };
  334. static const int flash_parents[] = {
  335. CLK_TOP_CLK26M_D8,
  336. CLK_XTAL,
  337. CLK_TOP_SYSPLL2_D8,
  338. CLK_TOP_SYSPLL3_D4,
  339. CLK_TOP_UNIVPLL3_D4,
  340. CLK_TOP_SYSPLL4_D2,
  341. CLK_TOP_SYSPLL2_D4,
  342. CLK_TOP_UNIVPLL2_D4
  343. };
  344. static const int di_parents[] = {
  345. CLK_XTAL,
  346. CLK_TOP_TVD2PLL,
  347. CLK_TOP_TVD2PLL_D2,
  348. CLK_XTAL
  349. };
  350. static const int nr_osd_parents[] = {
  351. CLK_XTAL,
  352. CLK_TOP_VENCPLL,
  353. CLK_TOP_SYSPLL1_D2,
  354. CLK_TOP_SYSPLL1_D4,
  355. CLK_TOP_UNIVPLL_D5,
  356. CLK_TOP_UNIVPLL1_D2,
  357. CLK_TOP_UNIVPLL2_D2,
  358. CLK_TOP_DMPLL
  359. };
  360. static const int hdmirx_bist_parents[] = {
  361. CLK_XTAL,
  362. CLK_TOP_SYSPLL_D3,
  363. CLK_XTAL,
  364. CLK_TOP_SYSPLL1_D16,
  365. CLK_TOP_SYSPLL4_D2,
  366. CLK_TOP_SYSPLL1_D4,
  367. CLK_TOP_VENCPLL,
  368. CLK_XTAL
  369. };
  370. static const int intdir_parents[] = {
  371. CLK_XTAL,
  372. CLK_TOP_MMPLL,
  373. CLK_TOP_SYSPLL_D2,
  374. CLK_TOP_UNIVPLL_D2
  375. };
  376. static const int asm_parents[] = {
  377. CLK_XTAL,
  378. CLK_TOP_UNIVPLL2_D4,
  379. CLK_TOP_UNIVPLL2_D2,
  380. CLK_TOP_SYSPLL_D5
  381. };
  382. static const int ms_card_parents[] = {
  383. CLK_XTAL,
  384. CLK_TOP_UNIVPLL3_D8,
  385. CLK_TOP_SYSPLL4_D4
  386. };
  387. static const int ethif_parents[] = {
  388. CLK_XTAL,
  389. CLK_TOP_SYSPLL1_D2,
  390. CLK_TOP_SYSPLL_D5,
  391. CLK_TOP_SYSPLL1_D4,
  392. CLK_TOP_UNIVPLL_D5,
  393. CLK_TOP_UNIVPLL1_D2,
  394. CLK_TOP_DMPLL,
  395. CLK_TOP_DMPLL_D2
  396. };
  397. static const int hdmirx_parents[] = {
  398. CLK_XTAL,
  399. CLK_TOP_UNIVPLL_D52
  400. };
  401. static const int cmsys_parents[] = {
  402. CLK_XTAL,
  403. CLK_TOP_SYSPLL1_D2,
  404. CLK_TOP_UNIVPLL1_D2,
  405. CLK_TOP_UNIVPLL_D5,
  406. CLK_TOP_SYSPLL_D5,
  407. CLK_TOP_SYSPLL2_D2,
  408. CLK_TOP_SYSPLL1_D4,
  409. CLK_TOP_SYSPLL3_D2,
  410. CLK_TOP_SYSPLL2_D4,
  411. CLK_TOP_SYSPLL1_D8,
  412. CLK_XTAL,
  413. CLK_XTAL,
  414. CLK_XTAL,
  415. CLK_XTAL,
  416. CLK_XTAL
  417. };
  418. static const int clk_8bdac_parents[] = {
  419. CLK_TOP_32K_INTERNAL,
  420. CLK_TOP_8BDAC,
  421. CLK_XTAL,
  422. CLK_XTAL
  423. };
  424. static const int aud2dvd_parents[] = {
  425. CLK_TOP_AUD_48K_TIMING,
  426. CLK_TOP_AUD_44K_TIMING
  427. };
  428. static const int padmclk_parents[] = {
  429. CLK_XTAL,
  430. CLK_TOP_UNIVPLL_D26,
  431. CLK_TOP_UNIVPLL_D52,
  432. CLK_TOP_UNIVPLL_D108,
  433. CLK_TOP_UNIVPLL2_D8,
  434. CLK_TOP_UNIVPLL2_D16,
  435. CLK_TOP_UNIVPLL2_D32
  436. };
  437. static const int aud_mux_parents[] = {
  438. CLK_XTAL,
  439. CLK_TOP_AUD1PLL_98M,
  440. CLK_TOP_AUD2PLL_90M,
  441. CLK_TOP_HADDS2PLL_98M,
  442. CLK_TOP_AUD_EXTCK1_DIV,
  443. CLK_TOP_AUD_EXTCK2_DIV
  444. };
  445. static const int aud_src_parents[] = {
  446. CLK_TOP_AUD_MUX1_SEL,
  447. CLK_TOP_AUD_MUX2_SEL
  448. };
  449. static const struct mtk_composite top_muxes[] = {
  450. MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
  451. MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
  452. MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
  453. MUX_GATE_FLAGS(CLK_TOP_MM_SEL, mm_parents, 0x40, 24, 3, 31,
  454. CLK_DOMAIN_SCPSYS),
  455. MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
  456. MUX_GATE(CLK_TOP_VDEC_SEL, vdec_parents, 0x50, 8, 4, 15),
  457. MUX_GATE_FLAGS(CLK_TOP_MFG_SEL, mfg_parents, 0x50, 16, 3, 23,
  458. CLK_DOMAIN_SCPSYS),
  459. MUX_GATE(CLK_TOP_CAMTG_SEL, camtg_parents, 0x50, 24, 3, 31),
  460. MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
  461. MUX_GATE(CLK_TOP_SPI0_SEL, spi_parents, 0x60, 8, 3, 15),
  462. MUX_GATE(CLK_TOP_USB20_SEL, usb20_parents, 0x60, 16, 2, 23),
  463. MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_parents, 0x60, 24, 3, 31),
  464. MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_parents, 0x70, 0, 3, 7),
  465. MUX_GATE(CLK_TOP_MSDC30_2_SEL, msdc30_parents, 0x70, 8, 3, 15),
  466. MUX_GATE(CLK_TOP_AUDIO_SEL, msdc30_parents, 0x70, 16, 1, 23),
  467. MUX_GATE(CLK_TOP_AUDINTBUS_SEL, aud_intbus_parents, 0x70, 24, 3, 31),
  468. MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 0, 4, 7),
  469. MUX_GATE(CLK_TOP_SCP_SEL, scp_parents, 0x80, 8, 2, 15),
  470. MUX_GATE(CLK_TOP_DPI0_SEL, dpi0_tve_parents, 0x80, 16, 3, 23),
  471. MUX_GATE(CLK_TOP_DPI1_SEL, dpi1_parents, 0x80, 24, 2, 31),
  472. MUX_GATE(CLK_TOP_TVE_SEL, dpi0_tve_parents, 0x90, 0, 3, 7),
  473. MUX_GATE(CLK_TOP_HDMI_SEL, hdmi_parents, 0x90, 8, 2, 15),
  474. MUX_GATE(CLK_TOP_APLL_SEL, apll_parents, 0x90, 16, 3, 23),
  475. MUX_GATE(CLK_TOP_RTC_SEL, rtc_parents, 0xA0, 0, 2, 7),
  476. MUX_GATE(CLK_TOP_NFI2X_SEL, nfi2x_parents, 0xA0, 8, 3, 15),
  477. MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, emmc_hclk_parents, 0xA0, 24, 2, 31),
  478. MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0xB0, 0, 3, 7),
  479. MUX_GATE(CLK_TOP_DI_SEL, di_parents, 0xB0, 8, 2, 15),
  480. MUX_GATE(CLK_TOP_NR_SEL, nr_osd_parents, 0xB0, 16, 3, 23),
  481. MUX_GATE(CLK_TOP_OSD_SEL, nr_osd_parents, 0xB0, 24, 3, 31),
  482. MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, hdmirx_bist_parents, 0xC0, 0, 3, 7),
  483. MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0xC0, 8, 2, 15),
  484. MUX_GATE(CLK_TOP_ASM_I_SEL, asm_parents, 0xC0, 16, 2, 23),
  485. MUX_GATE(CLK_TOP_ASM_M_SEL, asm_parents, 0xC0, 24, 3, 31),
  486. MUX_GATE(CLK_TOP_ASM_H_SEL, asm_parents, 0xD0, 0, 2, 7),
  487. MUX_GATE(CLK_TOP_MS_CARD_SEL, ms_card_parents, 0xD0, 16, 2, 23),
  488. MUX_GATE_FLAGS(CLK_TOP_ETHIF_SEL, ethif_parents, 0xD0, 24, 3, 31,
  489. CLK_DOMAIN_SCPSYS),
  490. MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, hdmirx_parents, 0xE0, 0, 1, 7),
  491. MUX_GATE(CLK_TOP_MSDC30_3_SEL, msdc30_parents, 0xE0, 8, 3, 15),
  492. MUX_GATE(CLK_TOP_CMSYS_SEL, cmsys_parents, 0xE0, 16, 4, 23),
  493. MUX_GATE(CLK_TOP_SPI1_SEL, spi_parents, 0xE0, 24, 3, 31),
  494. MUX_GATE(CLK_TOP_SPI2_SEL, spi_parents, 0xF0, 0, 3, 7),
  495. MUX_GATE(CLK_TOP_8BDAC_SEL, clk_8bdac_parents, 0xF0, 8, 2, 15),
  496. MUX_GATE(CLK_TOP_AUD2DVD_SEL, aud2dvd_parents, 0xF0, 16, 1, 23),
  497. MUX(CLK_TOP_PADMCLK_SEL, padmclk_parents, 0x100, 0, 3),
  498. MUX(CLK_TOP_AUD_MUX1_SEL, aud_mux_parents, 0x12c, 0, 3),
  499. MUX(CLK_TOP_AUD_MUX2_SEL, aud_mux_parents, 0x12c, 3, 3),
  500. MUX(CLK_TOP_AUDPLL_MUX_SEL, aud_mux_parents, 0x12c, 6, 3),
  501. MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, aud_src_parents, 0x12c, 15, 1, 23),
  502. MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, aud_src_parents, 0x12c, 16, 1, 24),
  503. MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, aud_src_parents, 0x12c, 17, 1, 25),
  504. MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, aud_src_parents, 0x12c, 18, 1, 26),
  505. MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, aud_src_parents, 0x12c, 19, 1, 27),
  506. MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, aud_src_parents, 0x12c, 20, 1, 28),
  507. };
  508. /* infracfg */
  509. static const struct mtk_gate_regs infra_cg_regs = {
  510. .set_ofs = 0x40,
  511. .clr_ofs = 0x44,
  512. .sta_ofs = 0x48,
  513. };
  514. #define GATE_INFRA(_id, _parent, _shift) { \
  515. .id = _id, \
  516. .parent = _parent, \
  517. .regs = &infra_cg_regs, \
  518. .shift = _shift, \
  519. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  520. }
  521. static const struct mtk_gate infra_cgs[] = {
  522. GATE_INFRA(CLK_INFRA_DBG, CLK_TOP_AXI_SEL, 0),
  523. GATE_INFRA(CLK_INFRA_SMI, CLK_TOP_MM_SEL, 1),
  524. GATE_INFRA(CLK_INFRA_QAXI_CM4, CLK_TOP_AXI_SEL, 2),
  525. GATE_INFRA(CLK_INFRA_AUD_SPLIN_B, CLK_TOP_HADDS2PLL_294M, 4),
  526. GATE_INFRA(CLK_INFRA_AUDIO, CLK_XTAL, 5),
  527. GATE_INFRA(CLK_INFRA_EFUSE, CLK_XTAL, 6),
  528. GATE_INFRA(CLK_INFRA_L2C_SRAM, CLK_TOP_MM_SEL, 7),
  529. GATE_INFRA(CLK_INFRA_M4U, CLK_TOP_MEM_SEL, 8),
  530. GATE_INFRA(CLK_INFRA_CONNMCU, CLK_TOP_WBG_DIG_416M, 12),
  531. GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 13),
  532. GATE_INFRA(CLK_INFRA_RAMBUFIF, CLK_TOP_MEM_SEL, 14),
  533. GATE_INFRA(CLK_INFRA_CPUM, CLK_TOP_MEM_SEL, 15),
  534. GATE_INFRA(CLK_INFRA_KP, CLK_TOP_AXI_SEL, 16),
  535. GATE_INFRA(CLK_INFRA_CEC, CLK_TOP_RTC_SEL, 18),
  536. GATE_INFRA(CLK_INFRA_IRRX, CLK_TOP_AXI_SEL, 19),
  537. GATE_INFRA(CLK_INFRA_PMICSPI, CLK_TOP_PMICSPI_SEL, 22),
  538. GATE_INFRA(CLK_INFRA_PMICWRAP, CLK_TOP_AXI_SEL, 23),
  539. GATE_INFRA(CLK_INFRA_DDCCI, CLK_TOP_AXI_SEL, 24),
  540. };
  541. /* pericfg */
  542. static const struct mtk_gate_regs peri0_cg_regs = {
  543. .set_ofs = 0x8,
  544. .clr_ofs = 0x10,
  545. .sta_ofs = 0x18,
  546. };
  547. static const struct mtk_gate_regs peri1_cg_regs = {
  548. .set_ofs = 0xC,
  549. .clr_ofs = 0x14,
  550. .sta_ofs = 0x1C,
  551. };
  552. #define GATE_PERI0(_id, _parent, _shift) { \
  553. .id = _id, \
  554. .parent = _parent, \
  555. .regs = &peri0_cg_regs, \
  556. .shift = _shift, \
  557. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  558. }
  559. #define GATE_PERI1(_id, _parent, _shift) { \
  560. .id = _id, \
  561. .parent = _parent, \
  562. .regs = &peri1_cg_regs, \
  563. .shift = _shift, \
  564. .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
  565. }
  566. static const struct mtk_gate peri_cgs[] = {
  567. GATE_PERI0(CLK_PERI_NFI, CLK_TOP_NFI2X_SEL, 0),
  568. GATE_PERI0(CLK_PERI_THERM, CLK_TOP_AXI_SEL, 1),
  569. GATE_PERI0(CLK_PERI_PWM1, CLK_TOP_AXISEL_D4, 2),
  570. GATE_PERI0(CLK_PERI_PWM2, CLK_TOP_AXISEL_D4, 3),
  571. GATE_PERI0(CLK_PERI_PWM3, CLK_TOP_AXISEL_D4, 4),
  572. GATE_PERI0(CLK_PERI_PWM4, CLK_TOP_AXISEL_D4, 5),
  573. GATE_PERI0(CLK_PERI_PWM5, CLK_TOP_AXISEL_D4, 6),
  574. GATE_PERI0(CLK_PERI_PWM6, CLK_TOP_AXISEL_D4, 7),
  575. GATE_PERI0(CLK_PERI_PWM7, CLK_TOP_AXISEL_D4, 8),
  576. GATE_PERI0(CLK_PERI_PWM, CLK_TOP_AXI_SEL, 9),
  577. GATE_PERI0(CLK_PERI_USB0, CLK_TOP_USB20_SEL, 10),
  578. GATE_PERI0(CLK_PERI_USB1, CLK_TOP_USB20_SEL, 11),
  579. GATE_PERI0(CLK_PERI_AP_DMA, CLK_TOP_AXI_SEL, 12),
  580. GATE_PERI0(CLK_PERI_MSDC30_0, CLK_TOP_MSDC30_0_SEL, 13),
  581. GATE_PERI0(CLK_PERI_MSDC30_1, CLK_TOP_MSDC30_1_SEL, 14),
  582. GATE_PERI0(CLK_PERI_MSDC30_2, CLK_TOP_MSDC30_2_SEL, 15),
  583. GATE_PERI0(CLK_PERI_MSDC30_3, CLK_TOP_MSDC30_3_SEL, 16),
  584. GATE_PERI0(CLK_PERI_MSDC50_3, CLK_TOP_EMMC_HCLK_SEL, 17),
  585. GATE_PERI0(CLK_PERI_NLI, CLK_TOP_AXI_SEL, 18),
  586. GATE_PERI0(CLK_PERI_UART0, CLK_TOP_AXI_SEL, 19),
  587. GATE_PERI0(CLK_PERI_UART1, CLK_TOP_AXI_SEL, 20),
  588. GATE_PERI0(CLK_PERI_UART2, CLK_TOP_AXI_SEL, 21),
  589. GATE_PERI0(CLK_PERI_UART3, CLK_TOP_AXI_SEL, 22),
  590. GATE_PERI0(CLK_PERI_BTIF, CLK_TOP_AXI_SEL, 23),
  591. GATE_PERI0(CLK_PERI_I2C0, CLK_TOP_AXI_SEL, 24),
  592. GATE_PERI0(CLK_PERI_I2C1, CLK_TOP_AXI_SEL, 25),
  593. GATE_PERI0(CLK_PERI_I2C2, CLK_TOP_AXI_SEL, 26),
  594. GATE_PERI0(CLK_PERI_I2C3, CLK_XTAL, 27),
  595. GATE_PERI0(CLK_PERI_AUXADC, CLK_XTAL, 28),
  596. GATE_PERI0(CLK_PERI_SPI0, CLK_TOP_SPI0_SEL, 29),
  597. GATE_PERI0(CLK_PERI_ETH, CLK_XTAL, 30),
  598. GATE_PERI0(CLK_PERI_USB0_MCU, CLK_TOP_AXI_SEL, 31),
  599. GATE_PERI1(CLK_PERI_USB1_MCU, CLK_TOP_AXI_SEL, 0),
  600. GATE_PERI1(CLK_PERI_USB_SLV, CLK_TOP_AXI_SEL, 1),
  601. GATE_PERI1(CLK_PERI_GCPU, CLK_TOP_AXI_SEL, 2),
  602. GATE_PERI1(CLK_PERI_NFI_ECC, CLK_TOP_NFI1X_PAD, 3),
  603. GATE_PERI1(CLK_PERI_NFI_PAD, CLK_TOP_NFI1X_PAD, 4),
  604. GATE_PERI1(CLK_PERI_FLASH, CLK_TOP_NFI2X_SEL, 5),
  605. GATE_PERI1(CLK_PERI_HOST89_INT, CLK_TOP_AXI_SEL, 6),
  606. GATE_PERI1(CLK_PERI_HOST89_SPI, CLK_TOP_SPI0_SEL, 7),
  607. GATE_PERI1(CLK_PERI_HOST89_DVD, CLK_TOP_AUD2DVD_SEL, 8),
  608. GATE_PERI1(CLK_PERI_SPI1, CLK_TOP_SPI1_SEL, 9),
  609. GATE_PERI1(CLK_PERI_SPI2, CLK_TOP_SPI2_SEL, 10),
  610. GATE_PERI1(CLK_PERI_FCI, CLK_TOP_MS_CARD_SEL, 11),
  611. };
  612. /* ethsys and hifsys */
  613. static const struct mtk_gate_regs eth_hif_cg_regs = {
  614. .sta_ofs = 0x30,
  615. };
  616. #define GATE_ETH_HIF(_id, _parent, _shift, _flag) { \
  617. .id = _id, \
  618. .parent = _parent, \
  619. .regs = &eth_hif_cg_regs, \
  620. .shift = _shift, \
  621. .flags = CLK_GATE_NO_SETCLR_INV | (_flag), \
  622. }
  623. #define GATE_ETH_HIF0(_id, _parent, _shift) \
  624. GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_APMIXED)
  625. #define GATE_ETH_HIF1(_id, _parent, _shift) \
  626. GATE_ETH_HIF(_id, _parent, _shift, CLK_PARENT_TOPCKGEN)
  627. static const struct mtk_gate eth_cgs[] = {
  628. GATE_ETH_HIF1(CLK_ETHSYS_HSDMA, CLK_TOP_ETHIF_SEL, 5),
  629. GATE_ETH_HIF1(CLK_ETHSYS_ESW, CLK_TOP_ETHPLL_500M, 6),
  630. GATE_ETH_HIF0(CLK_ETHSYS_GP2, CLK_APMIXED_TRGPLL, 7),
  631. GATE_ETH_HIF1(CLK_ETHSYS_GP1, CLK_TOP_ETHPLL_500M, 8),
  632. GATE_ETH_HIF1(CLK_ETHSYS_PCM, CLK_TOP_ETHIF_SEL, 11),
  633. GATE_ETH_HIF1(CLK_ETHSYS_GDMA, CLK_TOP_ETHIF_SEL, 14),
  634. GATE_ETH_HIF1(CLK_ETHSYS_I2S, CLK_TOP_ETHIF_SEL, 17),
  635. GATE_ETH_HIF1(CLK_ETHSYS_CRYPTO, CLK_TOP_ETHIF_SEL, 29),
  636. };
  637. static const struct mtk_gate hif_cgs[] = {
  638. GATE_ETH_HIF1(CLK_HIFSYS_USB0PHY, CLK_TOP_ETHPLL_500M, 21),
  639. GATE_ETH_HIF1(CLK_HIFSYS_USB1PHY, CLK_TOP_ETHPLL_500M, 22),
  640. GATE_ETH_HIF1(CLK_HIFSYS_PCIE0, CLK_TOP_ETHPLL_500M, 24),
  641. GATE_ETH_HIF1(CLK_HIFSYS_PCIE1, CLK_TOP_ETHPLL_500M, 25),
  642. GATE_ETH_HIF1(CLK_HIFSYS_PCIE2, CLK_TOP_ETHPLL_500M, 26),
  643. };
  644. static const struct mtk_clk_tree mt7623_clk_tree = {
  645. .xtal_rate = 26 * MHZ,
  646. .xtal2_rate = 26 * MHZ,
  647. .fdivs_offs = CLK_TOP_SYSPLL,
  648. .muxes_offs = CLK_TOP_AXI_SEL,
  649. .plls = apmixed_plls,
  650. .fclks = top_fixed_clks,
  651. .fdivs = top_fixed_divs,
  652. .muxes = top_muxes,
  653. };
  654. static int mt7623_mcucfg_probe(struct udevice *dev)
  655. {
  656. void __iomem *base;
  657. base = dev_read_addr_ptr(dev);
  658. if (!base)
  659. return -ENOENT;
  660. clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
  661. AXI_DIV_SEL(0x12));
  662. return 0;
  663. }
  664. static int mt7623_apmixedsys_probe(struct udevice *dev)
  665. {
  666. struct mtk_clk_priv *priv = dev_get_priv(dev);
  667. int ret;
  668. ret = mtk_common_clk_init(dev, &mt7623_clk_tree);
  669. if (ret)
  670. return ret;
  671. /* reduce clock square disable time */
  672. writel(0x50001, priv->base + MT7623_CLKSQ_STB_CON0);
  673. /* extend control timing to 1us */
  674. writel(0x888, priv->base + MT7623_PLL_ISO_CON0);
  675. return 0;
  676. }
  677. static int mt7623_topckgen_probe(struct udevice *dev)
  678. {
  679. return mtk_common_clk_init(dev, &mt7623_clk_tree);
  680. }
  681. static int mt7623_infracfg_probe(struct udevice *dev)
  682. {
  683. return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, infra_cgs);
  684. }
  685. static int mt7623_pericfg_probe(struct udevice *dev)
  686. {
  687. return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, peri_cgs);
  688. }
  689. static int mt7623_hifsys_probe(struct udevice *dev)
  690. {
  691. return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, hif_cgs);
  692. }
  693. static int mt7623_ethsys_probe(struct udevice *dev)
  694. {
  695. return mtk_common_clk_gate_init(dev, &mt7623_clk_tree, eth_cgs);
  696. }
  697. static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
  698. {
  699. int ret = 0;
  700. #if CONFIG_IS_ENABLED(RESET_MEDIATEK)
  701. ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
  702. if (ret)
  703. debug("Warning: failed to bind reset controller\n");
  704. #endif
  705. return ret;
  706. }
  707. static const struct udevice_id mt7623_apmixed_compat[] = {
  708. { .compatible = "mediatek,mt7623-apmixedsys" },
  709. { }
  710. };
  711. static const struct udevice_id mt7623_topckgen_compat[] = {
  712. { .compatible = "mediatek,mt7623-topckgen" },
  713. { }
  714. };
  715. static const struct udevice_id mt7623_infracfg_compat[] = {
  716. { .compatible = "mediatek,mt7623-infracfg", },
  717. { }
  718. };
  719. static const struct udevice_id mt7623_pericfg_compat[] = {
  720. { .compatible = "mediatek,mt7623-pericfg", },
  721. { }
  722. };
  723. static const struct udevice_id mt7623_ethsys_compat[] = {
  724. { .compatible = "mediatek,mt7623-ethsys" },
  725. { }
  726. };
  727. static const struct udevice_id mt7623_hifsys_compat[] = {
  728. { .compatible = "mediatek,mt7623-hifsys" },
  729. { }
  730. };
  731. static const struct udevice_id mt7623_mcucfg_compat[] = {
  732. { .compatible = "mediatek,mt7623-mcucfg" },
  733. { }
  734. };
  735. U_BOOT_DRIVER(mtk_mcucfg) = {
  736. .name = "mt7623-mcucfg",
  737. .id = UCLASS_SYSCON,
  738. .of_match = mt7623_mcucfg_compat,
  739. .probe = mt7623_mcucfg_probe,
  740. .flags = DM_FLAG_PRE_RELOC,
  741. };
  742. U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
  743. .name = "mt7623-clock-apmixedsys",
  744. .id = UCLASS_CLK,
  745. .of_match = mt7623_apmixed_compat,
  746. .probe = mt7623_apmixedsys_probe,
  747. .priv_auto = sizeof(struct mtk_clk_priv),
  748. .ops = &mtk_clk_apmixedsys_ops,
  749. .flags = DM_FLAG_PRE_RELOC,
  750. };
  751. U_BOOT_DRIVER(mtk_clk_topckgen) = {
  752. .name = "mt7623-clock-topckgen",
  753. .id = UCLASS_CLK,
  754. .of_match = mt7623_topckgen_compat,
  755. .probe = mt7623_topckgen_probe,
  756. .priv_auto = sizeof(struct mtk_clk_priv),
  757. .ops = &mtk_clk_topckgen_ops,
  758. .flags = DM_FLAG_PRE_RELOC,
  759. };
  760. U_BOOT_DRIVER(mtk_clk_infracfg) = {
  761. .name = "mt7623-infracfg",
  762. .id = UCLASS_CLK,
  763. .of_match = mt7623_infracfg_compat,
  764. .probe = mt7623_infracfg_probe,
  765. .priv_auto = sizeof(struct mtk_cg_priv),
  766. .ops = &mtk_clk_gate_ops,
  767. .flags = DM_FLAG_PRE_RELOC,
  768. };
  769. U_BOOT_DRIVER(mtk_clk_pericfg) = {
  770. .name = "mt7623-pericfg",
  771. .id = UCLASS_CLK,
  772. .of_match = mt7623_pericfg_compat,
  773. .probe = mt7623_pericfg_probe,
  774. .priv_auto = sizeof(struct mtk_cg_priv),
  775. .ops = &mtk_clk_gate_ops,
  776. .flags = DM_FLAG_PRE_RELOC,
  777. };
  778. U_BOOT_DRIVER(mtk_clk_hifsys) = {
  779. .name = "mt7623-clock-hifsys",
  780. .id = UCLASS_CLK,
  781. .of_match = mt7623_hifsys_compat,
  782. .probe = mt7623_hifsys_probe,
  783. .bind = mt7623_ethsys_hifsys_bind,
  784. .priv_auto = sizeof(struct mtk_cg_priv),
  785. .ops = &mtk_clk_gate_ops,
  786. };
  787. U_BOOT_DRIVER(mtk_clk_ethsys) = {
  788. .name = "mt7623-clock-ethsys",
  789. .id = UCLASS_CLK,
  790. .of_match = mt7623_ethsys_compat,
  791. .probe = mt7623_ethsys_probe,
  792. .bind = mt7623_ethsys_hifsys_bind,
  793. .priv_auto = sizeof(struct mtk_cg_priv),
  794. .ops = &mtk_clk_gate_ops,
  795. };