clk-pll.c 862 B

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Exynos PLL helper functions for clock drivers.
  4. * Copyright (C) 2016 Samsung Electronics
  5. * Thomas Abraham <thomas.ab@samsung.com>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <div64.h>
  10. #define PLL145X_MDIV_SHIFT 16
  11. #define PLL145X_MDIV_MASK 0x3ff
  12. #define PLL145X_PDIV_SHIFT 8
  13. #define PLL145X_PDIV_MASK 0x3f
  14. #define PLL145X_SDIV_SHIFT 0
  15. #define PLL145X_SDIV_MASK 0x7
  16. unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq)
  17. {
  18. unsigned long pll_con1 = readl(con1);
  19. unsigned long mdiv, sdiv, pdiv;
  20. uint64_t fvco = fin_freq;
  21. mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
  22. pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
  23. sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
  24. fvco *= mdiv;
  25. do_div(fvco, (pdiv << sdiv));
  26. return (unsigned long)fvco;
  27. }