clk_versaclock.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0-or-later
  2. /*
  3. * Driver for IDT Versaclock 5/6
  4. *
  5. * Derived from code Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  6. */
  7. #include <common.h>
  8. #include <clk.h>
  9. #include <clk-uclass.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <i2c.h>
  13. #include <dm/device_compat.h>
  14. #include <log.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/kernel.h>
  17. #include <linux/math64.h>
  18. #include <dt-bindings/clk/versaclock.h>
  19. /* VersaClock5 registers */
  20. #define VC5_OTP_CONTROL 0x00
  21. /* Factory-reserved register block */
  22. #define VC5_RSVD_DEVICE_ID 0x01
  23. #define VC5_RSVD_ADC_GAIN_7_0 0x02
  24. #define VC5_RSVD_ADC_GAIN_15_8 0x03
  25. #define VC5_RSVD_ADC_OFFSET_7_0 0x04
  26. #define VC5_RSVD_ADC_OFFSET_15_8 0x05
  27. #define VC5_RSVD_TEMPY 0x06
  28. #define VC5_RSVD_OFFSET_TBIN 0x07
  29. #define VC5_RSVD_GAIN 0x08
  30. #define VC5_RSVD_TEST_NP 0x09
  31. #define VC5_RSVD_UNUSED 0x0a
  32. #define VC5_RSVD_BANDGAP_TRIM_UP 0x0b
  33. #define VC5_RSVD_BANDGAP_TRIM_DN 0x0c
  34. #define VC5_RSVD_CLK_R_12_CLK_AMP_4 0x0d
  35. #define VC5_RSVD_CLK_R_34_CLK_AMP_4 0x0e
  36. #define VC5_RSVD_CLK_AMP_123 0x0f
  37. /* Configuration register block */
  38. #define VC5_PRIM_SRC_SHDN 0x10
  39. #define VC5_PRIM_SRC_SHDN_EN_XTAL BIT(7)
  40. #define VC5_PRIM_SRC_SHDN_EN_CLKIN BIT(6)
  41. #define VC5_PRIM_SRC_SHDN_EN_DOUBLE_XTAL_FREQ BIT(3)
  42. #define VC5_PRIM_SRC_SHDN_SP BIT(1)
  43. #define VC5_PRIM_SRC_SHDN_EN_GBL_SHDN BIT(0)
  44. #define VC5_VCO_BAND 0x11
  45. #define VC5_XTAL_X1_LOAD_CAP 0x12
  46. #define VC5_XTAL_X2_LOAD_CAP 0x13
  47. #define VC5_REF_DIVIDER 0x15
  48. #define VC5_REF_DIVIDER_SEL_PREDIV2 BIT(7)
  49. #define VC5_REF_DIVIDER_REF_DIV(n) ((n) & 0x3f)
  50. #define VC5_VCO_CTRL_AND_PREDIV 0x16
  51. #define VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV BIT(7)
  52. #define VC5_FEEDBACK_INT_DIV 0x17
  53. #define VC5_FEEDBACK_INT_DIV_BITS 0x18
  54. #define VC5_FEEDBACK_FRAC_DIV(n) (0x19 + (n))
  55. #define VC5_RC_CONTROL0 0x1e
  56. #define VC5_RC_CONTROL1 0x1f
  57. /* Register 0x20 is factory reserved */
  58. /* Output divider control for divider 1,2,3,4 */
  59. #define VC5_OUT_DIV_CONTROL(idx) (0x21 + ((idx) * 0x10))
  60. #define VC5_OUT_DIV_CONTROL_RESET BIT(7)
  61. #define VC5_OUT_DIV_CONTROL_SELB_NORM BIT(3)
  62. #define VC5_OUT_DIV_CONTROL_SEL_EXT BIT(2)
  63. #define VC5_OUT_DIV_CONTROL_INT_MODE BIT(1)
  64. #define VC5_OUT_DIV_CONTROL_EN_FOD BIT(0)
  65. #define VC5_OUT_DIV_FRAC(idx, n) (0x22 + ((idx) * 0x10) + (n))
  66. #define VC5_OUT_DIV_FRAC4_OD_SCEE BIT(1)
  67. #define VC5_OUT_DIV_STEP_SPREAD(idx, n) (0x26 + ((idx) * 0x10) + (n))
  68. #define VC5_OUT_DIV_SPREAD_MOD(idx, n) (0x29 + ((idx) * 0x10) + (n))
  69. #define VC5_OUT_DIV_SKEW_INT(idx, n) (0x2b + ((idx) * 0x10) + (n))
  70. #define VC5_OUT_DIV_INT(idx, n) (0x2d + ((idx) * 0x10) + (n))
  71. #define VC5_OUT_DIV_SKEW_FRAC(idx) (0x2f + ((idx) * 0x10))
  72. /* Registers 0x30, 0x40, 0x50 are factory reserved */
  73. /* Clock control register for clock 1,2 */
  74. #define VC5_CLK_OUTPUT_CFG(idx, n) (0x60 + ((idx) * 0x2) + (n))
  75. #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT 5
  76. #define VC5_CLK_OUTPUT_CFG0_CFG_MASK GENMASK(7, VC5_CLK_OUTPUT_CFG0_CFG_SHIFT)
  77. #define VC5_CLK_OUTPUT_CFG0_CFG_LVPECL (VC5_LVPECL)
  78. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS (VC5_CMOS)
  79. #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL33 (VC5_HCSL33)
  80. #define VC5_CLK_OUTPUT_CFG0_CFG_LVDS (VC5_LVDS)
  81. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOS2 (VC5_CMOS2)
  82. #define VC5_CLK_OUTPUT_CFG0_CFG_CMOSD (VC5_CMOSD)
  83. #define VC5_CLK_OUTPUT_CFG0_CFG_HCSL25 (VC5_HCSL25)
  84. #define VC5_CLK_OUTPUT_CFG0_PWR_SHIFT 3
  85. #define VC5_CLK_OUTPUT_CFG0_PWR_MASK GENMASK(4, VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  86. #define VC5_CLK_OUTPUT_CFG0_PWR_18 (0 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  87. #define VC5_CLK_OUTPUT_CFG0_PWR_25 (2 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  88. #define VC5_CLK_OUTPUT_CFG0_PWR_33 (3 << VC5_CLK_OUTPUT_CFG0_PWR_SHIFT)
  89. #define VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT 0
  90. #define VC5_CLK_OUTPUT_CFG0_SLEW_MASK GENMASK(1, VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  91. #define VC5_CLK_OUTPUT_CFG0_SLEW_80 (0 << VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  92. #define VC5_CLK_OUTPUT_CFG0_SLEW_85 (1 << VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  93. #define VC5_CLK_OUTPUT_CFG0_SLEW_90 (2 << VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  94. #define VC5_CLK_OUTPUT_CFG0_SLEW_100 (3 << VC5_CLK_OUTPUT_CFG0_SLEW_SHIFT)
  95. #define VC5_CLK_OUTPUT_CFG1_EN_CLKBUF BIT(0)
  96. #define VC5_CLK_OE_SHDN 0x68
  97. #define VC5_CLK_OS_SHDN 0x69
  98. #define VC5_GLOBAL_REGISTER 0x76
  99. #define VC5_GLOBAL_REGISTER_GLOBAL_RESET BIT(5)
  100. /* PLL/VCO runs between 2.5 GHz and 3.0 GHz */
  101. #define VC5_PLL_VCO_MIN 2500000000UL
  102. #define VC5_PLL_VCO_MAX 3000000000UL
  103. /* VC5 Input mux settings */
  104. #define VC5_MUX_IN_XIN BIT(0)
  105. #define VC5_MUX_IN_CLKIN BIT(1)
  106. /* Maximum number of clk_out supported by this driver */
  107. #define VC5_MAX_CLK_OUT_NUM 5
  108. /* Maximum number of FODs supported by this driver */
  109. #define VC5_MAX_FOD_NUM 4
  110. /* flags to describe chip features */
  111. /* chip has built-in oscilator */
  112. #define VC5_HAS_INTERNAL_XTAL BIT(0)
  113. /* chip has PFD requency doubler */
  114. #define VC5_HAS_PFD_FREQ_DBL BIT(1)
  115. /* Supported IDT VC5 models. */
  116. enum vc5_model {
  117. IDT_VC5_5P49V5923,
  118. IDT_VC5_5P49V5925,
  119. IDT_VC5_5P49V5933,
  120. IDT_VC5_5P49V5935,
  121. IDT_VC6_5P49V6901,
  122. IDT_VC6_5P49V6965,
  123. };
  124. /* Structure to describe features of a particular VC5 model */
  125. struct vc5_chip_info {
  126. const enum vc5_model model;
  127. const unsigned int clk_fod_cnt;
  128. const unsigned int clk_out_cnt;
  129. const u32 flags;
  130. };
  131. struct vc5_driver_data;
  132. struct vc5_hw_data {
  133. struct clk hw;
  134. struct vc5_driver_data *vc5;
  135. u32 div_int;
  136. u32 div_frc;
  137. unsigned int num;
  138. };
  139. struct vc5_out_data {
  140. struct clk hw;
  141. struct vc5_driver_data *vc5;
  142. unsigned int num;
  143. unsigned int clk_output_cfg0;
  144. unsigned int clk_output_cfg0_mask;
  145. };
  146. struct vc5_driver_data {
  147. struct udevice *i2c;
  148. const struct vc5_chip_info *chip_info;
  149. struct clk *pin_xin;
  150. struct clk *pin_clkin;
  151. unsigned char clk_mux_ins;
  152. struct clk clk_mux;
  153. struct clk clk_mul;
  154. struct clk clk_pfd;
  155. struct vc5_hw_data clk_pll;
  156. struct vc5_hw_data clk_fod[VC5_MAX_FOD_NUM];
  157. struct vc5_out_data clk_out[VC5_MAX_CLK_OUT_NUM];
  158. };
  159. static const struct vc5_chip_info idt_5p49v5923_info = {
  160. .model = IDT_VC5_5P49V5923,
  161. .clk_fod_cnt = 2,
  162. .clk_out_cnt = 3,
  163. .flags = 0,
  164. };
  165. static const struct vc5_chip_info idt_5p49v5925_info = {
  166. .model = IDT_VC5_5P49V5925,
  167. .clk_fod_cnt = 4,
  168. .clk_out_cnt = 5,
  169. .flags = 0,
  170. };
  171. static const struct vc5_chip_info idt_5p49v5933_info = {
  172. .model = IDT_VC5_5P49V5933,
  173. .clk_fod_cnt = 2,
  174. .clk_out_cnt = 3,
  175. .flags = VC5_HAS_INTERNAL_XTAL,
  176. };
  177. static const struct vc5_chip_info idt_5p49v5935_info = {
  178. .model = IDT_VC5_5P49V5935,
  179. .clk_fod_cnt = 4,
  180. .clk_out_cnt = 5,
  181. .flags = VC5_HAS_INTERNAL_XTAL,
  182. };
  183. static const struct vc5_chip_info idt_5p49v6901_info = {
  184. .model = IDT_VC6_5P49V6901,
  185. .clk_fod_cnt = 4,
  186. .clk_out_cnt = 5,
  187. .flags = VC5_HAS_PFD_FREQ_DBL,
  188. };
  189. static const struct vc5_chip_info idt_5p49v6965_info = {
  190. .model = IDT_VC6_5P49V6965,
  191. .clk_fod_cnt = 4,
  192. .clk_out_cnt = 5,
  193. .flags = 0,
  194. };
  195. static int vc5_update_bits(struct udevice *dev, unsigned int reg, unsigned int mask,
  196. unsigned int src)
  197. {
  198. int ret;
  199. unsigned char cache;
  200. ret = dm_i2c_read(dev, reg, &cache, 1);
  201. if (ret < 0)
  202. return ret;
  203. cache &= ~mask;
  204. cache |= mask & src;
  205. ret = dm_i2c_write(dev, reg, (uchar *)&cache, 1);
  206. return ret;
  207. }
  208. static unsigned long vc5_mux_get_rate(struct clk *hw)
  209. {
  210. return clk_get_rate(clk_get_parent(hw));
  211. }
  212. static int vc5_mux_set_parent(struct clk *hw, unsigned char index)
  213. {
  214. struct vc5_driver_data *vc5 = container_of(hw, struct vc5_driver_data, clk_mux);
  215. const u8 mask = VC5_PRIM_SRC_SHDN_EN_XTAL | VC5_PRIM_SRC_SHDN_EN_CLKIN;
  216. u8 src;
  217. if (index > 1 || !vc5->clk_mux_ins)
  218. return -EINVAL;
  219. if (vc5->clk_mux_ins == (VC5_MUX_IN_CLKIN | VC5_MUX_IN_XIN)) {
  220. if (index == 0)
  221. src = VC5_PRIM_SRC_SHDN_EN_XTAL;
  222. if (index == 1)
  223. src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
  224. } else {
  225. if (index != 0)
  226. return -EINVAL;
  227. if (vc5->clk_mux_ins == VC5_MUX_IN_XIN)
  228. src = VC5_PRIM_SRC_SHDN_EN_XTAL;
  229. else if (vc5->clk_mux_ins == VC5_MUX_IN_CLKIN)
  230. src = VC5_PRIM_SRC_SHDN_EN_CLKIN;
  231. else /* Invalid; should have been caught by vc5_probe() */
  232. return -EINVAL;
  233. }
  234. return vc5_update_bits(vc5->i2c, VC5_PRIM_SRC_SHDN, mask, src);
  235. }
  236. static const struct clk_ops vc5_mux_ops = {
  237. .get_rate = vc5_mux_get_rate,
  238. };
  239. static unsigned long vc5_pfd_round_rate(struct clk *hw, unsigned long rate)
  240. {
  241. struct clk *clk_parent = clk_get_parent(hw);
  242. unsigned long parent_rate = clk_get_rate(clk_parent);
  243. unsigned long idiv;
  244. /* PLL cannot operate with input clock above 50 MHz. */
  245. if (rate > 50000000)
  246. return -EINVAL;
  247. /* CLKIN within range of PLL input, feed directly to PLL. */
  248. if (parent_rate <= 50000000)
  249. return parent_rate;
  250. idiv = DIV_ROUND_UP(parent_rate, rate);
  251. if (idiv > 127)
  252. return -EINVAL;
  253. return parent_rate / idiv;
  254. }
  255. static unsigned long vc5_pfd_recalc_rate(struct clk *hw)
  256. {
  257. struct vc5_driver_data *vc5 =
  258. container_of(hw, struct vc5_driver_data, clk_pfd);
  259. unsigned int prediv, div;
  260. struct clk *clk_parent = clk_get_parent(hw);
  261. unsigned long parent_rate = clk_get_rate(clk_parent);
  262. dm_i2c_read(vc5->i2c, VC5_VCO_CTRL_AND_PREDIV, (uchar *)&prediv, 1);
  263. /* The bypass_prediv is set, PLL fed from Ref_in directly. */
  264. if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
  265. return parent_rate;
  266. dm_i2c_read(vc5->i2c, VC5_REF_DIVIDER, (uchar *)&div, 1);
  267. /* The Sel_prediv2 is set, PLL fed from prediv2 (Ref_in / 2) */
  268. if (div & VC5_REF_DIVIDER_SEL_PREDIV2)
  269. return parent_rate / 2;
  270. else
  271. return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
  272. }
  273. static unsigned long vc5_pfd_set_rate(struct clk *hw, unsigned long rate)
  274. {
  275. struct vc5_driver_data *vc5 =
  276. container_of(hw, struct vc5_driver_data, clk_pfd);
  277. unsigned long idiv;
  278. u8 div;
  279. struct clk *clk_parent = clk_get_parent(hw);
  280. unsigned long parent_rate = clk_get_rate(clk_parent);
  281. /* CLKIN within range of PLL input, feed directly to PLL. */
  282. if (parent_rate <= 50000000) {
  283. vc5_update_bits(vc5->i2c, VC5_VCO_CTRL_AND_PREDIV,
  284. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV,
  285. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV);
  286. vc5_update_bits(vc5->i2c, VC5_REF_DIVIDER, 0xff, 0x00);
  287. return 0;
  288. }
  289. idiv = DIV_ROUND_UP(parent_rate, rate);
  290. /* We have dedicated div-2 predivider. */
  291. if (idiv == 2)
  292. div = VC5_REF_DIVIDER_SEL_PREDIV2;
  293. else
  294. div = VC5_REF_DIVIDER_REF_DIV(idiv);
  295. vc5_update_bits(vc5->i2c, VC5_REF_DIVIDER, 0xff, div);
  296. vc5_update_bits(vc5->i2c, VC5_VCO_CTRL_AND_PREDIV,
  297. VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV, 0);
  298. return 0;
  299. }
  300. static const struct clk_ops vc5_pfd_ops = {
  301. .round_rate = vc5_pfd_round_rate,
  302. .get_rate = vc5_pfd_recalc_rate,
  303. .set_rate = vc5_pfd_set_rate,
  304. };
  305. /*
  306. * VersaClock5 PLL/VCO
  307. */
  308. static unsigned long vc5_pll_recalc_rate(struct clk *hw)
  309. {
  310. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  311. struct vc5_driver_data *vc = hwdata->vc5;
  312. struct clk *clk_parent = clk_get_parent(hw);
  313. unsigned long parent_rate = clk_get_rate(clk_parent);
  314. u32 div_int, div_frc;
  315. u8 fb[5];
  316. dm_i2c_read(vc->i2c, VC5_FEEDBACK_INT_DIV, fb, 5);
  317. div_int = (fb[0] << 4) | (fb[1] >> 4);
  318. div_frc = (fb[2] << 16) | (fb[3] << 8) | fb[4];
  319. /* The PLL divider has 12 integer bits and 24 fractional bits */
  320. return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
  321. }
  322. static unsigned long vc5_pll_round_rate(struct clk *hw, unsigned long rate)
  323. {
  324. struct clk *clk_parent = clk_get_parent(hw);
  325. unsigned long parent_rate = clk_get_rate(clk_parent);
  326. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  327. u32 div_int;
  328. u64 div_frc;
  329. if (rate < VC5_PLL_VCO_MIN)
  330. rate = VC5_PLL_VCO_MIN;
  331. if (rate > VC5_PLL_VCO_MAX)
  332. rate = VC5_PLL_VCO_MAX;
  333. /* Determine integer part, which is 12 bit wide */
  334. div_int = rate / parent_rate;
  335. if (div_int > 0xfff)
  336. rate = parent_rate * 0xfff;
  337. /* Determine best fractional part, which is 24 bit wide */
  338. div_frc = rate % parent_rate;
  339. div_frc *= BIT(24) - 1;
  340. do_div(div_frc, parent_rate);
  341. hwdata->div_int = div_int;
  342. hwdata->div_frc = (u32)div_frc;
  343. return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
  344. }
  345. static unsigned long vc5_pll_set_rate(struct clk *hw, unsigned long rate)
  346. {
  347. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  348. struct vc5_driver_data *vc5 = hwdata->vc5;
  349. u8 fb[5];
  350. fb[0] = hwdata->div_int >> 4;
  351. fb[1] = hwdata->div_int << 4;
  352. fb[2] = hwdata->div_frc >> 16;
  353. fb[3] = hwdata->div_frc >> 8;
  354. fb[4] = hwdata->div_frc;
  355. return dm_i2c_write(vc5->i2c, VC5_FEEDBACK_INT_DIV, fb, 5);
  356. }
  357. static const struct clk_ops vc5_pll_ops = {
  358. .round_rate = vc5_pll_round_rate,
  359. .get_rate = vc5_pll_recalc_rate,
  360. .set_rate = vc5_pll_set_rate,
  361. };
  362. static unsigned long vc5_fod_recalc_rate(struct clk *hw)
  363. {
  364. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  365. struct vc5_driver_data *vc = hwdata->vc5;
  366. struct clk *parent = &vc->clk_pll.hw;
  367. unsigned long parent_rate = vc5_pll_recalc_rate(parent);
  368. /* VCO frequency is divided by two before entering FOD */
  369. u32 f_in = parent_rate / 2;
  370. u32 div_int, div_frc;
  371. u8 od_int[2];
  372. u8 od_frc[4];
  373. dm_i2c_read(vc->i2c, VC5_OUT_DIV_INT(hwdata->num, 0), od_int, 2);
  374. dm_i2c_read(vc->i2c, VC5_OUT_DIV_FRAC(hwdata->num, 0), od_frc, 4);
  375. div_int = (od_int[0] << 4) | (od_int[1] >> 4);
  376. div_frc = (od_frc[0] << 22) | (od_frc[1] << 14) |
  377. (od_frc[2] << 6) | (od_frc[3] >> 2);
  378. /* Avoid division by zero if the output is not configured. */
  379. if (div_int == 0 && div_frc == 0)
  380. return 0;
  381. /* The PLL divider has 12 integer bits and 30 fractional bits */
  382. return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
  383. }
  384. static unsigned long vc5_fod_round_rate(struct clk *hw, unsigned long rate)
  385. {
  386. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  387. struct vc5_driver_data *vc = hwdata->vc5;
  388. struct clk *parent = &vc->clk_pll.hw;
  389. unsigned long parent_rate = vc5_pll_recalc_rate(parent);
  390. /* VCO frequency is divided by two before entering FOD */
  391. u32 f_in = parent_rate / 2;
  392. u32 div_int;
  393. u64 div_frc;
  394. /* Determine integer part, which is 12 bit wide */
  395. div_int = f_in / rate;
  396. /*
  397. * WARNING: The clock chip does not output signal if the integer part
  398. * of the divider is 0xfff and fractional part is non-zero.
  399. * Clamp the divider at 0xffe to keep the code simple.
  400. */
  401. if (div_int > 0xffe) {
  402. div_int = 0xffe;
  403. rate = f_in / div_int;
  404. }
  405. /* Determine best fractional part, which is 30 bit wide */
  406. div_frc = f_in % rate;
  407. div_frc <<= 24;
  408. do_div(div_frc, rate);
  409. hwdata->div_int = div_int;
  410. hwdata->div_frc = (u32)div_frc;
  411. return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
  412. }
  413. static unsigned long vc5_fod_set_rate(struct clk *hw, unsigned long rate)
  414. {
  415. struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
  416. struct vc5_driver_data *vc5 = hwdata->vc5;
  417. u8 data[14] = {
  418. hwdata->div_frc >> 22, hwdata->div_frc >> 14,
  419. hwdata->div_frc >> 6, hwdata->div_frc << 2,
  420. 0, 0, 0, 0, 0,
  421. 0, 0,
  422. hwdata->div_int >> 4, hwdata->div_int << 4,
  423. 0
  424. };
  425. dm_i2c_write(vc5->i2c, VC5_OUT_DIV_FRAC(hwdata->num, 0), data, 14);
  426. /*
  427. * Toggle magic bit in undocumented register for unknown reason.
  428. * This is what the IDT timing commander tool does and the chip
  429. * datasheet somewhat implies this is needed, but the register
  430. * and the bit is not documented.
  431. */
  432. vc5_update_bits(vc5->i2c, VC5_GLOBAL_REGISTER,
  433. VC5_GLOBAL_REGISTER_GLOBAL_RESET, 0);
  434. vc5_update_bits(vc5->i2c, VC5_GLOBAL_REGISTER,
  435. VC5_GLOBAL_REGISTER_GLOBAL_RESET,
  436. VC5_GLOBAL_REGISTER_GLOBAL_RESET);
  437. return 0;
  438. }
  439. static const struct clk_ops vc5_fod_ops = {
  440. .round_rate = vc5_fod_round_rate,
  441. .get_rate = vc5_fod_recalc_rate,
  442. .set_rate = vc5_fod_set_rate,
  443. };
  444. static int vc5_clk_out_prepare(struct clk *hw)
  445. {
  446. struct udevice *dev;
  447. struct vc5_driver_data *vc5;
  448. struct vc5_out_data *hwdata;
  449. const u8 mask = VC5_OUT_DIV_CONTROL_SELB_NORM |
  450. VC5_OUT_DIV_CONTROL_SEL_EXT |
  451. VC5_OUT_DIV_CONTROL_EN_FOD;
  452. unsigned int src;
  453. int ret;
  454. uclass_get_device_by_name(UCLASS_CLK, clk_hw_get_name(hw), &dev);
  455. vc5 = dev_get_priv(dev);
  456. hwdata = &vc5->clk_out[hw->id];
  457. /*
  458. * If the input mux is disabled, enable it first and
  459. * select source from matching FOD.
  460. */
  461. dm_i2c_read(vc5->i2c, VC5_OUT_DIV_CONTROL(hwdata->num), (uchar *)&src, 1);
  462. if ((src & mask) == 0) {
  463. src = VC5_OUT_DIV_CONTROL_RESET | VC5_OUT_DIV_CONTROL_EN_FOD;
  464. ret = vc5_update_bits(vc5->i2c,
  465. VC5_OUT_DIV_CONTROL(hwdata->num),
  466. mask | VC5_OUT_DIV_CONTROL_RESET, src);
  467. if (ret)
  468. return ret;
  469. }
  470. /* Enable the clock buffer */
  471. vc5_update_bits(vc5->i2c, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
  472. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF,
  473. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF);
  474. if (hwdata->clk_output_cfg0_mask) {
  475. vc5_update_bits(vc5->i2c, VC5_CLK_OUTPUT_CFG(hwdata->num, 0),
  476. hwdata->clk_output_cfg0_mask,
  477. hwdata->clk_output_cfg0);
  478. }
  479. return 0;
  480. }
  481. static int vc5_clk_out_unprepare(struct clk *hw)
  482. {
  483. struct udevice *dev;
  484. struct vc5_driver_data *vc5;
  485. struct vc5_out_data *hwdata;
  486. int ret;
  487. uclass_get_device_by_name(UCLASS_CLK, clk_hw_get_name(hw), &dev);
  488. vc5 = dev_get_priv(dev);
  489. hwdata = &vc5->clk_out[hw->id];
  490. /* Disable the clock buffer */
  491. ret = vc5_update_bits(vc5->i2c, VC5_CLK_OUTPUT_CFG(hwdata->num, 1),
  492. VC5_CLK_OUTPUT_CFG1_EN_CLKBUF, 0);
  493. return ret;
  494. }
  495. static int vc5_clk_out_set_parent(struct vc5_driver_data *vc, u8 num, u8 index)
  496. {
  497. const u8 mask = VC5_OUT_DIV_CONTROL_RESET |
  498. VC5_OUT_DIV_CONTROL_SELB_NORM |
  499. VC5_OUT_DIV_CONTROL_SEL_EXT |
  500. VC5_OUT_DIV_CONTROL_EN_FOD;
  501. const u8 extclk = VC5_OUT_DIV_CONTROL_SELB_NORM |
  502. VC5_OUT_DIV_CONTROL_SEL_EXT;
  503. u8 src = VC5_OUT_DIV_CONTROL_RESET;
  504. if (index == 0)
  505. src |= VC5_OUT_DIV_CONTROL_EN_FOD;
  506. else
  507. src |= extclk;
  508. return vc5_update_bits(vc->i2c, VC5_OUT_DIV_CONTROL(num), mask, src);
  509. }
  510. /*
  511. * The device references to the Versaclock point to the head, so xlate needs to
  512. * redirect it to clk_out[idx]
  513. */
  514. static int vc5_clk_out_xlate(struct clk *hw, struct ofnode_phandle_args *args)
  515. {
  516. unsigned int idx = args->args[0];
  517. if (args->args_count != 1) {
  518. debug("Invaild args_count: %d\n", args->args_count);
  519. return -EINVAL;
  520. }
  521. hw->id = idx;
  522. return 0;
  523. }
  524. static unsigned long vc5_clk_out_set_rate(struct clk *hw, unsigned long rate)
  525. {
  526. struct udevice *dev;
  527. struct vc5_driver_data *vc;
  528. struct clk *parent;
  529. uclass_get_device_by_name(UCLASS_CLK, clk_hw_get_name(hw), &dev);
  530. vc = dev_get_priv(dev);
  531. parent = clk_get_parent(&vc->clk_out[hw->id].hw);
  532. /* setting the output rate really means setting the parent FOD rate */
  533. return clk_set_rate(parent, clk_round_rate(parent, rate));
  534. }
  535. static unsigned long vc5_clk_out_get_rate(struct clk *hw)
  536. {
  537. return clk_get_parent_rate(hw);
  538. }
  539. static const struct clk_ops vc5_clk_out_ops = {
  540. .enable = vc5_clk_out_prepare,
  541. .disable = vc5_clk_out_unprepare,
  542. .set_rate = vc5_clk_out_set_rate,
  543. .get_rate = vc5_clk_out_get_rate,
  544. };
  545. static const struct clk_ops vc5_clk_out_sel_ops = {
  546. .enable = vc5_clk_out_prepare,
  547. .disable = vc5_clk_out_unprepare,
  548. .get_rate = vc5_clk_out_get_rate,
  549. };
  550. static const struct clk_ops vc5_clk_ops = {
  551. .enable = vc5_clk_out_prepare,
  552. .disable = vc5_clk_out_unprepare,
  553. .of_xlate = vc5_clk_out_xlate,
  554. .set_rate = vc5_clk_out_set_rate,
  555. .get_rate = vc5_clk_out_get_rate,
  556. };
  557. static int vc5_map_index_to_output(const enum vc5_model model,
  558. const unsigned int n)
  559. {
  560. switch (model) {
  561. case IDT_VC5_5P49V5933:
  562. return (n == 0) ? 0 : 3;
  563. case IDT_VC5_5P49V5923:
  564. case IDT_VC5_5P49V5925:
  565. case IDT_VC5_5P49V5935:
  566. case IDT_VC6_5P49V6901:
  567. case IDT_VC6_5P49V6965:
  568. default:
  569. return n;
  570. }
  571. }
  572. static int vc5_update_mode(ofnode np_output,
  573. struct vc5_out_data *clk_out)
  574. {
  575. u32 value;
  576. if (!ofnode_read_u32(np_output, "idt,mode", &value)) {
  577. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_CFG_MASK;
  578. switch (value) {
  579. case VC5_CLK_OUTPUT_CFG0_CFG_LVPECL:
  580. case VC5_CLK_OUTPUT_CFG0_CFG_CMOS:
  581. case VC5_CLK_OUTPUT_CFG0_CFG_HCSL33:
  582. case VC5_CLK_OUTPUT_CFG0_CFG_LVDS:
  583. case VC5_CLK_OUTPUT_CFG0_CFG_CMOS2:
  584. case VC5_CLK_OUTPUT_CFG0_CFG_CMOSD:
  585. case VC5_CLK_OUTPUT_CFG0_CFG_HCSL25:
  586. clk_out->clk_output_cfg0 |=
  587. value << VC5_CLK_OUTPUT_CFG0_CFG_SHIFT;
  588. break;
  589. default:
  590. return -EINVAL;
  591. }
  592. }
  593. return 0;
  594. }
  595. static int vc5_update_power(ofnode np_output, struct vc5_out_data *clk_out)
  596. {
  597. u32 value;
  598. if (!ofnode_read_u32(np_output, "idt,voltage-microvolt", &value)) {
  599. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_PWR_MASK;
  600. switch (value) {
  601. case 1800000:
  602. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_18;
  603. break;
  604. case 2500000:
  605. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_25;
  606. break;
  607. case 3300000:
  608. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_PWR_33;
  609. break;
  610. default:
  611. return -EINVAL;
  612. }
  613. }
  614. return 0;
  615. }
  616. static int vc5_map_cap_value(u32 femtofarads)
  617. {
  618. int mapped_value;
  619. /*
  620. * The datasheet explicitly states 9000 - 25000 with 0.5pF
  621. * steps, but the Programmer's guide shows the steps are 0.430pF.
  622. * After getting feedback from Renesas, the .5pF steps were the
  623. * goal, but 430nF was the actual values.
  624. * Because of this, the actual range goes to 22760 instead of 25000
  625. */
  626. if (femtofarads < 9000 || femtofarads > 22760)
  627. return -EINVAL;
  628. /*
  629. * The Programmer's guide shows XTAL[5:0] but in reality,
  630. * XTAL[0] and XTAL[1] are both LSB which makes the math
  631. * strange. With clarfication from Renesas, setting the
  632. * values should be simpler by ignoring XTAL[0]
  633. */
  634. mapped_value = DIV_ROUND_CLOSEST(femtofarads - 9000, 430);
  635. /*
  636. * Since the calculation ignores XTAL[0], there is one
  637. * special case where mapped_value = 32. In reality, this means
  638. * the real mapped value should be 111111b. In other cases,
  639. * the mapped_value needs to be shifted 1 to the left.
  640. */
  641. if (mapped_value > 31)
  642. mapped_value = 0x3f;
  643. else
  644. mapped_value <<= 1;
  645. return mapped_value;
  646. }
  647. static int vc5_update_cap_load(ofnode node, struct vc5_driver_data *vc5)
  648. {
  649. u32 value;
  650. int mapped_value;
  651. if (!ofnode_read_u32(node, "idt,xtal-load-femtofarads", &value)) {
  652. mapped_value = vc5_map_cap_value(value);
  653. if (mapped_value < 0)
  654. return mapped_value;
  655. /*
  656. * The mapped_value is really the high 6 bits of
  657. * VC5_XTAL_X1_LOAD_CAP and VC5_XTAL_X2_LOAD_CAP, so
  658. * shift the value 2 places.
  659. */
  660. vc5_update_bits(vc5->i2c, VC5_XTAL_X1_LOAD_CAP, ~0x03, mapped_value << 2);
  661. vc5_update_bits(vc5->i2c, VC5_XTAL_X2_LOAD_CAP, ~0x03, mapped_value << 2);
  662. }
  663. return 0;
  664. }
  665. static int vc5_update_slew(ofnode np_output, struct vc5_out_data *clk_out)
  666. {
  667. u32 value;
  668. if (!ofnode_read_u32(np_output, "idt,slew-percent", &value)) {
  669. clk_out->clk_output_cfg0_mask |= VC5_CLK_OUTPUT_CFG0_SLEW_MASK;
  670. switch (value) {
  671. case 80:
  672. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_80;
  673. break;
  674. case 85:
  675. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_85;
  676. break;
  677. case 90:
  678. clk_out->clk_output_cfg0 |= VC5_CLK_OUTPUT_CFG0_SLEW_90;
  679. break;
  680. case 100:
  681. clk_out->clk_output_cfg0 |=
  682. VC5_CLK_OUTPUT_CFG0_SLEW_100;
  683. break;
  684. default:
  685. return -EINVAL;
  686. }
  687. }
  688. return 0;
  689. }
  690. static int vc5_get_output_config(struct udevice *dev,
  691. struct vc5_out_data *clk_out)
  692. {
  693. ofnode np_output;
  694. char child_name[5];
  695. int ret = 0;
  696. sprintf(child_name, "OUT%d", clk_out->num + 1);
  697. np_output = dev_read_subnode(dev, child_name);
  698. if (!ofnode_valid(np_output)) {
  699. dev_dbg(dev, "Invalid clock output configuration OUT%d\n",
  700. clk_out->num + 1);
  701. return 0;
  702. }
  703. ret = vc5_update_mode(np_output, clk_out);
  704. if (ret)
  705. return ret;
  706. ret = vc5_update_power(np_output, clk_out);
  707. if (ret)
  708. return ret;
  709. ret = vc5_update_slew(np_output, clk_out);
  710. return ret;
  711. }
  712. static char *versaclock_get_name(const char *dev_name, const char *clk_name, int index)
  713. {
  714. int length;
  715. char *buf;
  716. if (index < 0)
  717. length = snprintf(NULL, 0, "%s.%s", dev_name, clk_name) + 1;
  718. else
  719. length = snprintf(NULL, 0, "%s.%s%d", dev_name, clk_name, index) + 1;
  720. buf = malloc(length);
  721. if (!buf)
  722. ERR_PTR(-ENOMEM);
  723. if (index < 0)
  724. snprintf(buf, length, "%s.%s", dev_name, clk_name);
  725. else
  726. snprintf(buf, length, "%s.%s%d", dev_name, clk_name, index);
  727. return buf;
  728. }
  729. int versaclock_probe(struct udevice *dev)
  730. {
  731. struct vc5_driver_data *vc5 = dev_get_priv(dev);
  732. struct vc5_chip_info *chip = (void *)dev_get_driver_data(dev);
  733. unsigned int n, idx = 0;
  734. char *mux_name, *pfd_name, *pll_name, *outsel_name;
  735. char *out_name[VC5_MAX_CLK_OUT_NUM];
  736. char *fod_name[VC5_MAX_FOD_NUM];
  737. int ret;
  738. u64 val;
  739. val = (u64)dev_read_addr_ptr(dev);
  740. ret = i2c_get_chip(dev->parent, val, 1, &vc5->i2c);
  741. if (ret) {
  742. dev_dbg(dev, "I2C probe failed.\n");
  743. return ret;
  744. }
  745. vc5->chip_info = chip;
  746. vc5->pin_xin = devm_clk_get(dev, "xin");
  747. if (IS_ERR(vc5->pin_xin))
  748. dev_dbg(dev, "failed to get xin clock\n");
  749. ret = clk_enable(vc5->pin_xin);
  750. if (ret)
  751. dev_dbg(dev, "failed to enable XIN clock\n");
  752. vc5->pin_clkin = devm_clk_get(dev, "clkin");
  753. /* Register clock input mux */
  754. if (!IS_ERR(vc5->pin_xin)) {
  755. vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
  756. } else if (vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL) {
  757. if (IS_ERR(vc5->pin_xin))
  758. return PTR_ERR(vc5->pin_xin);
  759. vc5->clk_mux_ins |= VC5_MUX_IN_XIN;
  760. }
  761. mux_name = versaclock_get_name(dev->name, "mux", -1);
  762. if (IS_ERR(mux_name))
  763. return PTR_ERR(mux_name);
  764. clk_register(&vc5->clk_mux, "versaclock-mux", mux_name, vc5->pin_xin->dev->name);
  765. if (!IS_ERR(vc5->pin_xin))
  766. vc5_mux_set_parent(&vc5->clk_mux, 1);
  767. else
  768. vc5_mux_set_parent(&vc5->clk_mux, 0);
  769. /* Configure Optional Loading Capacitance for external XTAL */
  770. if (!(vc5->chip_info->flags & VC5_HAS_INTERNAL_XTAL)) {
  771. ret = vc5_update_cap_load(dev_ofnode(dev), vc5);
  772. if (ret)
  773. dev_dbg(dev, "failed to vc5_update_cap_load\n");
  774. }
  775. /* Register PFD */
  776. pfd_name = versaclock_get_name(dev->name, "pfd", -1);
  777. if (IS_ERR(pfd_name)) {
  778. ret = PTR_ERR(pfd_name);
  779. goto free_mux;
  780. }
  781. ret = clk_register(&vc5->clk_pfd, "versaclock-pfd", pfd_name, vc5->clk_mux.dev->name);
  782. if (ret)
  783. goto free_pfd;
  784. /* Register PLL */
  785. vc5->clk_pll.num = 0;
  786. vc5->clk_pll.vc5 = vc5;
  787. pll_name = versaclock_get_name(dev->name, "pll", -1);
  788. if (IS_ERR(pll_name)) {
  789. ret = PTR_ERR(pll_name);
  790. goto free_pfd;
  791. }
  792. ret = clk_register(&vc5->clk_pll.hw, "versaclock-pll", pll_name, vc5->clk_pfd.dev->name);
  793. if (ret)
  794. goto free_pll;
  795. /* Register FODs */
  796. for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
  797. fod_name[n] = versaclock_get_name(dev->name, "fod", n);
  798. if (IS_ERR(pll_name)) {
  799. ret = PTR_ERR(fod_name[n]);
  800. goto free_fod;
  801. }
  802. idx = vc5_map_index_to_output(vc5->chip_info->model, n);
  803. vc5->clk_fod[n].num = idx;
  804. vc5->clk_fod[n].vc5 = vc5;
  805. ret = clk_register(&vc5->clk_fod[n].hw, "versaclock-fod", fod_name[n],
  806. vc5->clk_pll.hw.dev->name);
  807. if (ret)
  808. goto free_fod;
  809. }
  810. /* Register MUX-connected OUT0_I2C_SELB output */
  811. vc5->clk_out[0].num = idx;
  812. vc5->clk_out[0].vc5 = vc5;
  813. outsel_name = versaclock_get_name(dev->name, "out0_sel_i2cb", -1);
  814. if (IS_ERR(outsel_name)) {
  815. ret = PTR_ERR(outsel_name);
  816. goto free_fod;
  817. };
  818. ret = clk_register(&vc5->clk_out[0].hw, "versaclock-outsel", outsel_name,
  819. vc5->clk_mux.dev->name);
  820. if (ret)
  821. goto free_selb;
  822. /* Register FOD-connected OUTx outputs */
  823. for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
  824. idx = vc5_map_index_to_output(vc5->chip_info->model, n - 1);
  825. out_name[n] = versaclock_get_name(dev->name, "out", n);
  826. if (IS_ERR(out_name[n])) {
  827. ret = PTR_ERR(out_name[n]);
  828. goto free_selb;
  829. }
  830. vc5->clk_out[n].num = idx;
  831. vc5->clk_out[n].vc5 = vc5;
  832. ret = clk_register(&vc5->clk_out[n].hw, "versaclock-out", out_name[n],
  833. vc5->clk_fod[idx].hw.dev->name);
  834. if (ret)
  835. goto free_out;
  836. vc5_clk_out_set_parent(vc5, idx, 0);
  837. /* Fetch Clock Output configuration from DT (if specified) */
  838. ret = vc5_get_output_config(dev, &vc5->clk_out[n]);
  839. if (ret) {
  840. dev_dbg(dev, "failed to vc5_get_output_config()\n");
  841. goto free_out;
  842. }
  843. }
  844. return 0;
  845. free_out:
  846. for (n = 1; n < vc5->chip_info->clk_out_cnt; n++) {
  847. clk_free(&vc5->clk_out[n].hw);
  848. free(out_name[n]);
  849. }
  850. free_selb:
  851. clk_free(&vc5->clk_out[0].hw);
  852. free(outsel_name);
  853. free_fod:
  854. for (n = 0; n < vc5->chip_info->clk_fod_cnt; n++) {
  855. clk_free(&vc5->clk_fod[n].hw);
  856. free(fod_name[n]);
  857. }
  858. free_pll:
  859. clk_free(&vc5->clk_pll.hw);
  860. free(pll_name);
  861. free_pfd:
  862. clk_free(&vc5->clk_pfd);
  863. free(pfd_name);
  864. free_mux:
  865. clk_free(&vc5->clk_mux);
  866. free(mux_name);
  867. return ret;
  868. }
  869. static const struct udevice_id versaclock_ids[] = {
  870. { .compatible = "idt,5p49v5923", .data = (ulong)&idt_5p49v5923_info },
  871. { .compatible = "idt,5p49v5925", .data = (ulong)&idt_5p49v5925_info },
  872. { .compatible = "idt,5p49v5933", .data = (ulong)&idt_5p49v5933_info },
  873. { .compatible = "idt,5p49v5935", .data = (ulong)&idt_5p49v5935_info },
  874. { .compatible = "idt,5p49v6901", .data = (ulong)&idt_5p49v6901_info },
  875. { .compatible = "idt,5p49v6965", .data = (ulong)&idt_5p49v6965_info },
  876. {},
  877. };
  878. U_BOOT_DRIVER(versaclock) = {
  879. .name = "versaclock",
  880. .id = UCLASS_CLK,
  881. .ops = &vc5_clk_ops,
  882. .of_match = versaclock_ids,
  883. .probe = versaclock_probe,
  884. .priv_auto = sizeof(struct vc5_driver_data),
  885. };
  886. U_BOOT_DRIVER(versaclock_mux) = {
  887. .name = "versaclock-mux",
  888. .id = UCLASS_CLK,
  889. .ops = &vc5_mux_ops,
  890. };
  891. U_BOOT_DRIVER(versaclock_pfd) = {
  892. .name = "versaclock-pfd",
  893. .id = UCLASS_CLK,
  894. .ops = &vc5_pfd_ops,
  895. };
  896. U_BOOT_DRIVER(versaclock_pll) = {
  897. .name = "versaclock-pll",
  898. .id = UCLASS_CLK,
  899. .ops = &vc5_pll_ops,
  900. };
  901. U_BOOT_DRIVER(versaclock_fod) = {
  902. .name = "versaclock-fod",
  903. .id = UCLASS_CLK,
  904. .ops = &vc5_fod_ops,
  905. };
  906. U_BOOT_DRIVER(versaclock_out) = {
  907. .name = "versaclock-out",
  908. .id = UCLASS_CLK,
  909. .ops = &vc5_clk_out_ops,
  910. };
  911. U_BOOT_DRIVER(versaclock_outsel) = {
  912. .name = "versaclock-outsel",
  913. .id = UCLASS_CLK,
  914. .ops = &vc5_clk_out_sel_ops,
  915. };