clk_stm32mp1.c 59 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #define LOG_CATEGORY UCLASS_CLK
  6. #include <common.h>
  7. #include <clk-uclass.h>
  8. #include <div64.h>
  9. #include <dm.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <regmap.h>
  13. #include <spl.h>
  14. #include <syscon.h>
  15. #include <time.h>
  16. #include <vsprintf.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/global_data.h>
  19. #include <dm/device_compat.h>
  20. #include <dt-bindings/clock/stm32mp1-clks.h>
  21. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  22. #include <linux/bitops.h>
  23. #include <linux/io.h>
  24. #include <linux/iopoll.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifndef CONFIG_TFABOOT
  27. #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
  28. /* activate clock tree initialization in the driver */
  29. #define STM32MP1_CLOCK_TREE_INIT
  30. #endif
  31. #endif
  32. #define MAX_HSI_HZ 64000000
  33. /* TIMEOUT */
  34. #define TIMEOUT_200MS 200000
  35. #define TIMEOUT_1S 1000000
  36. /* STGEN registers */
  37. #define STGENC_CNTCR 0x00
  38. #define STGENC_CNTSR 0x04
  39. #define STGENC_CNTCVL 0x08
  40. #define STGENC_CNTCVU 0x0C
  41. #define STGENC_CNTFID0 0x20
  42. #define STGENC_CNTCR_EN BIT(0)
  43. /* RCC registers */
  44. #define RCC_OCENSETR 0x0C
  45. #define RCC_OCENCLRR 0x10
  46. #define RCC_HSICFGR 0x18
  47. #define RCC_MPCKSELR 0x20
  48. #define RCC_ASSCKSELR 0x24
  49. #define RCC_RCK12SELR 0x28
  50. #define RCC_MPCKDIVR 0x2C
  51. #define RCC_AXIDIVR 0x30
  52. #define RCC_APB4DIVR 0x3C
  53. #define RCC_APB5DIVR 0x40
  54. #define RCC_RTCDIVR 0x44
  55. #define RCC_MSSCKSELR 0x48
  56. #define RCC_PLL1CR 0x80
  57. #define RCC_PLL1CFGR1 0x84
  58. #define RCC_PLL1CFGR2 0x88
  59. #define RCC_PLL1FRACR 0x8C
  60. #define RCC_PLL1CSGR 0x90
  61. #define RCC_PLL2CR 0x94
  62. #define RCC_PLL2CFGR1 0x98
  63. #define RCC_PLL2CFGR2 0x9C
  64. #define RCC_PLL2FRACR 0xA0
  65. #define RCC_PLL2CSGR 0xA4
  66. #define RCC_I2C46CKSELR 0xC0
  67. #define RCC_SPI6CKSELR 0xC4
  68. #define RCC_CPERCKSELR 0xD0
  69. #define RCC_STGENCKSELR 0xD4
  70. #define RCC_DDRITFCR 0xD8
  71. #define RCC_BDCR 0x140
  72. #define RCC_RDLSICR 0x144
  73. #define RCC_MP_APB4ENSETR 0x200
  74. #define RCC_MP_APB5ENSETR 0x208
  75. #define RCC_MP_AHB5ENSETR 0x210
  76. #define RCC_MP_AHB6ENSETR 0x218
  77. #define RCC_OCRDYR 0x808
  78. #define RCC_DBGCFGR 0x80C
  79. #define RCC_RCK3SELR 0x820
  80. #define RCC_RCK4SELR 0x824
  81. #define RCC_MCUDIVR 0x830
  82. #define RCC_APB1DIVR 0x834
  83. #define RCC_APB2DIVR 0x838
  84. #define RCC_APB3DIVR 0x83C
  85. #define RCC_PLL3CR 0x880
  86. #define RCC_PLL3CFGR1 0x884
  87. #define RCC_PLL3CFGR2 0x888
  88. #define RCC_PLL3FRACR 0x88C
  89. #define RCC_PLL3CSGR 0x890
  90. #define RCC_PLL4CR 0x894
  91. #define RCC_PLL4CFGR1 0x898
  92. #define RCC_PLL4CFGR2 0x89C
  93. #define RCC_PLL4FRACR 0x8A0
  94. #define RCC_PLL4CSGR 0x8A4
  95. #define RCC_I2C12CKSELR 0x8C0
  96. #define RCC_I2C35CKSELR 0x8C4
  97. #define RCC_SPI2S1CKSELR 0x8D8
  98. #define RCC_SPI2S23CKSELR 0x8DC
  99. #define RCC_SPI45CKSELR 0x8E0
  100. #define RCC_UART6CKSELR 0x8E4
  101. #define RCC_UART24CKSELR 0x8E8
  102. #define RCC_UART35CKSELR 0x8EC
  103. #define RCC_UART78CKSELR 0x8F0
  104. #define RCC_SDMMC12CKSELR 0x8F4
  105. #define RCC_SDMMC3CKSELR 0x8F8
  106. #define RCC_ETHCKSELR 0x8FC
  107. #define RCC_QSPICKSELR 0x900
  108. #define RCC_FMCCKSELR 0x904
  109. #define RCC_USBCKSELR 0x91C
  110. #define RCC_DSICKSELR 0x924
  111. #define RCC_ADCCKSELR 0x928
  112. #define RCC_MP_APB1ENSETR 0xA00
  113. #define RCC_MP_APB2ENSETR 0XA08
  114. #define RCC_MP_APB3ENSETR 0xA10
  115. #define RCC_MP_AHB2ENSETR 0xA18
  116. #define RCC_MP_AHB3ENSETR 0xA20
  117. #define RCC_MP_AHB4ENSETR 0xA28
  118. /* used for most of SELR register */
  119. #define RCC_SELR_SRC_MASK GENMASK(2, 0)
  120. #define RCC_SELR_SRCRDY BIT(31)
  121. /* Values of RCC_MPCKSELR register */
  122. #define RCC_MPCKSELR_HSI 0
  123. #define RCC_MPCKSELR_HSE 1
  124. #define RCC_MPCKSELR_PLL 2
  125. #define RCC_MPCKSELR_PLL_MPUDIV 3
  126. /* Values of RCC_ASSCKSELR register */
  127. #define RCC_ASSCKSELR_HSI 0
  128. #define RCC_ASSCKSELR_HSE 1
  129. #define RCC_ASSCKSELR_PLL 2
  130. /* Values of RCC_MSSCKSELR register */
  131. #define RCC_MSSCKSELR_HSI 0
  132. #define RCC_MSSCKSELR_HSE 1
  133. #define RCC_MSSCKSELR_CSI 2
  134. #define RCC_MSSCKSELR_PLL 3
  135. /* Values of RCC_CPERCKSELR register */
  136. #define RCC_CPERCKSELR_HSI 0
  137. #define RCC_CPERCKSELR_CSI 1
  138. #define RCC_CPERCKSELR_HSE 2
  139. /* used for most of DIVR register : max div for RTC */
  140. #define RCC_DIVR_DIV_MASK GENMASK(5, 0)
  141. #define RCC_DIVR_DIVRDY BIT(31)
  142. /* Masks for specific DIVR registers */
  143. #define RCC_APBXDIV_MASK GENMASK(2, 0)
  144. #define RCC_MPUDIV_MASK GENMASK(2, 0)
  145. #define RCC_AXIDIV_MASK GENMASK(2, 0)
  146. #define RCC_MCUDIV_MASK GENMASK(3, 0)
  147. /* offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
  148. #define RCC_MP_ENCLRR_OFFSET 4
  149. /* Fields of RCC_BDCR register */
  150. #define RCC_BDCR_LSEON BIT(0)
  151. #define RCC_BDCR_LSEBYP BIT(1)
  152. #define RCC_BDCR_LSERDY BIT(2)
  153. #define RCC_BDCR_DIGBYP BIT(3)
  154. #define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4)
  155. #define RCC_BDCR_LSEDRV_SHIFT 4
  156. #define RCC_BDCR_LSECSSON BIT(8)
  157. #define RCC_BDCR_RTCCKEN BIT(20)
  158. #define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16)
  159. #define RCC_BDCR_RTCSRC_SHIFT 16
  160. /* Fields of RCC_RDLSICR register */
  161. #define RCC_RDLSICR_LSION BIT(0)
  162. #define RCC_RDLSICR_LSIRDY BIT(1)
  163. /* used for ALL PLLNCR registers */
  164. #define RCC_PLLNCR_PLLON BIT(0)
  165. #define RCC_PLLNCR_PLLRDY BIT(1)
  166. #define RCC_PLLNCR_SSCG_CTRL BIT(2)
  167. #define RCC_PLLNCR_DIVPEN BIT(4)
  168. #define RCC_PLLNCR_DIVQEN BIT(5)
  169. #define RCC_PLLNCR_DIVREN BIT(6)
  170. #define RCC_PLLNCR_DIVEN_SHIFT 4
  171. /* used for ALL PLLNCFGR1 registers */
  172. #define RCC_PLLNCFGR1_DIVM_SHIFT 16
  173. #define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16)
  174. #define RCC_PLLNCFGR1_DIVN_SHIFT 0
  175. #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0)
  176. /* only for PLL3 and PLL4 */
  177. #define RCC_PLLNCFGR1_IFRGE_SHIFT 24
  178. #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24)
  179. /* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */
  180. #define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8)
  181. #define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0)
  182. #define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P)
  183. #define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0)
  184. #define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q)
  185. #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8)
  186. #define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R)
  187. #define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16)
  188. /* used for ALL PLLNFRACR registers */
  189. #define RCC_PLLNFRACR_FRACV_SHIFT 3
  190. #define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3)
  191. #define RCC_PLLNFRACR_FRACLE BIT(16)
  192. /* used for ALL PLLNCSGR registers */
  193. #define RCC_PLLNCSGR_INC_STEP_SHIFT 16
  194. #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16)
  195. #define RCC_PLLNCSGR_MOD_PER_SHIFT 0
  196. #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0)
  197. #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15
  198. #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15)
  199. /* used for RCC_OCENSETR and RCC_OCENCLRR registers */
  200. #define RCC_OCENR_HSION BIT(0)
  201. #define RCC_OCENR_CSION BIT(4)
  202. #define RCC_OCENR_DIGBYP BIT(7)
  203. #define RCC_OCENR_HSEON BIT(8)
  204. #define RCC_OCENR_HSEBYP BIT(10)
  205. #define RCC_OCENR_HSECSSON BIT(11)
  206. /* Fields of RCC_OCRDYR register */
  207. #define RCC_OCRDYR_HSIRDY BIT(0)
  208. #define RCC_OCRDYR_HSIDIVRDY BIT(2)
  209. #define RCC_OCRDYR_CSIRDY BIT(4)
  210. #define RCC_OCRDYR_HSERDY BIT(8)
  211. /* Fields of DDRITFCR register */
  212. #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20)
  213. #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20
  214. #define RCC_DDRITFCR_DDRCKMOD_SSR 0
  215. /* Fields of RCC_HSICFGR register */
  216. #define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0)
  217. /* used for MCO related operations */
  218. #define RCC_MCOCFG_MCOON BIT(12)
  219. #define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4)
  220. #define RCC_MCOCFG_MCODIV_SHIFT 4
  221. #define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0)
  222. enum stm32mp1_parent_id {
  223. /*
  224. * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved
  225. * they are used as index in osc_clk[] as clock reference
  226. */
  227. _HSI,
  228. _HSE,
  229. _CSI,
  230. _LSI,
  231. _LSE,
  232. _I2S_CKIN,
  233. NB_OSC,
  234. /* other parent source */
  235. _HSI_KER = NB_OSC,
  236. _HSE_KER,
  237. _HSE_KER_DIV2,
  238. _CSI_KER,
  239. _PLL1_P,
  240. _PLL1_Q,
  241. _PLL1_R,
  242. _PLL2_P,
  243. _PLL2_Q,
  244. _PLL2_R,
  245. _PLL3_P,
  246. _PLL3_Q,
  247. _PLL3_R,
  248. _PLL4_P,
  249. _PLL4_Q,
  250. _PLL4_R,
  251. _ACLK,
  252. _PCLK1,
  253. _PCLK2,
  254. _PCLK3,
  255. _PCLK4,
  256. _PCLK5,
  257. _HCLK6,
  258. _HCLK2,
  259. _CK_PER,
  260. _CK_MPU,
  261. _CK_MCU,
  262. _DSI_PHY,
  263. _USB_PHY_48,
  264. _PARENT_NB,
  265. _UNKNOWN_ID = 0xff,
  266. };
  267. enum stm32mp1_parent_sel {
  268. _I2C12_SEL,
  269. _I2C35_SEL,
  270. _I2C46_SEL,
  271. _UART6_SEL,
  272. _UART24_SEL,
  273. _UART35_SEL,
  274. _UART78_SEL,
  275. _SDMMC12_SEL,
  276. _SDMMC3_SEL,
  277. _ETH_SEL,
  278. _QSPI_SEL,
  279. _FMC_SEL,
  280. _USBPHY_SEL,
  281. _USBO_SEL,
  282. _STGEN_SEL,
  283. _DSI_SEL,
  284. _ADC12_SEL,
  285. _SPI1_SEL,
  286. _SPI23_SEL,
  287. _SPI45_SEL,
  288. _SPI6_SEL,
  289. _RTC_SEL,
  290. _PARENT_SEL_NB,
  291. _UNKNOWN_SEL = 0xff,
  292. };
  293. enum stm32mp1_pll_id {
  294. _PLL1,
  295. _PLL2,
  296. _PLL3,
  297. _PLL4,
  298. _PLL_NB
  299. };
  300. enum stm32mp1_div_id {
  301. _DIV_P,
  302. _DIV_Q,
  303. _DIV_R,
  304. _DIV_NB,
  305. };
  306. enum stm32mp1_clksrc_id {
  307. CLKSRC_MPU,
  308. CLKSRC_AXI,
  309. CLKSRC_MCU,
  310. CLKSRC_PLL12,
  311. CLKSRC_PLL3,
  312. CLKSRC_PLL4,
  313. CLKSRC_RTC,
  314. CLKSRC_MCO1,
  315. CLKSRC_MCO2,
  316. CLKSRC_NB
  317. };
  318. enum stm32mp1_clkdiv_id {
  319. CLKDIV_MPU,
  320. CLKDIV_AXI,
  321. CLKDIV_MCU,
  322. CLKDIV_APB1,
  323. CLKDIV_APB2,
  324. CLKDIV_APB3,
  325. CLKDIV_APB4,
  326. CLKDIV_APB5,
  327. CLKDIV_RTC,
  328. CLKDIV_MCO1,
  329. CLKDIV_MCO2,
  330. CLKDIV_NB
  331. };
  332. enum stm32mp1_pllcfg {
  333. PLLCFG_M,
  334. PLLCFG_N,
  335. PLLCFG_P,
  336. PLLCFG_Q,
  337. PLLCFG_R,
  338. PLLCFG_O,
  339. PLLCFG_NB
  340. };
  341. enum stm32mp1_pllcsg {
  342. PLLCSG_MOD_PER,
  343. PLLCSG_INC_STEP,
  344. PLLCSG_SSCG_MODE,
  345. PLLCSG_NB
  346. };
  347. enum stm32mp1_plltype {
  348. PLL_800,
  349. PLL_1600,
  350. PLL_TYPE_NB
  351. };
  352. struct stm32mp1_pll {
  353. u8 refclk_min;
  354. u8 refclk_max;
  355. u8 divn_max;
  356. };
  357. struct stm32mp1_clk_gate {
  358. u16 offset;
  359. u8 bit;
  360. u8 index;
  361. u8 set_clr;
  362. u8 sel;
  363. u8 fixed;
  364. };
  365. struct stm32mp1_clk_sel {
  366. u16 offset;
  367. u8 src;
  368. u8 msk;
  369. u8 nb_parent;
  370. const u8 *parent;
  371. };
  372. #define REFCLK_SIZE 4
  373. struct stm32mp1_clk_pll {
  374. enum stm32mp1_plltype plltype;
  375. u16 rckxselr;
  376. u16 pllxcfgr1;
  377. u16 pllxcfgr2;
  378. u16 pllxfracr;
  379. u16 pllxcr;
  380. u16 pllxcsgr;
  381. u8 refclk[REFCLK_SIZE];
  382. };
  383. struct stm32mp1_clk_data {
  384. const struct stm32mp1_clk_gate *gate;
  385. const struct stm32mp1_clk_sel *sel;
  386. const struct stm32mp1_clk_pll *pll;
  387. const int nb_gate;
  388. };
  389. struct stm32mp1_clk_priv {
  390. fdt_addr_t base;
  391. const struct stm32mp1_clk_data *data;
  392. struct clk osc_clk[NB_OSC];
  393. };
  394. #define STM32MP1_CLK(off, b, idx, s) \
  395. { \
  396. .offset = (off), \
  397. .bit = (b), \
  398. .index = (idx), \
  399. .set_clr = 0, \
  400. .sel = (s), \
  401. .fixed = _UNKNOWN_ID, \
  402. }
  403. #define STM32MP1_CLK_F(off, b, idx, f) \
  404. { \
  405. .offset = (off), \
  406. .bit = (b), \
  407. .index = (idx), \
  408. .set_clr = 0, \
  409. .sel = _UNKNOWN_SEL, \
  410. .fixed = (f), \
  411. }
  412. #define STM32MP1_CLK_SET_CLR(off, b, idx, s) \
  413. { \
  414. .offset = (off), \
  415. .bit = (b), \
  416. .index = (idx), \
  417. .set_clr = 1, \
  418. .sel = (s), \
  419. .fixed = _UNKNOWN_ID, \
  420. }
  421. #define STM32MP1_CLK_SET_CLR_F(off, b, idx, f) \
  422. { \
  423. .offset = (off), \
  424. .bit = (b), \
  425. .index = (idx), \
  426. .set_clr = 1, \
  427. .sel = _UNKNOWN_SEL, \
  428. .fixed = (f), \
  429. }
  430. #define STM32MP1_CLK_PARENT(idx, off, s, m, p) \
  431. [(idx)] = { \
  432. .offset = (off), \
  433. .src = (s), \
  434. .msk = (m), \
  435. .parent = (p), \
  436. .nb_parent = ARRAY_SIZE((p)) \
  437. }
  438. #define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\
  439. p1, p2, p3, p4) \
  440. [(idx)] = { \
  441. .plltype = (type), \
  442. .rckxselr = (off1), \
  443. .pllxcfgr1 = (off2), \
  444. .pllxcfgr2 = (off3), \
  445. .pllxfracr = (off4), \
  446. .pllxcr = (off5), \
  447. .pllxcsgr = (off6), \
  448. .refclk[0] = (p1), \
  449. .refclk[1] = (p2), \
  450. .refclk[2] = (p3), \
  451. .refclk[3] = (p4), \
  452. }
  453. static const u8 stm32mp1_clks[][2] = {
  454. {CK_PER, _CK_PER},
  455. {CK_MPU, _CK_MPU},
  456. {CK_AXI, _ACLK},
  457. {CK_MCU, _CK_MCU},
  458. {CK_HSE, _HSE},
  459. {CK_CSI, _CSI},
  460. {CK_LSI, _LSI},
  461. {CK_LSE, _LSE},
  462. {CK_HSI, _HSI},
  463. {CK_HSE_DIV2, _HSE_KER_DIV2},
  464. };
  465. static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
  466. STM32MP1_CLK(RCC_DDRITFCR, 0, DDRC1, _UNKNOWN_SEL),
  467. STM32MP1_CLK(RCC_DDRITFCR, 1, DDRC1LP, _UNKNOWN_SEL),
  468. STM32MP1_CLK(RCC_DDRITFCR, 2, DDRC2, _UNKNOWN_SEL),
  469. STM32MP1_CLK(RCC_DDRITFCR, 3, DDRC2LP, _UNKNOWN_SEL),
  470. STM32MP1_CLK_F(RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
  471. STM32MP1_CLK(RCC_DDRITFCR, 5, DDRPHYCLP, _UNKNOWN_SEL),
  472. STM32MP1_CLK(RCC_DDRITFCR, 6, DDRCAPB, _UNKNOWN_SEL),
  473. STM32MP1_CLK(RCC_DDRITFCR, 7, DDRCAPBLP, _UNKNOWN_SEL),
  474. STM32MP1_CLK(RCC_DDRITFCR, 8, AXIDCG, _UNKNOWN_SEL),
  475. STM32MP1_CLK(RCC_DDRITFCR, 9, DDRPHYCAPB, _UNKNOWN_SEL),
  476. STM32MP1_CLK(RCC_DDRITFCR, 10, DDRPHYCAPBLP, _UNKNOWN_SEL),
  477. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 11, SPI2_K, _SPI23_SEL),
  478. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 12, SPI3_K, _SPI23_SEL),
  479. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL),
  480. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL),
  481. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL),
  482. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL),
  483. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL),
  484. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL),
  485. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL),
  486. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL),
  487. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL),
  488. STM32MP1_CLK_SET_CLR(RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL),
  489. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 8, SPI1_K, _SPI1_SEL),
  490. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 9, SPI4_K, _SPI45_SEL),
  491. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 10, SPI5_K, _SPI45_SEL),
  492. STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
  493. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
  494. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_SEL),
  495. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 0, LTDC_PX, _PLL4_Q),
  496. STM32MP1_CLK_SET_CLR_F(RCC_MP_APB4ENSETR, 4, DSI_PX, _PLL4_Q),
  497. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 4, DSI_K, _DSI_SEL),
  498. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
  499. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
  500. STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),
  501. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL),
  502. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL),
  503. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL),
  504. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5),
  505. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 16, BSEC, _UNKNOWN_SEL),
  506. STM32MP1_CLK_SET_CLR(RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL),
  507. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB2ENSETR, 5, ADC12, _HCLK2),
  508. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 5, ADC12_K, _ADC12_SEL),
  509. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
  510. STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
  511. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
  512. STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL),
  513. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
  514. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
  515. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
  516. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL),
  517. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL),
  518. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL),
  519. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL),
  520. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL),
  521. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL),
  522. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL),
  523. STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
  524. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
  525. STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
  526. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
  527. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),
  528. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 9, ETHRX, _UNKNOWN_SEL),
  529. STM32MP1_CLK_SET_CLR_F(RCC_MP_AHB6ENSETR, 10, ETHMAC, _ACLK),
  530. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL),
  531. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL),
  532. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL),
  533. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL),
  534. STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL),
  535. STM32MP1_CLK(RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL),
  536. STM32MP1_CLK(RCC_BDCR, 20, RTC, _RTC_SEL),
  537. };
  538. static const u8 i2c12_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  539. static const u8 i2c35_parents[] = {_PCLK1, _PLL4_R, _HSI_KER, _CSI_KER};
  540. static const u8 i2c46_parents[] = {_PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER};
  541. static const u8 uart6_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  542. _HSE_KER};
  543. static const u8 uart24_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  544. _HSE_KER};
  545. static const u8 uart35_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  546. _HSE_KER};
  547. static const u8 uart78_parents[] = {_PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER,
  548. _HSE_KER};
  549. static const u8 sdmmc12_parents[] = {_HCLK6, _PLL3_R, _PLL4_P, _HSI_KER};
  550. static const u8 sdmmc3_parents[] = {_HCLK2, _PLL3_R, _PLL4_P, _HSI_KER};
  551. static const u8 eth_parents[] = {_PLL4_P, _PLL3_Q};
  552. static const u8 qspi_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  553. static const u8 fmc_parents[] = {_ACLK, _PLL3_R, _PLL4_P, _CK_PER};
  554. static const u8 usbphy_parents[] = {_HSE_KER, _PLL4_R, _HSE_KER_DIV2};
  555. static const u8 usbo_parents[] = {_PLL4_R, _USB_PHY_48};
  556. static const u8 stgen_parents[] = {_HSI_KER, _HSE_KER};
  557. static const u8 dsi_parents[] = {_DSI_PHY, _PLL4_P};
  558. static const u8 adc_parents[] = {_PLL4_R, _CK_PER, _PLL3_Q};
  559. /* same parents for SPI1=RCC_SPI2S1CKSELR and SPI2&3 = RCC_SPI2S23CKSELR */
  560. static const u8 spi_parents[] = {_PLL4_P, _PLL3_Q, _I2S_CKIN, _CK_PER,
  561. _PLL3_R};
  562. static const u8 spi45_parents[] = {_PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER,
  563. _HSE_KER};
  564. static const u8 spi6_parents[] = {_PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER,
  565. _HSE_KER, _PLL3_Q};
  566. static const u8 rtc_parents[] = {_UNKNOWN_ID, _LSE, _LSI, _HSE};
  567. static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = {
  568. STM32MP1_CLK_PARENT(_I2C12_SEL, RCC_I2C12CKSELR, 0, 0x7, i2c12_parents),
  569. STM32MP1_CLK_PARENT(_I2C35_SEL, RCC_I2C35CKSELR, 0, 0x7, i2c35_parents),
  570. STM32MP1_CLK_PARENT(_I2C46_SEL, RCC_I2C46CKSELR, 0, 0x7, i2c46_parents),
  571. STM32MP1_CLK_PARENT(_UART6_SEL, RCC_UART6CKSELR, 0, 0x7, uart6_parents),
  572. STM32MP1_CLK_PARENT(_UART24_SEL, RCC_UART24CKSELR, 0, 0x7,
  573. uart24_parents),
  574. STM32MP1_CLK_PARENT(_UART35_SEL, RCC_UART35CKSELR, 0, 0x7,
  575. uart35_parents),
  576. STM32MP1_CLK_PARENT(_UART78_SEL, RCC_UART78CKSELR, 0, 0x7,
  577. uart78_parents),
  578. STM32MP1_CLK_PARENT(_SDMMC12_SEL, RCC_SDMMC12CKSELR, 0, 0x7,
  579. sdmmc12_parents),
  580. STM32MP1_CLK_PARENT(_SDMMC3_SEL, RCC_SDMMC3CKSELR, 0, 0x7,
  581. sdmmc3_parents),
  582. STM32MP1_CLK_PARENT(_ETH_SEL, RCC_ETHCKSELR, 0, 0x3, eth_parents),
  583. STM32MP1_CLK_PARENT(_QSPI_SEL, RCC_QSPICKSELR, 0, 0x3, qspi_parents),
  584. STM32MP1_CLK_PARENT(_FMC_SEL, RCC_FMCCKSELR, 0, 0x3, fmc_parents),
  585. STM32MP1_CLK_PARENT(_USBPHY_SEL, RCC_USBCKSELR, 0, 0x3, usbphy_parents),
  586. STM32MP1_CLK_PARENT(_USBO_SEL, RCC_USBCKSELR, 4, 0x1, usbo_parents),
  587. STM32MP1_CLK_PARENT(_STGEN_SEL, RCC_STGENCKSELR, 0, 0x3, stgen_parents),
  588. STM32MP1_CLK_PARENT(_DSI_SEL, RCC_DSICKSELR, 0, 0x1, dsi_parents),
  589. STM32MP1_CLK_PARENT(_ADC12_SEL, RCC_ADCCKSELR, 0, 0x3, adc_parents),
  590. STM32MP1_CLK_PARENT(_SPI1_SEL, RCC_SPI2S1CKSELR, 0, 0x7, spi_parents),
  591. STM32MP1_CLK_PARENT(_SPI23_SEL, RCC_SPI2S23CKSELR, 0, 0x7, spi_parents),
  592. STM32MP1_CLK_PARENT(_SPI45_SEL, RCC_SPI45CKSELR, 0, 0x7, spi45_parents),
  593. STM32MP1_CLK_PARENT(_SPI6_SEL, RCC_SPI6CKSELR, 0, 0x7, spi6_parents),
  594. STM32MP1_CLK_PARENT(_RTC_SEL, RCC_BDCR, RCC_BDCR_RTCSRC_SHIFT,
  595. (RCC_BDCR_RTCSRC_MASK >> RCC_BDCR_RTCSRC_SHIFT),
  596. rtc_parents),
  597. };
  598. #ifdef STM32MP1_CLOCK_TREE_INIT
  599. /* define characteristic of PLL according type */
  600. #define DIVM_MIN 0
  601. #define DIVM_MAX 63
  602. #define DIVN_MIN 24
  603. #define DIVP_MIN 0
  604. #define DIVP_MAX 127
  605. #define FRAC_MAX 8192
  606. #define PLL1600_VCO_MIN 800000000
  607. #define PLL1600_VCO_MAX 1600000000
  608. static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
  609. [PLL_800] = {
  610. .refclk_min = 4,
  611. .refclk_max = 16,
  612. .divn_max = 99,
  613. },
  614. [PLL_1600] = {
  615. .refclk_min = 8,
  616. .refclk_max = 16,
  617. .divn_max = 199,
  618. },
  619. };
  620. #endif /* STM32MP1_CLOCK_TREE_INIT */
  621. static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = {
  622. STM32MP1_CLK_PLL(_PLL1, PLL_1600,
  623. RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2,
  624. RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR,
  625. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  626. STM32MP1_CLK_PLL(_PLL2, PLL_1600,
  627. RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2,
  628. RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR,
  629. _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID),
  630. STM32MP1_CLK_PLL(_PLL3, PLL_800,
  631. RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2,
  632. RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR,
  633. _HSI, _HSE, _CSI, _UNKNOWN_ID),
  634. STM32MP1_CLK_PLL(_PLL4, PLL_800,
  635. RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2,
  636. RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR,
  637. _HSI, _HSE, _CSI, _I2S_CKIN),
  638. };
  639. /* Prescaler table lookups for clock computation */
  640. /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */
  641. static const u8 stm32mp1_mcu_div[16] = {
  642. 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9
  643. };
  644. /* div = /1 /2 /4 /8 /16 : same divider for pmu and apbx*/
  645. #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div
  646. #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div
  647. static const u8 stm32mp1_mpu_apbx_div[8] = {
  648. 0, 1, 2, 3, 4, 4, 4, 4
  649. };
  650. /* div = /1 /2 /3 /4 */
  651. static const u8 stm32mp1_axi_div[8] = {
  652. 1, 2, 3, 4, 4, 4, 4, 4
  653. };
  654. static const __maybe_unused
  655. char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
  656. [_HSI] = "HSI",
  657. [_HSE] = "HSE",
  658. [_CSI] = "CSI",
  659. [_LSI] = "LSI",
  660. [_LSE] = "LSE",
  661. [_I2S_CKIN] = "I2S_CKIN",
  662. [_HSI_KER] = "HSI_KER",
  663. [_HSE_KER] = "HSE_KER",
  664. [_HSE_KER_DIV2] = "HSE_KER_DIV2",
  665. [_CSI_KER] = "CSI_KER",
  666. [_PLL1_P] = "PLL1_P",
  667. [_PLL1_Q] = "PLL1_Q",
  668. [_PLL1_R] = "PLL1_R",
  669. [_PLL2_P] = "PLL2_P",
  670. [_PLL2_Q] = "PLL2_Q",
  671. [_PLL2_R] = "PLL2_R",
  672. [_PLL3_P] = "PLL3_P",
  673. [_PLL3_Q] = "PLL3_Q",
  674. [_PLL3_R] = "PLL3_R",
  675. [_PLL4_P] = "PLL4_P",
  676. [_PLL4_Q] = "PLL4_Q",
  677. [_PLL4_R] = "PLL4_R",
  678. [_ACLK] = "ACLK",
  679. [_PCLK1] = "PCLK1",
  680. [_PCLK2] = "PCLK2",
  681. [_PCLK3] = "PCLK3",
  682. [_PCLK4] = "PCLK4",
  683. [_PCLK5] = "PCLK5",
  684. [_HCLK6] = "KCLK6",
  685. [_HCLK2] = "HCLK2",
  686. [_CK_PER] = "CK_PER",
  687. [_CK_MPU] = "CK_MPU",
  688. [_CK_MCU] = "CK_MCU",
  689. [_USB_PHY_48] = "USB_PHY_48",
  690. [_DSI_PHY] = "DSI_PHY_PLL",
  691. };
  692. static const __maybe_unused
  693. char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
  694. [_I2C12_SEL] = "I2C12",
  695. [_I2C35_SEL] = "I2C35",
  696. [_I2C46_SEL] = "I2C46",
  697. [_UART6_SEL] = "UART6",
  698. [_UART24_SEL] = "UART24",
  699. [_UART35_SEL] = "UART35",
  700. [_UART78_SEL] = "UART78",
  701. [_SDMMC12_SEL] = "SDMMC12",
  702. [_SDMMC3_SEL] = "SDMMC3",
  703. [_ETH_SEL] = "ETH",
  704. [_QSPI_SEL] = "QSPI",
  705. [_FMC_SEL] = "FMC",
  706. [_USBPHY_SEL] = "USBPHY",
  707. [_USBO_SEL] = "USBO",
  708. [_STGEN_SEL] = "STGEN",
  709. [_DSI_SEL] = "DSI",
  710. [_ADC12_SEL] = "ADC12",
  711. [_SPI1_SEL] = "SPI1",
  712. [_SPI45_SEL] = "SPI45",
  713. [_RTC_SEL] = "RTC",
  714. };
  715. static const struct stm32mp1_clk_data stm32mp1_data = {
  716. .gate = stm32mp1_clk_gate,
  717. .sel = stm32mp1_clk_sel,
  718. .pll = stm32mp1_clk_pll,
  719. .nb_gate = ARRAY_SIZE(stm32mp1_clk_gate),
  720. };
  721. static ulong stm32mp1_clk_get_fixed(struct stm32mp1_clk_priv *priv, int idx)
  722. {
  723. if (idx >= NB_OSC) {
  724. log_debug("clk id %d not found\n", idx);
  725. return 0;
  726. }
  727. return clk_get_rate(&priv->osc_clk[idx]);
  728. }
  729. static int stm32mp1_clk_get_id(struct stm32mp1_clk_priv *priv, unsigned long id)
  730. {
  731. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  732. int i, nb_clks = priv->data->nb_gate;
  733. for (i = 0; i < nb_clks; i++) {
  734. if (gate[i].index == id)
  735. break;
  736. }
  737. if (i == nb_clks) {
  738. log_err("clk id %d not found\n", (u32)id);
  739. return -EINVAL;
  740. }
  741. return i;
  742. }
  743. static int stm32mp1_clk_get_sel(struct stm32mp1_clk_priv *priv,
  744. int i)
  745. {
  746. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  747. if (gate[i].sel > _PARENT_SEL_NB) {
  748. log_err("parents for clk id %d not found\n", i);
  749. return -EINVAL;
  750. }
  751. return gate[i].sel;
  752. }
  753. static int stm32mp1_clk_get_fixed_parent(struct stm32mp1_clk_priv *priv,
  754. int i)
  755. {
  756. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  757. if (gate[i].fixed == _UNKNOWN_ID)
  758. return -ENOENT;
  759. return gate[i].fixed;
  760. }
  761. static int stm32mp1_clk_get_parent(struct stm32mp1_clk_priv *priv,
  762. unsigned long id)
  763. {
  764. const struct stm32mp1_clk_sel *sel = priv->data->sel;
  765. int i;
  766. int s, p;
  767. unsigned int idx;
  768. for (idx = 0; idx < ARRAY_SIZE(stm32mp1_clks); idx++)
  769. if (stm32mp1_clks[idx][0] == id)
  770. return stm32mp1_clks[idx][1];
  771. i = stm32mp1_clk_get_id(priv, id);
  772. if (i < 0)
  773. return i;
  774. p = stm32mp1_clk_get_fixed_parent(priv, i);
  775. if (p >= 0 && p < _PARENT_NB)
  776. return p;
  777. s = stm32mp1_clk_get_sel(priv, i);
  778. if (s < 0)
  779. return s;
  780. p = (readl(priv->base + sel[s].offset) >> sel[s].src) & sel[s].msk;
  781. if (p < sel[s].nb_parent) {
  782. log_content("%s clock is the parent %s of clk id %d\n",
  783. stm32mp1_clk_parent_name[sel[s].parent[p]],
  784. stm32mp1_clk_parent_sel_name[s],
  785. (u32)id);
  786. return sel[s].parent[p];
  787. }
  788. log_err("no parents defined for clk id %d\n", (u32)id);
  789. return -EINVAL;
  790. }
  791. static ulong pll_get_fref_ck(struct stm32mp1_clk_priv *priv,
  792. int pll_id)
  793. {
  794. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  795. u32 selr;
  796. int src;
  797. ulong refclk;
  798. /* Get current refclk */
  799. selr = readl(priv->base + pll[pll_id].rckxselr);
  800. src = selr & RCC_SELR_SRC_MASK;
  801. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]);
  802. return refclk;
  803. }
  804. /*
  805. * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL
  806. * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1)
  807. * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1)
  808. * => in all the case Fpll_y_ck = pll_get_fvco() / (DIVy + 1)
  809. */
  810. static ulong pll_get_fvco(struct stm32mp1_clk_priv *priv,
  811. int pll_id)
  812. {
  813. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  814. int divm, divn;
  815. ulong refclk, fvco;
  816. u32 cfgr1, fracr;
  817. cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1);
  818. fracr = readl(priv->base + pll[pll_id].pllxfracr);
  819. divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT;
  820. divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK;
  821. refclk = pll_get_fref_ck(priv, pll_id);
  822. /* with FRACV :
  823. * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1)
  824. * without FRACV
  825. * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1)
  826. */
  827. if (fracr & RCC_PLLNFRACR_FRACLE) {
  828. u32 fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK)
  829. >> RCC_PLLNFRACR_FRACV_SHIFT;
  830. fvco = (ulong)lldiv((unsigned long long)refclk *
  831. (((divn + 1) << 13) + fracv),
  832. ((unsigned long long)(divm + 1)) << 13);
  833. } else {
  834. fvco = (ulong)(refclk * (divn + 1) / (divm + 1));
  835. }
  836. return fvco;
  837. }
  838. static ulong stm32mp1_read_pll_freq(struct stm32mp1_clk_priv *priv,
  839. int pll_id, int div_id)
  840. {
  841. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  842. int divy;
  843. ulong dfout;
  844. u32 cfgr2;
  845. if (div_id >= _DIV_NB)
  846. return 0;
  847. cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2);
  848. divy = (cfgr2 >> RCC_PLLNCFGR2_SHIFT(div_id)) & RCC_PLLNCFGR2_DIVX_MASK;
  849. dfout = pll_get_fvco(priv, pll_id) / (divy + 1);
  850. return dfout;
  851. }
  852. static ulong stm32mp1_clk_get(struct stm32mp1_clk_priv *priv, int p)
  853. {
  854. u32 reg;
  855. ulong clock = 0;
  856. switch (p) {
  857. case _CK_MPU:
  858. /* MPU sub system */
  859. reg = readl(priv->base + RCC_MPCKSELR);
  860. switch (reg & RCC_SELR_SRC_MASK) {
  861. case RCC_MPCKSELR_HSI:
  862. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  863. break;
  864. case RCC_MPCKSELR_HSE:
  865. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  866. break;
  867. case RCC_MPCKSELR_PLL:
  868. case RCC_MPCKSELR_PLL_MPUDIV:
  869. clock = stm32mp1_read_pll_freq(priv, _PLL1, _DIV_P);
  870. if ((reg & RCC_SELR_SRC_MASK) ==
  871. RCC_MPCKSELR_PLL_MPUDIV) {
  872. reg = readl(priv->base + RCC_MPCKDIVR);
  873. clock >>= stm32mp1_mpu_div[reg &
  874. RCC_MPUDIV_MASK];
  875. }
  876. break;
  877. }
  878. break;
  879. /* AXI sub system */
  880. case _ACLK:
  881. case _HCLK2:
  882. case _HCLK6:
  883. case _PCLK4:
  884. case _PCLK5:
  885. reg = readl(priv->base + RCC_ASSCKSELR);
  886. switch (reg & RCC_SELR_SRC_MASK) {
  887. case RCC_ASSCKSELR_HSI:
  888. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  889. break;
  890. case RCC_ASSCKSELR_HSE:
  891. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  892. break;
  893. case RCC_ASSCKSELR_PLL:
  894. clock = stm32mp1_read_pll_freq(priv, _PLL2, _DIV_P);
  895. break;
  896. }
  897. /* System clock divider */
  898. reg = readl(priv->base + RCC_AXIDIVR);
  899. clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK];
  900. switch (p) {
  901. case _PCLK4:
  902. reg = readl(priv->base + RCC_APB4DIVR);
  903. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  904. break;
  905. case _PCLK5:
  906. reg = readl(priv->base + RCC_APB5DIVR);
  907. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  908. break;
  909. default:
  910. break;
  911. }
  912. break;
  913. /* MCU sub system */
  914. case _CK_MCU:
  915. case _PCLK1:
  916. case _PCLK2:
  917. case _PCLK3:
  918. reg = readl(priv->base + RCC_MSSCKSELR);
  919. switch (reg & RCC_SELR_SRC_MASK) {
  920. case RCC_MSSCKSELR_HSI:
  921. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  922. break;
  923. case RCC_MSSCKSELR_HSE:
  924. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  925. break;
  926. case RCC_MSSCKSELR_CSI:
  927. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  928. break;
  929. case RCC_MSSCKSELR_PLL:
  930. clock = stm32mp1_read_pll_freq(priv, _PLL3, _DIV_P);
  931. break;
  932. }
  933. /* MCU clock divider */
  934. reg = readl(priv->base + RCC_MCUDIVR);
  935. clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK];
  936. switch (p) {
  937. case _PCLK1:
  938. reg = readl(priv->base + RCC_APB1DIVR);
  939. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  940. break;
  941. case _PCLK2:
  942. reg = readl(priv->base + RCC_APB2DIVR);
  943. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  944. break;
  945. case _PCLK3:
  946. reg = readl(priv->base + RCC_APB3DIVR);
  947. clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK];
  948. break;
  949. case _CK_MCU:
  950. default:
  951. break;
  952. }
  953. break;
  954. case _CK_PER:
  955. reg = readl(priv->base + RCC_CPERCKSELR);
  956. switch (reg & RCC_SELR_SRC_MASK) {
  957. case RCC_CPERCKSELR_HSI:
  958. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  959. break;
  960. case RCC_CPERCKSELR_HSE:
  961. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  962. break;
  963. case RCC_CPERCKSELR_CSI:
  964. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  965. break;
  966. }
  967. break;
  968. case _HSI:
  969. case _HSI_KER:
  970. clock = stm32mp1_clk_get_fixed(priv, _HSI);
  971. break;
  972. case _CSI:
  973. case _CSI_KER:
  974. clock = stm32mp1_clk_get_fixed(priv, _CSI);
  975. break;
  976. case _HSE:
  977. case _HSE_KER:
  978. case _HSE_KER_DIV2:
  979. clock = stm32mp1_clk_get_fixed(priv, _HSE);
  980. if (p == _HSE_KER_DIV2)
  981. clock >>= 1;
  982. break;
  983. case _LSI:
  984. clock = stm32mp1_clk_get_fixed(priv, _LSI);
  985. break;
  986. case _LSE:
  987. clock = stm32mp1_clk_get_fixed(priv, _LSE);
  988. break;
  989. /* PLL */
  990. case _PLL1_P:
  991. case _PLL1_Q:
  992. case _PLL1_R:
  993. clock = stm32mp1_read_pll_freq(priv, _PLL1, p - _PLL1_P);
  994. break;
  995. case _PLL2_P:
  996. case _PLL2_Q:
  997. case _PLL2_R:
  998. clock = stm32mp1_read_pll_freq(priv, _PLL2, p - _PLL2_P);
  999. break;
  1000. case _PLL3_P:
  1001. case _PLL3_Q:
  1002. case _PLL3_R:
  1003. clock = stm32mp1_read_pll_freq(priv, _PLL3, p - _PLL3_P);
  1004. break;
  1005. case _PLL4_P:
  1006. case _PLL4_Q:
  1007. case _PLL4_R:
  1008. clock = stm32mp1_read_pll_freq(priv, _PLL4, p - _PLL4_P);
  1009. break;
  1010. /* other */
  1011. case _USB_PHY_48:
  1012. clock = 48000000;
  1013. break;
  1014. case _DSI_PHY:
  1015. {
  1016. struct clk clk;
  1017. struct udevice *dev = NULL;
  1018. if (!uclass_get_device_by_name(UCLASS_CLK, "ck_dsi_phy",
  1019. &dev)) {
  1020. if (clk_request(dev, &clk)) {
  1021. log_err("ck_dsi_phy request");
  1022. } else {
  1023. clk.id = 0;
  1024. clock = clk_get_rate(&clk);
  1025. }
  1026. }
  1027. break;
  1028. }
  1029. default:
  1030. break;
  1031. }
  1032. log_debug("id=%d clock = %lx : %ld kHz\n", p, clock, clock / 1000);
  1033. return clock;
  1034. }
  1035. static int stm32mp1_clk_enable(struct clk *clk)
  1036. {
  1037. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1038. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1039. int i = stm32mp1_clk_get_id(priv, clk->id);
  1040. if (i < 0)
  1041. return i;
  1042. if (gate[i].set_clr)
  1043. writel(BIT(gate[i].bit), priv->base + gate[i].offset);
  1044. else
  1045. setbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1046. dev_dbg(clk->dev, "%s: id clock %d has been enabled\n", __func__, (u32)clk->id);
  1047. return 0;
  1048. }
  1049. static int stm32mp1_clk_disable(struct clk *clk)
  1050. {
  1051. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1052. const struct stm32mp1_clk_gate *gate = priv->data->gate;
  1053. int i = stm32mp1_clk_get_id(priv, clk->id);
  1054. if (i < 0)
  1055. return i;
  1056. if (gate[i].set_clr)
  1057. writel(BIT(gate[i].bit),
  1058. priv->base + gate[i].offset
  1059. + RCC_MP_ENCLRR_OFFSET);
  1060. else
  1061. clrbits_le32(priv->base + gate[i].offset, BIT(gate[i].bit));
  1062. dev_dbg(clk->dev, "%s: id clock %d has been disabled\n", __func__, (u32)clk->id);
  1063. return 0;
  1064. }
  1065. static ulong stm32mp1_clk_get_rate(struct clk *clk)
  1066. {
  1067. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1068. int p = stm32mp1_clk_get_parent(priv, clk->id);
  1069. ulong rate;
  1070. if (p < 0)
  1071. return 0;
  1072. rate = stm32mp1_clk_get(priv, p);
  1073. dev_vdbg(clk->dev, "computed rate for id clock %d is %d (parent is %s)\n",
  1074. (u32)clk->id, (u32)rate, stm32mp1_clk_parent_name[p]);
  1075. return rate;
  1076. }
  1077. #ifdef STM32MP1_CLOCK_TREE_INIT
  1078. bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
  1079. {
  1080. unsigned int id;
  1081. switch (opp_id) {
  1082. case 1:
  1083. case 2:
  1084. id = opp_id;
  1085. break;
  1086. default:
  1087. id = 1; /* default value */
  1088. break;
  1089. }
  1090. switch (cpu_type) {
  1091. case CPU_STM32MP157Fxx:
  1092. case CPU_STM32MP157Dxx:
  1093. case CPU_STM32MP153Fxx:
  1094. case CPU_STM32MP153Dxx:
  1095. case CPU_STM32MP151Fxx:
  1096. case CPU_STM32MP151Dxx:
  1097. return true;
  1098. default:
  1099. return id == 1;
  1100. }
  1101. }
  1102. __weak void board_vddcore_init(u32 voltage_mv)
  1103. {
  1104. }
  1105. /*
  1106. * gets OPP parameters (frequency in KHz and voltage in mV) from
  1107. * an OPP table subnode. Platform HW support capabilities are also checked.
  1108. * Returns 0 on success and a negative FDT error code on failure.
  1109. */
  1110. static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
  1111. u32 *freq_khz, u32 *voltage_mv)
  1112. {
  1113. u32 opp_hw;
  1114. u64 read_freq_64;
  1115. u32 read_voltage_32;
  1116. *freq_khz = 0;
  1117. *voltage_mv = 0;
  1118. opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
  1119. if (opp_hw)
  1120. if (!stm32mp1_supports_opp(opp_hw, cpu_type))
  1121. return -FDT_ERR_BADVALUE;
  1122. read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
  1123. 1000ULL;
  1124. read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
  1125. 1000U;
  1126. if (!read_voltage_32 || !read_freq_64)
  1127. return -FDT_ERR_NOTFOUND;
  1128. /* Frequency value expressed in KHz must fit on 32 bits */
  1129. if (read_freq_64 > U32_MAX)
  1130. return -FDT_ERR_BADVALUE;
  1131. /* Millivolt value must fit on 16 bits */
  1132. if (read_voltage_32 > U16_MAX)
  1133. return -FDT_ERR_BADVALUE;
  1134. *freq_khz = (u32)read_freq_64;
  1135. *voltage_mv = read_voltage_32;
  1136. return 0;
  1137. }
  1138. /*
  1139. * parses OPP table in DT and finds the parameters for the
  1140. * highest frequency supported by the HW platform.
  1141. * Returns 0 on success and a negative FDT error code on failure.
  1142. */
  1143. int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
  1144. {
  1145. ofnode node, subnode;
  1146. int ret;
  1147. u32 freq = 0U, voltage = 0U;
  1148. u32 cpu_type = get_cpu_type();
  1149. node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
  1150. if (!ofnode_valid(node))
  1151. return -FDT_ERR_NOTFOUND;
  1152. ofnode_for_each_subnode(subnode, node) {
  1153. unsigned int read_freq;
  1154. unsigned int read_voltage;
  1155. ret = stm32mp1_get_opp(cpu_type, subnode,
  1156. &read_freq, &read_voltage);
  1157. if (ret)
  1158. continue;
  1159. if (read_freq > freq) {
  1160. freq = read_freq;
  1161. voltage = read_voltage;
  1162. }
  1163. }
  1164. if (!freq || !voltage)
  1165. return -FDT_ERR_NOTFOUND;
  1166. *freq_hz = (u64)1000U * freq;
  1167. board_vddcore_init(voltage);
  1168. return 0;
  1169. }
  1170. static int stm32mp1_pll1_opp(struct stm32mp1_clk_priv *priv, int clksrc,
  1171. u32 *pllcfg, u32 *fracv)
  1172. {
  1173. u32 post_divm;
  1174. u32 input_freq;
  1175. u64 output_freq;
  1176. u64 freq;
  1177. u64 vco;
  1178. u32 divm, divn, divp, frac;
  1179. int i, ret;
  1180. u32 diff;
  1181. u32 best_diff = U32_MAX;
  1182. /* PLL1 is 1600 */
  1183. const u32 DIVN_MAX = stm32mp1_pll[PLL_1600].divn_max;
  1184. const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_1600].refclk_min * 1000000U;
  1185. const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_1600].refclk_max * 1000000U;
  1186. ret = stm32mp1_get_max_opp_freq(priv, &output_freq);
  1187. if (ret) {
  1188. log_debug("PLL1 OPP configuration not found (%d).\n", ret);
  1189. return ret;
  1190. }
  1191. switch (clksrc) {
  1192. case CLK_PLL12_HSI:
  1193. input_freq = stm32mp1_clk_get_fixed(priv, _HSI);
  1194. break;
  1195. case CLK_PLL12_HSE:
  1196. input_freq = stm32mp1_clk_get_fixed(priv, _HSE);
  1197. break;
  1198. default:
  1199. return -EINTR;
  1200. }
  1201. /* Following parameters have always the same value */
  1202. pllcfg[PLLCFG_Q] = 0;
  1203. pllcfg[PLLCFG_R] = 0;
  1204. pllcfg[PLLCFG_O] = PQR(1, 0, 0);
  1205. for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) {
  1206. post_divm = (u32)(input_freq / (divm + 1));
  1207. if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX)
  1208. continue;
  1209. for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) {
  1210. freq = output_freq * (divm + 1) * (divp + 1);
  1211. divn = (u32)((freq / input_freq) - 1);
  1212. if (divn < DIVN_MIN || divn > DIVN_MAX)
  1213. continue;
  1214. frac = (u32)(((freq * FRAC_MAX) / input_freq) -
  1215. ((divn + 1) * FRAC_MAX));
  1216. /* 2 loops to refine the fractional part */
  1217. for (i = 2; i != 0; i--) {
  1218. if (frac > FRAC_MAX)
  1219. break;
  1220. vco = (post_divm * (divn + 1)) +
  1221. ((post_divm * (u64)frac) /
  1222. FRAC_MAX);
  1223. if (vco < (PLL1600_VCO_MIN / 2) ||
  1224. vco > (PLL1600_VCO_MAX / 2)) {
  1225. frac++;
  1226. continue;
  1227. }
  1228. freq = vco / (divp + 1);
  1229. if (output_freq < freq)
  1230. diff = (u32)(freq - output_freq);
  1231. else
  1232. diff = (u32)(output_freq - freq);
  1233. if (diff < best_diff) {
  1234. pllcfg[PLLCFG_M] = divm;
  1235. pllcfg[PLLCFG_N] = divn;
  1236. pllcfg[PLLCFG_P] = divp;
  1237. *fracv = frac;
  1238. if (diff == 0)
  1239. return 0;
  1240. best_diff = diff;
  1241. }
  1242. frac++;
  1243. }
  1244. }
  1245. }
  1246. if (best_diff == U32_MAX)
  1247. return -1;
  1248. return 0;
  1249. }
  1250. static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset,
  1251. u32 mask_on)
  1252. {
  1253. u32 address = rcc + offset;
  1254. if (enable)
  1255. setbits_le32(address, mask_on);
  1256. else
  1257. clrbits_le32(address, mask_on);
  1258. }
  1259. static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on)
  1260. {
  1261. writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR));
  1262. }
  1263. static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset,
  1264. u32 mask_rdy)
  1265. {
  1266. u32 mask_test = 0;
  1267. u32 address = rcc + offset;
  1268. u32 val;
  1269. int ret;
  1270. if (enable)
  1271. mask_test = mask_rdy;
  1272. ret = readl_poll_timeout(address, val,
  1273. (val & mask_rdy) == mask_test,
  1274. TIMEOUT_1S);
  1275. if (ret)
  1276. log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n",
  1277. mask_rdy, address, enable, readl(address));
  1278. return ret;
  1279. }
  1280. static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp,
  1281. u32 lsedrv)
  1282. {
  1283. u32 value;
  1284. if (digbyp)
  1285. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP);
  1286. if (bypass || digbyp)
  1287. setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP);
  1288. /*
  1289. * warning: not recommended to switch directly from "high drive"
  1290. * to "medium low drive", and vice-versa.
  1291. */
  1292. value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK)
  1293. >> RCC_BDCR_LSEDRV_SHIFT;
  1294. while (value != lsedrv) {
  1295. if (value > lsedrv)
  1296. value--;
  1297. else
  1298. value++;
  1299. clrsetbits_le32(rcc + RCC_BDCR,
  1300. RCC_BDCR_LSEDRV_MASK,
  1301. value << RCC_BDCR_LSEDRV_SHIFT);
  1302. }
  1303. stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON);
  1304. }
  1305. static void stm32mp1_lse_wait(fdt_addr_t rcc)
  1306. {
  1307. stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY);
  1308. }
  1309. static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable)
  1310. {
  1311. stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION);
  1312. stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY);
  1313. }
  1314. static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css)
  1315. {
  1316. if (digbyp)
  1317. writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR);
  1318. if (bypass || digbyp)
  1319. writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR);
  1320. stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON);
  1321. stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY);
  1322. if (css)
  1323. writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR);
  1324. }
  1325. static void stm32mp1_csi_set(fdt_addr_t rcc, int enable)
  1326. {
  1327. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION);
  1328. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY);
  1329. }
  1330. static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable)
  1331. {
  1332. stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION);
  1333. stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY);
  1334. }
  1335. static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv)
  1336. {
  1337. u32 address = rcc + RCC_OCRDYR;
  1338. u32 val;
  1339. int ret;
  1340. clrsetbits_le32(rcc + RCC_HSICFGR,
  1341. RCC_HSICFGR_HSIDIV_MASK,
  1342. RCC_HSICFGR_HSIDIV_MASK & hsidiv);
  1343. ret = readl_poll_timeout(address, val,
  1344. val & RCC_OCRDYR_HSIDIVRDY,
  1345. TIMEOUT_200MS);
  1346. if (ret)
  1347. log_err("HSIDIV failed @ 0x%x: 0x%x\n",
  1348. address, readl(address));
  1349. return ret;
  1350. }
  1351. static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq)
  1352. {
  1353. u8 hsidiv;
  1354. u32 hsidivfreq = MAX_HSI_HZ;
  1355. for (hsidiv = 0; hsidiv < 4; hsidiv++,
  1356. hsidivfreq = hsidivfreq / 2)
  1357. if (hsidivfreq == hsifreq)
  1358. break;
  1359. if (hsidiv == 4) {
  1360. log_err("hsi frequency invalid");
  1361. return -1;
  1362. }
  1363. if (hsidiv > 0)
  1364. return stm32mp1_set_hsidiv(rcc, hsidiv);
  1365. return 0;
  1366. }
  1367. static void pll_start(struct stm32mp1_clk_priv *priv, int pll_id)
  1368. {
  1369. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1370. clrsetbits_le32(priv->base + pll[pll_id].pllxcr,
  1371. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN |
  1372. RCC_PLLNCR_DIVREN,
  1373. RCC_PLLNCR_PLLON);
  1374. }
  1375. static int pll_output(struct stm32mp1_clk_priv *priv, int pll_id, int output)
  1376. {
  1377. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1378. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1379. u32 val;
  1380. int ret;
  1381. ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY,
  1382. TIMEOUT_200MS);
  1383. if (ret) {
  1384. log_err("PLL%d start failed @ 0x%x: 0x%x\n",
  1385. pll_id, pllxcr, readl(pllxcr));
  1386. return ret;
  1387. }
  1388. /* start the requested output */
  1389. setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT);
  1390. return 0;
  1391. }
  1392. static int pll_stop(struct stm32mp1_clk_priv *priv, int pll_id)
  1393. {
  1394. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1395. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1396. u32 val;
  1397. /* stop all output */
  1398. clrbits_le32(pllxcr,
  1399. RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);
  1400. /* stop PLL */
  1401. clrbits_le32(pllxcr, RCC_PLLNCR_PLLON);
  1402. /* wait PLL stopped */
  1403. return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0,
  1404. TIMEOUT_200MS);
  1405. }
  1406. static void pll_config_output(struct stm32mp1_clk_priv *priv,
  1407. int pll_id, u32 *pllcfg)
  1408. {
  1409. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1410. fdt_addr_t rcc = priv->base;
  1411. u32 value;
  1412. value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT)
  1413. & RCC_PLLNCFGR2_DIVP_MASK;
  1414. value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT)
  1415. & RCC_PLLNCFGR2_DIVQ_MASK;
  1416. value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT)
  1417. & RCC_PLLNCFGR2_DIVR_MASK;
  1418. writel(value, rcc + pll[pll_id].pllxcfgr2);
  1419. }
  1420. static int pll_config(struct stm32mp1_clk_priv *priv, int pll_id,
  1421. u32 *pllcfg, u32 fracv)
  1422. {
  1423. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1424. fdt_addr_t rcc = priv->base;
  1425. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1426. int src;
  1427. ulong refclk;
  1428. u8 ifrge = 0;
  1429. u32 value;
  1430. src = readl(priv->base + pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK;
  1431. refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]) /
  1432. (pllcfg[PLLCFG_M] + 1);
  1433. if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) ||
  1434. refclk > (stm32mp1_pll[type].refclk_max * 1000000)) {
  1435. log_err("invalid refclk = %x\n", (u32)refclk);
  1436. return -EINVAL;
  1437. }
  1438. if (type == PLL_800 && refclk >= 8000000)
  1439. ifrge = 1;
  1440. value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT)
  1441. & RCC_PLLNCFGR1_DIVN_MASK;
  1442. value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT)
  1443. & RCC_PLLNCFGR1_DIVM_MASK;
  1444. value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT)
  1445. & RCC_PLLNCFGR1_IFRGE_MASK;
  1446. writel(value, rcc + pll[pll_id].pllxcfgr1);
  1447. /* fractional configuration: load sigma-delta modulator (SDM) */
  1448. /* Write into FRACV the new fractional value , and FRACLE to 0 */
  1449. writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT,
  1450. rcc + pll[pll_id].pllxfracr);
  1451. /* Write FRACLE to 1 : FRACV value is loaded into the SDM */
  1452. setbits_le32(rcc + pll[pll_id].pllxfracr,
  1453. RCC_PLLNFRACR_FRACLE);
  1454. pll_config_output(priv, pll_id, pllcfg);
  1455. return 0;
  1456. }
  1457. static void pll_csg(struct stm32mp1_clk_priv *priv, int pll_id, u32 *csg)
  1458. {
  1459. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1460. u32 pllxcsg;
  1461. pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) &
  1462. RCC_PLLNCSGR_MOD_PER_MASK) |
  1463. ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) &
  1464. RCC_PLLNCSGR_INC_STEP_MASK) |
  1465. ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) &
  1466. RCC_PLLNCSGR_SSCG_MODE_MASK);
  1467. writel(pllxcsg, priv->base + pll[pll_id].pllxcsgr);
  1468. setbits_le32(priv->base + pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL);
  1469. }
  1470. static __maybe_unused int pll_set_rate(struct udevice *dev,
  1471. int pll_id,
  1472. int div_id,
  1473. unsigned long clk_rate)
  1474. {
  1475. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1476. unsigned int pllcfg[PLLCFG_NB];
  1477. ofnode plloff;
  1478. char name[12];
  1479. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1480. enum stm32mp1_plltype type = pll[pll_id].plltype;
  1481. int divm, divn, divy;
  1482. int ret;
  1483. ulong fck_ref;
  1484. u32 fracv;
  1485. u64 value;
  1486. if (div_id > _DIV_NB)
  1487. return -EINVAL;
  1488. sprintf(name, "st,pll@%d", pll_id);
  1489. plloff = dev_read_subnode(dev, name);
  1490. if (!ofnode_valid(plloff))
  1491. return -FDT_ERR_NOTFOUND;
  1492. ret = ofnode_read_u32_array(plloff, "cfg",
  1493. pllcfg, PLLCFG_NB);
  1494. if (ret < 0)
  1495. return -FDT_ERR_NOTFOUND;
  1496. fck_ref = pll_get_fref_ck(priv, pll_id);
  1497. divm = pllcfg[PLLCFG_M];
  1498. /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */
  1499. divy = pllcfg[PLLCFG_P + div_id];
  1500. /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2
  1501. * So same final result than PLL2 et 4
  1502. * with FRACV
  1503. * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13)
  1504. * / (DIVy + 1) * (DIVM + 1)
  1505. * value = (DIVN + 1) * 2^13 + FRACV / 2^13
  1506. * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref
  1507. */
  1508. value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13;
  1509. value = lldiv(value, fck_ref);
  1510. divn = (value >> 13) - 1;
  1511. if (divn < DIVN_MIN ||
  1512. divn > stm32mp1_pll[type].divn_max) {
  1513. dev_err(dev, "divn invalid = %d", divn);
  1514. return -EINVAL;
  1515. }
  1516. fracv = value - ((divn + 1) << 13);
  1517. pllcfg[PLLCFG_N] = divn;
  1518. /* reconfigure PLL */
  1519. pll_stop(priv, pll_id);
  1520. pll_config(priv, pll_id, pllcfg, fracv);
  1521. pll_start(priv, pll_id);
  1522. pll_output(priv, pll_id, pllcfg[PLLCFG_O]);
  1523. return 0;
  1524. }
  1525. static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc)
  1526. {
  1527. u32 address = priv->base + (clksrc >> 4);
  1528. u32 val;
  1529. int ret;
  1530. clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK);
  1531. ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY,
  1532. TIMEOUT_200MS);
  1533. if (ret)
  1534. log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n",
  1535. clksrc, address, readl(address));
  1536. return ret;
  1537. }
  1538. static void stgen_config(struct stm32mp1_clk_priv *priv)
  1539. {
  1540. int p;
  1541. u32 stgenc, cntfid0;
  1542. ulong rate;
  1543. stgenc = STM32_STGEN_BASE;
  1544. cntfid0 = readl(stgenc + STGENC_CNTFID0);
  1545. p = stm32mp1_clk_get_parent(priv, STGEN_K);
  1546. rate = stm32mp1_clk_get(priv, p);
  1547. if (cntfid0 != rate) {
  1548. u64 counter;
  1549. log_debug("System Generic Counter (STGEN) update\n");
  1550. clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1551. counter = (u64)readl(stgenc + STGENC_CNTCVL);
  1552. counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32;
  1553. counter = lldiv(counter * (u64)rate, cntfid0);
  1554. writel((u32)counter, stgenc + STGENC_CNTCVL);
  1555. writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU);
  1556. writel(rate, stgenc + STGENC_CNTFID0);
  1557. setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN);
  1558. __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate));
  1559. /* need to update gd->arch.timer_rate_hz with new frequency */
  1560. timer_init();
  1561. }
  1562. }
  1563. static int set_clkdiv(unsigned int clkdiv, u32 address)
  1564. {
  1565. u32 val;
  1566. int ret;
  1567. clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK);
  1568. ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY,
  1569. TIMEOUT_200MS);
  1570. if (ret)
  1571. log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n",
  1572. clkdiv, address, readl(address));
  1573. return ret;
  1574. }
  1575. static void stm32mp1_mco_csg(struct stm32mp1_clk_priv *priv,
  1576. u32 clksrc, u32 clkdiv)
  1577. {
  1578. u32 address = priv->base + (clksrc >> 4);
  1579. /*
  1580. * binding clksrc : bit15-4 offset
  1581. * bit3: disable
  1582. * bit2-0: MCOSEL[2:0]
  1583. */
  1584. if (clksrc & 0x8) {
  1585. clrbits_le32(address, RCC_MCOCFG_MCOON);
  1586. } else {
  1587. clrsetbits_le32(address,
  1588. RCC_MCOCFG_MCOSRC_MASK,
  1589. clksrc & RCC_MCOCFG_MCOSRC_MASK);
  1590. clrsetbits_le32(address,
  1591. RCC_MCOCFG_MCODIV_MASK,
  1592. clkdiv << RCC_MCOCFG_MCODIV_SHIFT);
  1593. setbits_le32(address, RCC_MCOCFG_MCOON);
  1594. }
  1595. }
  1596. static void set_rtcsrc(struct stm32mp1_clk_priv *priv,
  1597. unsigned int clksrc,
  1598. int lse_css)
  1599. {
  1600. u32 address = priv->base + RCC_BDCR;
  1601. if (readl(address) & RCC_BDCR_RTCCKEN)
  1602. goto skip_rtc;
  1603. if (clksrc == CLK_RTC_DISABLED)
  1604. goto skip_rtc;
  1605. clrsetbits_le32(address,
  1606. RCC_BDCR_RTCSRC_MASK,
  1607. clksrc << RCC_BDCR_RTCSRC_SHIFT);
  1608. setbits_le32(address, RCC_BDCR_RTCCKEN);
  1609. skip_rtc:
  1610. if (lse_css)
  1611. setbits_le32(address, RCC_BDCR_LSECSSON);
  1612. }
  1613. static void pkcs_config(struct stm32mp1_clk_priv *priv, u32 pkcs)
  1614. {
  1615. u32 address = priv->base + ((pkcs >> 4) & 0xFFF);
  1616. u32 value = pkcs & 0xF;
  1617. u32 mask = 0xF;
  1618. if (pkcs & BIT(31)) {
  1619. mask <<= 4;
  1620. value <<= 4;
  1621. }
  1622. clrsetbits_le32(address, mask, value);
  1623. }
  1624. static int stm32mp1_clktree(struct udevice *dev)
  1625. {
  1626. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1627. fdt_addr_t rcc = priv->base;
  1628. unsigned int clksrc[CLKSRC_NB];
  1629. unsigned int clkdiv[CLKDIV_NB];
  1630. unsigned int pllcfg[_PLL_NB][PLLCFG_NB];
  1631. unsigned int pllfracv[_PLL_NB];
  1632. unsigned int pllcsg[_PLL_NB][PLLCSG_NB];
  1633. bool pllcfg_valid[_PLL_NB];
  1634. bool pllcsg_set[_PLL_NB];
  1635. int ret;
  1636. int i, len;
  1637. int lse_css = 0;
  1638. const u32 *pkcs_cell;
  1639. /* check mandatory field */
  1640. ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB);
  1641. if (ret < 0) {
  1642. dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret);
  1643. return -FDT_ERR_NOTFOUND;
  1644. }
  1645. ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB);
  1646. if (ret < 0) {
  1647. dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret);
  1648. return -FDT_ERR_NOTFOUND;
  1649. }
  1650. /* check mandatory field in each pll */
  1651. for (i = 0; i < _PLL_NB; i++) {
  1652. char name[12];
  1653. ofnode node;
  1654. sprintf(name, "st,pll@%d", i);
  1655. node = dev_read_subnode(dev, name);
  1656. pllcfg_valid[i] = ofnode_valid(node);
  1657. pllcsg_set[i] = false;
  1658. if (pllcfg_valid[i]) {
  1659. dev_dbg(dev, "DT for PLL %d @ %s\n", i, name);
  1660. ret = ofnode_read_u32_array(node, "cfg",
  1661. pllcfg[i], PLLCFG_NB);
  1662. if (ret < 0) {
  1663. dev_dbg(dev, "field cfg invalid: error %d\n", ret);
  1664. return -FDT_ERR_NOTFOUND;
  1665. }
  1666. pllfracv[i] = ofnode_read_u32_default(node, "frac", 0);
  1667. ret = ofnode_read_u32_array(node, "csg", pllcsg[i],
  1668. PLLCSG_NB);
  1669. if (!ret) {
  1670. pllcsg_set[i] = true;
  1671. } else if (ret != -FDT_ERR_NOTFOUND) {
  1672. dev_dbg(dev, "invalid csg node for pll@%d res=%d\n",
  1673. i, ret);
  1674. return ret;
  1675. }
  1676. } else if (i == _PLL1) {
  1677. /* use OPP for PLL1 for A7 CPU */
  1678. dev_dbg(dev, "DT for PLL %d with OPP\n", i);
  1679. ret = stm32mp1_pll1_opp(priv,
  1680. clksrc[CLKSRC_PLL12],
  1681. pllcfg[i],
  1682. &pllfracv[i]);
  1683. if (ret) {
  1684. dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret);
  1685. return ret;
  1686. }
  1687. pllcfg_valid[i] = true;
  1688. }
  1689. }
  1690. dev_dbg(dev, "configuration MCO\n");
  1691. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]);
  1692. stm32mp1_mco_csg(priv, clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]);
  1693. dev_dbg(dev, "switch ON osillator\n");
  1694. /*
  1695. * switch ON oscillator found in device-tree,
  1696. * HSI already ON after bootrom
  1697. */
  1698. if (clk_valid(&priv->osc_clk[_LSI]))
  1699. stm32mp1_lsi_set(rcc, 1);
  1700. if (clk_valid(&priv->osc_clk[_LSE])) {
  1701. int bypass, digbyp;
  1702. u32 lsedrv;
  1703. struct udevice *dev = priv->osc_clk[_LSE].dev;
  1704. bypass = dev_read_bool(dev, "st,bypass");
  1705. digbyp = dev_read_bool(dev, "st,digbypass");
  1706. lse_css = dev_read_bool(dev, "st,css");
  1707. lsedrv = dev_read_u32_default(dev, "st,drive",
  1708. LSEDRV_MEDIUM_HIGH);
  1709. stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv);
  1710. }
  1711. if (clk_valid(&priv->osc_clk[_HSE])) {
  1712. int bypass, digbyp, css;
  1713. struct udevice *dev = priv->osc_clk[_HSE].dev;
  1714. bypass = dev_read_bool(dev, "st,bypass");
  1715. digbyp = dev_read_bool(dev, "st,digbypass");
  1716. css = dev_read_bool(dev, "st,css");
  1717. stm32mp1_hse_enable(rcc, bypass, digbyp, css);
  1718. }
  1719. /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR)
  1720. * => switch on CSI even if node is not present in device tree
  1721. */
  1722. stm32mp1_csi_set(rcc, 1);
  1723. /* come back to HSI */
  1724. dev_dbg(dev, "come back to HSI\n");
  1725. set_clksrc(priv, CLK_MPU_HSI);
  1726. set_clksrc(priv, CLK_AXI_HSI);
  1727. set_clksrc(priv, CLK_MCU_HSI);
  1728. dev_dbg(dev, "pll stop\n");
  1729. for (i = 0; i < _PLL_NB; i++)
  1730. pll_stop(priv, i);
  1731. /* configure HSIDIV */
  1732. dev_dbg(dev, "configure HSIDIV\n");
  1733. if (clk_valid(&priv->osc_clk[_HSI])) {
  1734. stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI]));
  1735. stgen_config(priv);
  1736. }
  1737. /* select DIV */
  1738. dev_dbg(dev, "select DIV\n");
  1739. /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */
  1740. writel(clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK, rcc + RCC_MPCKDIVR);
  1741. set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR);
  1742. set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR);
  1743. set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR);
  1744. set_clkdiv(clkdiv[CLKDIV_MCU], rcc + RCC_MCUDIVR);
  1745. set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR);
  1746. set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR);
  1747. set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR);
  1748. /* no ready bit for RTC */
  1749. writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR);
  1750. /* configure PLLs source */
  1751. dev_dbg(dev, "configure PLLs source\n");
  1752. set_clksrc(priv, clksrc[CLKSRC_PLL12]);
  1753. set_clksrc(priv, clksrc[CLKSRC_PLL3]);
  1754. set_clksrc(priv, clksrc[CLKSRC_PLL4]);
  1755. /* configure and start PLLs */
  1756. dev_dbg(dev, "configure PLLs\n");
  1757. for (i = 0; i < _PLL_NB; i++) {
  1758. if (!pllcfg_valid[i])
  1759. continue;
  1760. dev_dbg(dev, "configure PLL %d\n", i);
  1761. pll_config(priv, i, pllcfg[i], pllfracv[i]);
  1762. if (pllcsg_set[i])
  1763. pll_csg(priv, i, pllcsg[i]);
  1764. pll_start(priv, i);
  1765. }
  1766. /* wait and start PLLs ouptut when ready */
  1767. for (i = 0; i < _PLL_NB; i++) {
  1768. if (!pllcfg_valid[i])
  1769. continue;
  1770. dev_dbg(dev, "output PLL %d\n", i);
  1771. pll_output(priv, i, pllcfg[i][PLLCFG_O]);
  1772. }
  1773. /* wait LSE ready before to use it */
  1774. if (clk_valid(&priv->osc_clk[_LSE]))
  1775. stm32mp1_lse_wait(rcc);
  1776. /* configure with expected clock source */
  1777. dev_dbg(dev, "CLKSRC\n");
  1778. set_clksrc(priv, clksrc[CLKSRC_MPU]);
  1779. set_clksrc(priv, clksrc[CLKSRC_AXI]);
  1780. set_clksrc(priv, clksrc[CLKSRC_MCU]);
  1781. set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css);
  1782. /* configure PKCK */
  1783. dev_dbg(dev, "PKCK\n");
  1784. pkcs_cell = dev_read_prop(dev, "st,pkcs", &len);
  1785. if (pkcs_cell) {
  1786. bool ckper_disabled = false;
  1787. for (i = 0; i < len / sizeof(u32); i++) {
  1788. u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]);
  1789. if (pkcs == CLK_CKPER_DISABLED) {
  1790. ckper_disabled = true;
  1791. continue;
  1792. }
  1793. pkcs_config(priv, pkcs);
  1794. }
  1795. /* CKPER is source for some peripheral clock
  1796. * (FMC-NAND / QPSI-NOR) and switching source is allowed
  1797. * only if previous clock is still ON
  1798. * => deactivated CKPER only after switching clock
  1799. */
  1800. if (ckper_disabled)
  1801. pkcs_config(priv, CLK_CKPER_DISABLED);
  1802. }
  1803. /* STGEN clock source can change with CLK_STGEN_XXX */
  1804. stgen_config(priv);
  1805. dev_dbg(dev, "oscillator off\n");
  1806. /* switch OFF HSI if not found in device-tree */
  1807. if (!clk_valid(&priv->osc_clk[_HSI]))
  1808. stm32mp1_hsi_set(rcc, 0);
  1809. /* Software Self-Refresh mode (SSR) during DDR initilialization */
  1810. clrsetbits_le32(priv->base + RCC_DDRITFCR,
  1811. RCC_DDRITFCR_DDRCKMOD_MASK,
  1812. RCC_DDRITFCR_DDRCKMOD_SSR <<
  1813. RCC_DDRITFCR_DDRCKMOD_SHIFT);
  1814. return 0;
  1815. }
  1816. #endif /* STM32MP1_CLOCK_TREE_INIT */
  1817. static int pll_set_output_rate(struct udevice *dev,
  1818. int pll_id,
  1819. int div_id,
  1820. unsigned long clk_rate)
  1821. {
  1822. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1823. const struct stm32mp1_clk_pll *pll = priv->data->pll;
  1824. u32 pllxcr = priv->base + pll[pll_id].pllxcr;
  1825. int div;
  1826. ulong fvco;
  1827. if (div_id > _DIV_NB)
  1828. return -EINVAL;
  1829. fvco = pll_get_fvco(priv, pll_id);
  1830. if (fvco <= clk_rate)
  1831. div = 1;
  1832. else
  1833. div = DIV_ROUND_UP(fvco, clk_rate);
  1834. if (div > 128)
  1835. div = 128;
  1836. /* stop the requested output */
  1837. clrbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1838. /* change divider */
  1839. clrsetbits_le32(priv->base + pll[pll_id].pllxcfgr2,
  1840. RCC_PLLNCFGR2_DIVX_MASK << RCC_PLLNCFGR2_SHIFT(div_id),
  1841. (div - 1) << RCC_PLLNCFGR2_SHIFT(div_id));
  1842. /* start the requested output */
  1843. setbits_le32(pllxcr, 0x1 << div_id << RCC_PLLNCR_DIVEN_SHIFT);
  1844. return 0;
  1845. }
  1846. static ulong stm32mp1_clk_set_rate(struct clk *clk, unsigned long clk_rate)
  1847. {
  1848. struct stm32mp1_clk_priv *priv = dev_get_priv(clk->dev);
  1849. int p;
  1850. switch (clk->id) {
  1851. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1852. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1853. case DDRPHYC:
  1854. break;
  1855. #endif
  1856. case LTDC_PX:
  1857. case DSI_PX:
  1858. break;
  1859. default:
  1860. dev_err(clk->dev, "Set of clk %ld not supported", clk->id);
  1861. return -EINVAL;
  1862. }
  1863. p = stm32mp1_clk_get_parent(priv, clk->id);
  1864. dev_vdbg(clk->dev, "parent = %d:%s\n", p, stm32mp1_clk_parent_name[p]);
  1865. if (p < 0)
  1866. return -EINVAL;
  1867. switch (p) {
  1868. #if defined(STM32MP1_CLOCK_TREE_INIT) && \
  1869. defined(CONFIG_STM32MP1_DDR_INTERACTIVE)
  1870. case _PLL2_R: /* DDRPHYC */
  1871. {
  1872. /* only for change DDR clock in interactive mode */
  1873. ulong result;
  1874. set_clksrc(priv, CLK_AXI_HSI);
  1875. result = pll_set_rate(clk->dev, _PLL2, _DIV_R, clk_rate);
  1876. set_clksrc(priv, CLK_AXI_PLL2P);
  1877. return result;
  1878. }
  1879. #endif
  1880. case _PLL4_Q:
  1881. /* for LTDC_PX and DSI_PX case */
  1882. return pll_set_output_rate(clk->dev, _PLL4, _DIV_Q, clk_rate);
  1883. }
  1884. return -EINVAL;
  1885. }
  1886. static void stm32mp1_osc_init(struct udevice *dev)
  1887. {
  1888. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1889. int i;
  1890. const char *name[NB_OSC] = {
  1891. [_LSI] = "lsi",
  1892. [_LSE] = "lse",
  1893. [_HSI] = "hsi",
  1894. [_HSE] = "hse",
  1895. [_CSI] = "csi",
  1896. [_I2S_CKIN] = "i2s_ckin",
  1897. };
  1898. for (i = 0; i < NB_OSC; i++) {
  1899. if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
  1900. dev_dbg(dev, "No source clock \"%s\"", name[i]);
  1901. else
  1902. dev_dbg(dev, "%s clock rate: %luHz\n",
  1903. name[i], clk_get_rate(&priv->osc_clk[i]));
  1904. }
  1905. }
  1906. static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
  1907. {
  1908. char buf[32];
  1909. int i, s, p;
  1910. printf("Clocks:\n");
  1911. for (i = 0; i < _PARENT_NB; i++) {
  1912. printf("- %s : %s MHz\n",
  1913. stm32mp1_clk_parent_name[i],
  1914. strmhz(buf, stm32mp1_clk_get(priv, i)));
  1915. }
  1916. printf("Source Clocks:\n");
  1917. for (i = 0; i < _PARENT_SEL_NB; i++) {
  1918. p = (readl(priv->base + priv->data->sel[i].offset) >>
  1919. priv->data->sel[i].src) & priv->data->sel[i].msk;
  1920. if (p < priv->data->sel[i].nb_parent) {
  1921. s = priv->data->sel[i].parent[p];
  1922. printf("- %s(%d) => parent %s(%d)\n",
  1923. stm32mp1_clk_parent_sel_name[i], i,
  1924. stm32mp1_clk_parent_name[s], s);
  1925. } else {
  1926. printf("- %s(%d) => parent index %d is invalid\n",
  1927. stm32mp1_clk_parent_sel_name[i], i, p);
  1928. }
  1929. }
  1930. }
  1931. #ifdef CONFIG_CMD_CLK
  1932. int soc_clk_dump(void)
  1933. {
  1934. struct udevice *dev;
  1935. struct stm32mp1_clk_priv *priv;
  1936. int ret;
  1937. ret = uclass_get_device_by_driver(UCLASS_CLK,
  1938. DM_DRIVER_GET(stm32mp1_clock),
  1939. &dev);
  1940. if (ret)
  1941. return ret;
  1942. priv = dev_get_priv(dev);
  1943. stm32mp1_clk_dump(priv);
  1944. return 0;
  1945. }
  1946. #endif
  1947. static int stm32mp1_clk_probe(struct udevice *dev)
  1948. {
  1949. int result = 0;
  1950. struct stm32mp1_clk_priv *priv = dev_get_priv(dev);
  1951. priv->base = dev_read_addr(dev->parent);
  1952. if (priv->base == FDT_ADDR_T_NONE)
  1953. return -EINVAL;
  1954. priv->data = (void *)&stm32mp1_data;
  1955. if (!priv->data->gate || !priv->data->sel ||
  1956. !priv->data->pll)
  1957. return -EINVAL;
  1958. stm32mp1_osc_init(dev);
  1959. #ifdef STM32MP1_CLOCK_TREE_INIT
  1960. /* clock tree init is done only one time, before relocation */
  1961. if (!(gd->flags & GD_FLG_RELOC))
  1962. result = stm32mp1_clktree(dev);
  1963. if (result)
  1964. dev_err(dev, "clock tree initialization failed (%d)\n", result);
  1965. #endif
  1966. #ifndef CONFIG_SPL_BUILD
  1967. #if defined(VERBOSE_DEBUG)
  1968. /* display debug information for probe after relocation */
  1969. if (gd->flags & GD_FLG_RELOC)
  1970. stm32mp1_clk_dump(priv);
  1971. #endif
  1972. gd->cpu_clk = stm32mp1_clk_get(priv, _CK_MPU);
  1973. gd->bus_clk = stm32mp1_clk_get(priv, _ACLK);
  1974. /* DDRPHYC father */
  1975. gd->mem_clk = stm32mp1_clk_get(priv, _PLL2_R);
  1976. #if defined(CONFIG_DISPLAY_CPUINFO)
  1977. if (gd->flags & GD_FLG_RELOC) {
  1978. char buf[32];
  1979. log_info("Clocks:\n");
  1980. log_info("- MPU : %s MHz\n", strmhz(buf, gd->cpu_clk));
  1981. log_info("- MCU : %s MHz\n",
  1982. strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
  1983. log_info("- AXI : %s MHz\n", strmhz(buf, gd->bus_clk));
  1984. log_info("- PER : %s MHz\n",
  1985. strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
  1986. log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk));
  1987. }
  1988. #endif /* CONFIG_DISPLAY_CPUINFO */
  1989. #endif
  1990. return result;
  1991. }
  1992. static const struct clk_ops stm32mp1_clk_ops = {
  1993. .enable = stm32mp1_clk_enable,
  1994. .disable = stm32mp1_clk_disable,
  1995. .get_rate = stm32mp1_clk_get_rate,
  1996. .set_rate = stm32mp1_clk_set_rate,
  1997. };
  1998. U_BOOT_DRIVER(stm32mp1_clock) = {
  1999. .name = "stm32mp1_clk",
  2000. .id = UCLASS_CLK,
  2001. .ops = &stm32mp1_clk_ops,
  2002. .priv_auto = sizeof(struct stm32mp1_clk_priv),
  2003. .probe = stm32mp1_clk_probe,
  2004. };