clk_stm32h7.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  4. * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
  5. */
  6. #define LOG_CATEGORY UCLASS_CLK
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <log.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <dm/device_compat.h>
  15. #include <dm/root.h>
  16. #include <linux/bitops.h>
  17. #include <dt-bindings/clock/stm32h7-clks.h>
  18. /* RCC CR specific definitions */
  19. #define RCC_CR_HSION BIT(0)
  20. #define RCC_CR_HSIRDY BIT(2)
  21. #define RCC_CR_HSEON BIT(16)
  22. #define RCC_CR_HSERDY BIT(17)
  23. #define RCC_CR_HSEBYP BIT(18)
  24. #define RCC_CR_PLL1ON BIT(24)
  25. #define RCC_CR_PLL1RDY BIT(25)
  26. #define RCC_CR_HSIDIV_MASK GENMASK(4, 3)
  27. #define RCC_CR_HSIDIV_SHIFT 3
  28. #define RCC_CFGR_SW_MASK GENMASK(2, 0)
  29. #define RCC_CFGR_SW_HSI 0
  30. #define RCC_CFGR_SW_CSI 1
  31. #define RCC_CFGR_SW_HSE 2
  32. #define RCC_CFGR_SW_PLL1 3
  33. #define RCC_CFGR_TIMPRE BIT(15)
  34. #define RCC_PLLCKSELR_PLLSRC_HSI 0
  35. #define RCC_PLLCKSELR_PLLSRC_CSI 1
  36. #define RCC_PLLCKSELR_PLLSRC_HSE 2
  37. #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3
  38. #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0)
  39. #define RCC_PLLCKSELR_DIVM1_SHIFT 4
  40. #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4)
  41. #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0)
  42. #define RCC_PLL1DIVR_DIVP1_SHIFT 9
  43. #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9)
  44. #define RCC_PLL1DIVR_DIVQ1_SHIFT 16
  45. #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16)
  46. #define RCC_PLL1DIVR_DIVR1_SHIFT 24
  47. #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24)
  48. #define RCC_PLL1FRACR_FRACN1_SHIFT 3
  49. #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3)
  50. #define RCC_PLLCFGR_PLL1RGE_SHIFT 2
  51. #define PLL1RGE_1_2_MHZ 0
  52. #define PLL1RGE_2_4_MHZ 1
  53. #define PLL1RGE_4_8_MHZ 2
  54. #define PLL1RGE_8_16_MHZ 3
  55. #define RCC_PLLCFGR_DIVP1EN BIT(16)
  56. #define RCC_PLLCFGR_DIVQ1EN BIT(17)
  57. #define RCC_PLLCFGR_DIVR1EN BIT(18)
  58. #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0)
  59. #define RCC_D1CFGR_HPRE_DIVIDED BIT(3)
  60. #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0)
  61. #define RCC_D1CFGR_HPRE_DIV2 8
  62. #define RCC_D1CFGR_D1PPRE_SHIFT 4
  63. #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6)
  64. #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4)
  65. #define RCC_D1CFGR_D1CPRE_SHIFT 8
  66. #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8)
  67. #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11)
  68. #define RCC_D2CFGR_D2PPRE1_SHIFT 4
  69. #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6)
  70. #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4)
  71. #define RCC_D2CFGR_D2PPRE2_SHIFT 8
  72. #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10)
  73. #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8)
  74. #define RCC_D3CFGR_D3PPRE_SHIFT 4
  75. #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6)
  76. #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4)
  77. #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0)
  78. #define FMCSRC_HCLKD1 0
  79. #define FMCSRC_PLL1_Q_CK 1
  80. #define FMCSRC_PLL2_R_CK 2
  81. #define FMCSRC_PER_CK 3
  82. #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4)
  83. #define RCC_D1CCIPR_QSPISRC_SHIFT 4
  84. #define QSPISRC_HCLKD1 0
  85. #define QSPISRC_PLL1_Q_CK 1
  86. #define QSPISRC_PLL2_R_CK 2
  87. #define QSPISRC_PER_CK 3
  88. #define PWR_CR3 0x0c
  89. #define PWR_CR3_SCUEN BIT(2)
  90. #define PWR_D3CR 0x18
  91. #define PWR_D3CR_VOS_MASK GENMASK(15, 14)
  92. #define PWR_D3CR_VOS_SHIFT 14
  93. #define VOS_SCALE_3 1
  94. #define VOS_SCALE_2 2
  95. #define VOS_SCALE_1 3
  96. #define PWR_D3CR_VOSREADY BIT(13)
  97. struct stm32_rcc_regs {
  98. u32 cr; /* 0x00 Source Control Register */
  99. u32 icscr; /* 0x04 Internal Clock Source Calibration Register */
  100. u32 crrcr; /* 0x08 Clock Recovery RC Register */
  101. u32 reserved1; /* 0x0c reserved */
  102. u32 cfgr; /* 0x10 Clock Configuration Register */
  103. u32 reserved2; /* 0x14 reserved */
  104. u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */
  105. u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */
  106. u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */
  107. u32 reserved3; /* 0x24 reserved */
  108. u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */
  109. u32 pllcfgr; /* 0x2c PLLs Configuration Register */
  110. u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */
  111. u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */
  112. u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */
  113. u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */
  114. u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */
  115. u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */
  116. u32 reserved4; /* 0x48 reserved */
  117. u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */
  118. u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */
  119. u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */
  120. u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */
  121. u32 reserved5; /* 0x5c reserved */
  122. u32 cier; /* 0x60 Clock Source Interrupt Enable Register */
  123. u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */
  124. u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */
  125. u32 reserved6; /* 0x6c reserved */
  126. u32 bdcr; /* 0x70 Backup Domain Control Register */
  127. u32 csr; /* 0x74 Clock Control and Status Register */
  128. u32 reserved7; /* 0x78 reserved */
  129. u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */
  130. u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */
  131. u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */
  132. u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */
  133. u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */
  134. u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */
  135. u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */
  136. u32 apb2rstr; /* 0x98 APB2 Clock Register */
  137. u32 apb4rstr; /* 0x9c APB4 Clock Register */
  138. u32 gcr; /* 0xa0 Global Control Register */
  139. u32 reserved8; /* 0xa4 reserved */
  140. u32 d3amr; /* 0xa8 D3 Autonomous mode Register */
  141. u32 reserved9[9];/* 0xac to 0xcc reserved */
  142. u32 rsr; /* 0xd0 Reset Status Register */
  143. u32 ahb3enr; /* 0xd4 AHB3 Clock Register */
  144. u32 ahb1enr; /* 0xd8 AHB1 Clock Register */
  145. u32 ahb2enr; /* 0xdc AHB2 Clock Register */
  146. u32 ahb4enr; /* 0xe0 AHB4 Clock Register */
  147. u32 apb3enr; /* 0xe4 APB3 Clock Register */
  148. u32 apb1lenr; /* 0xe8 APB1 low Clock Register */
  149. u32 apb1henr; /* 0xec APB1 high Clock Register */
  150. u32 apb2enr; /* 0xf0 APB2 Clock Register */
  151. u32 apb4enr; /* 0xf4 APB4 Clock Register */
  152. };
  153. #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr)
  154. #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr)
  155. #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr)
  156. #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr)
  157. #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr)
  158. #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr)
  159. #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr)
  160. #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr)
  161. #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr)
  162. struct clk_cfg {
  163. u32 gate_offset;
  164. u8 gate_bit_idx;
  165. const char *name;
  166. };
  167. /*
  168. * the way all these entries are sorted in this array could seem
  169. * unlogical, but we are dependant of kernel DT_bindings,
  170. * where clocks are separate in 2 banks, peripheral clocks and
  171. * kernel clocks.
  172. */
  173. static const struct clk_cfg clk_map[] = {
  174. {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */
  175. {RCC_AHB3ENR, 30, "itcm"},
  176. {RCC_AHB3ENR, 29, "dtcm2"},
  177. {RCC_AHB3ENR, 28, "dtcm1"},
  178. {RCC_AHB3ENR, 8, "flitf"},
  179. {RCC_AHB3ENR, 5, "jpgdec"},
  180. {RCC_AHB3ENR, 4, "dma2d"},
  181. {RCC_AHB3ENR, 0, "mdma"},
  182. {RCC_AHB1ENR, 28, "usb2ulpi"},
  183. {RCC_AHB1ENR, 17, "eth1rx"},
  184. {RCC_AHB1ENR, 16, "eth1tx"},
  185. {RCC_AHB1ENR, 15, "eth1mac"},
  186. {RCC_AHB1ENR, 14, "art"},
  187. {RCC_AHB1ENR, 26, "usb1ulpi"},
  188. {RCC_AHB1ENR, 1, "dma2"},
  189. {RCC_AHB1ENR, 0, "dma1"},
  190. {RCC_AHB2ENR, 31, "d2sram3"},
  191. {RCC_AHB2ENR, 30, "d2sram2"},
  192. {RCC_AHB2ENR, 29, "d2sram1"},
  193. {RCC_AHB2ENR, 5, "hash"},
  194. {RCC_AHB2ENR, 4, "crypt"},
  195. {RCC_AHB2ENR, 0, "camitf"},
  196. {RCC_AHB4ENR, 28, "bkpram"},
  197. {RCC_AHB4ENR, 25, "hsem"},
  198. {RCC_AHB4ENR, 21, "bdma"},
  199. {RCC_AHB4ENR, 19, "crc"},
  200. {RCC_AHB4ENR, 10, "gpiok"},
  201. {RCC_AHB4ENR, 9, "gpioj"},
  202. {RCC_AHB4ENR, 8, "gpioi"},
  203. {RCC_AHB4ENR, 7, "gpioh"},
  204. {RCC_AHB4ENR, 6, "gpiog"},
  205. {RCC_AHB4ENR, 5, "gpiof"},
  206. {RCC_AHB4ENR, 4, "gpioe"},
  207. {RCC_AHB4ENR, 3, "gpiod"},
  208. {RCC_AHB4ENR, 2, "gpioc"},
  209. {RCC_AHB4ENR, 1, "gpiob"},
  210. {RCC_AHB4ENR, 0, "gpioa"},
  211. {RCC_APB3ENR, 6, "wwdg1"},
  212. {RCC_APB1LENR, 29, "dac12"},
  213. {RCC_APB1LENR, 11, "wwdg2"},
  214. {RCC_APB1LENR, 8, "tim14"},
  215. {RCC_APB1LENR, 7, "tim13"},
  216. {RCC_APB1LENR, 6, "tim12"},
  217. {RCC_APB1LENR, 5, "tim7"},
  218. {RCC_APB1LENR, 4, "tim6"},
  219. {RCC_APB1LENR, 3, "tim5"},
  220. {RCC_APB1LENR, 2, "tim4"},
  221. {RCC_APB1LENR, 1, "tim3"},
  222. {RCC_APB1LENR, 0, "tim2"},
  223. {RCC_APB1HENR, 5, "mdios"},
  224. {RCC_APB1HENR, 4, "opamp"},
  225. {RCC_APB1HENR, 1, "crs"},
  226. {RCC_APB2ENR, 18, "tim17"},
  227. {RCC_APB2ENR, 17, "tim16"},
  228. {RCC_APB2ENR, 16, "tim15"},
  229. {RCC_APB2ENR, 1, "tim8"},
  230. {RCC_APB2ENR, 0, "tim1"},
  231. {RCC_APB4ENR, 26, "tmpsens"},
  232. {RCC_APB4ENR, 16, "rtcapb"},
  233. {RCC_APB4ENR, 15, "vref"},
  234. {RCC_APB4ENR, 14, "comp12"},
  235. {RCC_APB4ENR, 1, "syscfg"},
  236. {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */
  237. {RCC_AHB3ENR, 14, "quadspi"},
  238. {RCC_AHB3ENR, 12, "fmc"},
  239. {RCC_AHB1ENR, 27, "usb2otg"},
  240. {RCC_AHB1ENR, 25, "usb1otg"},
  241. {RCC_AHB1ENR, 5, "adc12"},
  242. {RCC_AHB2ENR, 9, "sdmmc2"},
  243. {RCC_AHB2ENR, 6, "rng"},
  244. {RCC_AHB4ENR, 24, "adc3"},
  245. {RCC_APB3ENR, 4, "dsi"},
  246. {RCC_APB3ENR, 3, "ltdc"},
  247. {RCC_APB1LENR, 31, "usart8"},
  248. {RCC_APB1LENR, 30, "usart7"},
  249. {RCC_APB1LENR, 27, "hdmicec"},
  250. {RCC_APB1LENR, 23, "i2c3"},
  251. {RCC_APB1LENR, 22, "i2c2"},
  252. {RCC_APB1LENR, 21, "i2c1"},
  253. {RCC_APB1LENR, 20, "uart5"},
  254. {RCC_APB1LENR, 19, "uart4"},
  255. {RCC_APB1LENR, 18, "usart3"},
  256. {RCC_APB1LENR, 17, "usart2"},
  257. {RCC_APB1LENR, 16, "spdifrx"},
  258. {RCC_APB1LENR, 15, "spi3"},
  259. {RCC_APB1LENR, 14, "spi2"},
  260. {RCC_APB1LENR, 9, "lptim1"},
  261. {RCC_APB1HENR, 8, "fdcan"},
  262. {RCC_APB1HENR, 2, "swp"},
  263. {RCC_APB2ENR, 29, "hrtim"},
  264. {RCC_APB2ENR, 28, "dfsdm1"},
  265. {RCC_APB2ENR, 24, "sai3"},
  266. {RCC_APB2ENR, 23, "sai2"},
  267. {RCC_APB2ENR, 22, "sai1"},
  268. {RCC_APB2ENR, 20, "spi5"},
  269. {RCC_APB2ENR, 13, "spi4"},
  270. {RCC_APB2ENR, 12, "spi1"},
  271. {RCC_APB2ENR, 5, "usart6"},
  272. {RCC_APB2ENR, 4, "usart1"},
  273. {RCC_APB4ENR, 21, "sai4a"},
  274. {RCC_APB4ENR, 21, "sai4b"},
  275. {RCC_APB4ENR, 12, "lptim5"},
  276. {RCC_APB4ENR, 11, "lptim4"},
  277. {RCC_APB4ENR, 10, "lptim3"},
  278. {RCC_APB4ENR, 9, "lptim2"},
  279. {RCC_APB4ENR, 7, "i2c4"},
  280. {RCC_APB4ENR, 5, "spi6"},
  281. {RCC_APB4ENR, 3, "lpuart1"},
  282. };
  283. struct stm32_clk {
  284. struct stm32_rcc_regs *rcc_base;
  285. struct regmap *pwr_regmap;
  286. };
  287. struct pll_psc {
  288. u8 divm;
  289. u16 divn;
  290. u8 divp;
  291. u8 divq;
  292. u8 divr;
  293. };
  294. /*
  295. * OSC_HSE = 25 MHz
  296. * VCO = 500MHz
  297. * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz
  298. */
  299. struct pll_psc sys_pll_psc = {
  300. .divm = 4,
  301. .divn = 80,
  302. .divp = 2,
  303. .divq = 2,
  304. .divr = 2,
  305. };
  306. enum apb {
  307. APB1,
  308. APB2,
  309. };
  310. int configure_clocks(struct udevice *dev)
  311. {
  312. struct stm32_clk *priv = dev_get_priv(dev);
  313. struct stm32_rcc_regs *regs = priv->rcc_base;
  314. uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0);
  315. uint32_t pllckselr = 0;
  316. uint32_t pll1divr = 0;
  317. uint32_t pllcfgr = 0;
  318. /* Switch on HSI */
  319. setbits_le32(&regs->cr, RCC_CR_HSION);
  320. while (!(readl(&regs->cr) & RCC_CR_HSIRDY))
  321. ;
  322. /* Reset CFGR, now HSI is the default system clock */
  323. writel(0, &regs->cfgr);
  324. /* Set all kernel domain clock registers to reset value*/
  325. writel(0x0, &regs->d1ccipr);
  326. writel(0x0, &regs->d2ccip1r);
  327. writel(0x0, &regs->d2ccip2r);
  328. /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */
  329. clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK,
  330. VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT);
  331. /* Lock supply configuration update */
  332. clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN);
  333. while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY))
  334. ;
  335. /* disable HSE to configure it */
  336. clrbits_le32(&regs->cr, RCC_CR_HSEON);
  337. while ((readl(&regs->cr) & RCC_CR_HSERDY))
  338. ;
  339. /* clear HSE bypass and set it ON */
  340. clrbits_le32(&regs->cr, RCC_CR_HSEBYP);
  341. /* Switch on HSE */
  342. setbits_le32(&regs->cr, RCC_CR_HSEON);
  343. while (!(readl(&regs->cr) & RCC_CR_HSERDY))
  344. ;
  345. /* pll setup, disable it */
  346. clrbits_le32(&regs->cr, RCC_CR_PLL1ON);
  347. while ((readl(&regs->cr) & RCC_CR_PLL1RDY))
  348. ;
  349. /* Select HSE as PLL clock source */
  350. pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE;
  351. pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT;
  352. writel(pllckselr, &regs->pllckselr);
  353. pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT;
  354. pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT;
  355. pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT;
  356. pll1divr |= (sys_pll_psc.divn - 1);
  357. writel(pll1divr, &regs->pll1divr);
  358. pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT;
  359. pllcfgr |= RCC_PLLCFGR_DIVP1EN;
  360. pllcfgr |= RCC_PLLCFGR_DIVQ1EN;
  361. pllcfgr |= RCC_PLLCFGR_DIVR1EN;
  362. writel(pllcfgr, &regs->pllcfgr);
  363. /* pll setup, enable it */
  364. setbits_le32(&regs->cr, RCC_CR_PLL1ON);
  365. /* set HPRE (/2) DI clk --> 125MHz */
  366. clrsetbits_le32(&regs->d1cfgr, RCC_D1CFGR_HPRE_MASK,
  367. RCC_D1CFGR_HPRE_DIV2);
  368. /* select PLL1 as system clock source (sys_ck)*/
  369. clrsetbits_le32(&regs->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1);
  370. while ((readl(&regs->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1)
  371. ;
  372. /* sdram: use pll1_q as fmc_k clk */
  373. clrsetbits_le32(&regs->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK,
  374. FMCSRC_PLL1_Q_CK);
  375. return 0;
  376. }
  377. static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs)
  378. {
  379. u32 divider;
  380. /* get HSI divider value */
  381. divider = readl(&regs->cr) & RCC_CR_HSIDIV_MASK;
  382. divider = divider >> RCC_CR_HSIDIV_SHIFT;
  383. return divider;
  384. };
  385. enum pllsrc {
  386. HSE,
  387. LSE,
  388. HSI,
  389. CSI,
  390. I2S,
  391. TIMER,
  392. PLLSRC_NB,
  393. };
  394. static const char * const pllsrc_name[PLLSRC_NB] = {
  395. [HSE] = "clk-hse",
  396. [LSE] = "clk-lse",
  397. [HSI] = "clk-hsi",
  398. [CSI] = "clk-csi",
  399. [I2S] = "clk-i2s",
  400. [TIMER] = "timer-clk"
  401. };
  402. static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc)
  403. {
  404. struct clk clk;
  405. struct udevice *fixed_clock_dev = NULL;
  406. u32 divider;
  407. int ret;
  408. const char *name = pllsrc_name[pllsrc];
  409. log_debug("pllsrc name %s\n", name);
  410. clk.id = 0;
  411. ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev);
  412. if (ret) {
  413. log_err("Can't find clk %s (%d)", name, ret);
  414. return 0;
  415. }
  416. ret = clk_request(fixed_clock_dev, &clk);
  417. if (ret) {
  418. log_err("Can't request %s clk (%d)", name, ret);
  419. return 0;
  420. }
  421. divider = 0;
  422. if (pllsrc == HSI)
  423. divider = stm32_get_HSI_divider(regs);
  424. log_debug("divider %d rate %ld\n", divider, clk_get_rate(&clk));
  425. return clk_get_rate(&clk) >> divider;
  426. };
  427. enum pll1_output {
  428. PLL1_P_CK,
  429. PLL1_Q_CK,
  430. PLL1_R_CK,
  431. };
  432. static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs,
  433. enum pll1_output output)
  434. {
  435. ulong pllsrc = 0;
  436. u32 divm1, divn1, divp1, divq1, divr1, fracn1;
  437. ulong vco, rate;
  438. /* get the PLLSRC */
  439. switch (readl(&regs->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) {
  440. case RCC_PLLCKSELR_PLLSRC_HSI:
  441. pllsrc = stm32_get_rate(regs, HSI);
  442. break;
  443. case RCC_PLLCKSELR_PLLSRC_CSI:
  444. pllsrc = stm32_get_rate(regs, CSI);
  445. break;
  446. case RCC_PLLCKSELR_PLLSRC_HSE:
  447. pllsrc = stm32_get_rate(regs, HSE);
  448. break;
  449. case RCC_PLLCKSELR_PLLSRC_NO_CLK:
  450. /* shouldn't happen */
  451. log_err("wrong value for RCC_PLLCKSELR register\n");
  452. pllsrc = 0;
  453. break;
  454. }
  455. /* pllsrc = 0 ? no need to go ahead */
  456. if (!pllsrc)
  457. return pllsrc;
  458. /* get divm1, divp1, divn1 and divr1 */
  459. divm1 = readl(&regs->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK;
  460. divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT;
  461. divn1 = (readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1;
  462. divp1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK;
  463. divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1;
  464. divq1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK;
  465. divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1;
  466. divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK;
  467. divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1;
  468. fracn1 = readl(&regs->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK;
  469. fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT;
  470. vco = (pllsrc / divm1) * divn1;
  471. rate = (pllsrc * fracn1) / (divm1 * 8192);
  472. log_debug("divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n",
  473. divm1, divn1, divp1, divq1, divr1);
  474. log_debug("fracn1 = %d vco = %ld rate = %ld\n",
  475. fracn1, vco, rate);
  476. switch (output) {
  477. case PLL1_P_CK:
  478. return (vco + rate) / divp1;
  479. break;
  480. case PLL1_Q_CK:
  481. return (vco + rate) / divq1;
  482. break;
  483. case PLL1_R_CK:
  484. return (vco + rate) / divr1;
  485. break;
  486. }
  487. return -EINVAL;
  488. }
  489. static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb)
  490. {
  491. u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
  492. u32 d2cfgr = readl(&regs->d2cfgr);
  493. if (apb == APB1) {
  494. if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED)
  495. /* get D2 domain APB1 prescaler */
  496. return prescaler_table[
  497. ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER)
  498. >> RCC_D2CFGR_D2PPRE1_SHIFT)];
  499. } else { /* APB2 */
  500. if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED)
  501. /* get D2 domain APB2 prescaler */
  502. return prescaler_table[
  503. ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER)
  504. >> RCC_D2CFGR_D2PPRE2_SHIFT)];
  505. }
  506. return 1;
  507. };
  508. static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk,
  509. enum apb apb)
  510. {
  511. struct stm32_rcc_regs *regs = priv->rcc_base;
  512. u32 psc = stm32_get_apb_psc(regs, apb);
  513. if (readl(&regs->cfgr) & RCC_CFGR_TIMPRE)
  514. /*
  515. * if APB prescaler is configured to a
  516. * division factor of 1, 2 or 4
  517. */
  518. switch (psc) {
  519. case 1:
  520. case 2:
  521. case 4:
  522. return sysclk;
  523. case 8:
  524. return sysclk / 2;
  525. case 16:
  526. return sysclk / 4;
  527. default:
  528. log_err("unexpected prescaler value (%d)\n", psc);
  529. return 0;
  530. }
  531. else
  532. switch (psc) {
  533. case 1:
  534. return sysclk;
  535. case 2:
  536. case 4:
  537. case 8:
  538. case 16:
  539. return sysclk / psc;
  540. default:
  541. log_err("unexpected prescaler value (%d)\n", psc);
  542. return 0;
  543. }
  544. };
  545. static ulong stm32_clk_get_rate(struct clk *clk)
  546. {
  547. struct stm32_clk *priv = dev_get_priv(clk->dev);
  548. struct stm32_rcc_regs *regs = priv->rcc_base;
  549. ulong sysclk = 0;
  550. u32 gate_offset;
  551. u32 d1cfgr, d3cfgr;
  552. /* prescaler table lookups for clock computation */
  553. u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512};
  554. u8 source, idx;
  555. /*
  556. * get system clock (sys_ck) source
  557. * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck
  558. */
  559. source = readl(&regs->cfgr) & RCC_CFGR_SW_MASK;
  560. switch (source) {
  561. case RCC_CFGR_SW_PLL1:
  562. sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK);
  563. break;
  564. case RCC_CFGR_SW_HSE:
  565. sysclk = stm32_get_rate(regs, HSE);
  566. break;
  567. case RCC_CFGR_SW_CSI:
  568. sysclk = stm32_get_rate(regs, CSI);
  569. break;
  570. case RCC_CFGR_SW_HSI:
  571. sysclk = stm32_get_rate(regs, HSI);
  572. break;
  573. }
  574. /* sysclk = 0 ? no need to go ahead */
  575. if (!sysclk)
  576. return sysclk;
  577. dev_dbg(clk->dev, "system clock: source = %d freq = %ld\n",
  578. source, sysclk);
  579. d1cfgr = readl(&regs->d1cfgr);
  580. if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) {
  581. /* get D1 domain Core prescaler */
  582. idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >>
  583. RCC_D1CFGR_D1CPRE_SHIFT;
  584. sysclk = sysclk / prescaler_table[idx];
  585. }
  586. if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) {
  587. /* get D1 domain AHB prescaler */
  588. idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER;
  589. sysclk = sysclk / prescaler_table[idx];
  590. }
  591. gate_offset = clk_map[clk->id].gate_offset;
  592. dev_dbg(clk->dev, "clk->id=%ld gate_offset=0x%x sysclk=%ld\n",
  593. clk->id, gate_offset, sysclk);
  594. switch (gate_offset) {
  595. case RCC_AHB3ENR:
  596. case RCC_AHB1ENR:
  597. case RCC_AHB2ENR:
  598. case RCC_AHB4ENR:
  599. return sysclk;
  600. break;
  601. case RCC_APB3ENR:
  602. if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) {
  603. /* get D1 domain APB3 prescaler */
  604. idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >>
  605. RCC_D1CFGR_D1PPRE_SHIFT;
  606. sysclk = sysclk / prescaler_table[idx];
  607. }
  608. dev_dbg(clk->dev, "system clock: freq after APB3 prescaler = %ld\n",
  609. sysclk);
  610. return sysclk;
  611. break;
  612. case RCC_APB4ENR:
  613. d3cfgr = readl(&regs->d3cfgr);
  614. if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) {
  615. /* get D3 domain APB4 prescaler */
  616. idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >>
  617. RCC_D3CFGR_D3PPRE_SHIFT;
  618. sysclk = sysclk / prescaler_table[idx];
  619. }
  620. dev_dbg(clk->dev,
  621. "system clock: freq after APB4 prescaler = %ld\n",
  622. sysclk);
  623. return sysclk;
  624. break;
  625. case RCC_APB1LENR:
  626. case RCC_APB1HENR:
  627. /* special case for GPT timers */
  628. switch (clk->id) {
  629. case TIM14_CK:
  630. case TIM13_CK:
  631. case TIM12_CK:
  632. case TIM7_CK:
  633. case TIM6_CK:
  634. case TIM5_CK:
  635. case TIM4_CK:
  636. case TIM3_CK:
  637. case TIM2_CK:
  638. return stm32_get_timer_rate(priv, sysclk, APB1);
  639. }
  640. dev_dbg(clk->dev,
  641. "system clock: freq after APB1 prescaler = %ld\n",
  642. sysclk);
  643. return (sysclk / stm32_get_apb_psc(regs, APB1));
  644. break;
  645. case RCC_APB2ENR:
  646. /* special case for timers */
  647. switch (clk->id) {
  648. case TIM17_CK:
  649. case TIM16_CK:
  650. case TIM15_CK:
  651. case TIM8_CK:
  652. case TIM1_CK:
  653. return stm32_get_timer_rate(priv, sysclk, APB2);
  654. }
  655. dev_dbg(clk->dev,
  656. "system clock: freq after APB2 prescaler = %ld\n",
  657. sysclk);
  658. return (sysclk / stm32_get_apb_psc(regs, APB2));
  659. break;
  660. default:
  661. dev_err(clk->dev, "unexpected gate_offset value (0x%x)\n",
  662. gate_offset);
  663. return -EINVAL;
  664. break;
  665. }
  666. }
  667. static int stm32_clk_enable(struct clk *clk)
  668. {
  669. struct stm32_clk *priv = dev_get_priv(clk->dev);
  670. struct stm32_rcc_regs *regs = priv->rcc_base;
  671. u32 gate_offset;
  672. u32 gate_bit_index;
  673. unsigned long clk_id = clk->id;
  674. gate_offset = clk_map[clk_id].gate_offset;
  675. gate_bit_index = clk_map[clk_id].gate_bit_idx;
  676. dev_dbg(clk->dev, "clkid=%ld gate offset=0x%x bit_index=%d name=%s\n",
  677. clk->id, gate_offset, gate_bit_index,
  678. clk_map[clk_id].name);
  679. setbits_le32(&regs->cr + (gate_offset / 4), BIT(gate_bit_index));
  680. return 0;
  681. }
  682. static int stm32_clk_probe(struct udevice *dev)
  683. {
  684. struct stm32_clk *priv = dev_get_priv(dev);
  685. struct udevice *syscon;
  686. fdt_addr_t addr;
  687. int err;
  688. addr = dev_read_addr(dev);
  689. if (addr == FDT_ADDR_T_NONE)
  690. return -EINVAL;
  691. priv->rcc_base = (struct stm32_rcc_regs *)addr;
  692. /* get corresponding syscon phandle */
  693. err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
  694. "st,syscfg", &syscon);
  695. if (err) {
  696. dev_err(dev, "unable to find syscon device\n");
  697. return err;
  698. }
  699. priv->pwr_regmap = syscon_get_regmap(syscon);
  700. if (!priv->pwr_regmap) {
  701. dev_err(dev, "unable to find regmap\n");
  702. return -ENODEV;
  703. }
  704. configure_clocks(dev);
  705. return 0;
  706. }
  707. static int stm32_clk_of_xlate(struct clk *clk,
  708. struct ofnode_phandle_args *args)
  709. {
  710. if (args->args_count != 1) {
  711. dev_dbg(clk->dev, "Invaild args_count: %d\n", args->args_count);
  712. return -EINVAL;
  713. }
  714. if (args->args_count) {
  715. clk->id = args->args[0];
  716. /*
  717. * this computation convert DT clock index which is used to
  718. * point into 2 separate clock arrays (peripheral and kernel
  719. * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h)
  720. * into index to point into only one array where peripheral
  721. * and kernel clocks are consecutive
  722. */
  723. if (clk->id >= KERN_BANK) {
  724. clk->id -= KERN_BANK;
  725. clk->id += LAST_PERIF_BANK - PERIF_BANK + 1;
  726. } else {
  727. clk->id -= PERIF_BANK;
  728. }
  729. } else {
  730. clk->id = 0;
  731. }
  732. dev_dbg(clk->dev, "clk->id %ld\n", clk->id);
  733. return 0;
  734. }
  735. static struct clk_ops stm32_clk_ops = {
  736. .of_xlate = stm32_clk_of_xlate,
  737. .enable = stm32_clk_enable,
  738. .get_rate = stm32_clk_get_rate,
  739. };
  740. U_BOOT_DRIVER(stm32h7_clk) = {
  741. .name = "stm32h7_rcc_clock",
  742. .id = UCLASS_CLK,
  743. .ops = &stm32_clk_ops,
  744. .probe = stm32_clk_probe,
  745. .priv_auto = sizeof(struct stm32_clk),
  746. .flags = DM_FLAG_PRE_RELOC,
  747. };