clk_fixed_factor.c 1.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 Western Digital Corporation or its affiliates.
  4. *
  5. * Author: Anup Patel <anup.patel@wdc.com>
  6. */
  7. #include <common.h>
  8. #include <clk-uclass.h>
  9. #include <div64.h>
  10. #include <dm.h>
  11. #include <linux/err.h>
  12. struct clk_fixed_factor {
  13. struct clk parent;
  14. unsigned int div;
  15. unsigned int mult;
  16. };
  17. #define to_clk_fixed_factor(dev) \
  18. ((struct clk_fixed_factor *)dev_get_plat(dev))
  19. static ulong clk_fixed_factor_get_rate(struct clk *clk)
  20. {
  21. uint64_t rate;
  22. struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
  23. rate = clk_get_rate(&ff->parent);
  24. if (IS_ERR_VALUE(rate))
  25. return rate;
  26. do_div(rate, ff->div);
  27. return rate * ff->mult;
  28. }
  29. const struct clk_ops clk_fixed_factor_ops = {
  30. .get_rate = clk_fixed_factor_get_rate,
  31. };
  32. static int clk_fixed_factor_of_to_plat(struct udevice *dev)
  33. {
  34. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  35. int err;
  36. struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
  37. err = clk_get_by_index(dev, 0, &ff->parent);
  38. if (err)
  39. return err;
  40. ff->div = dev_read_u32_default(dev, "clock-div", 1);
  41. ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
  42. #endif
  43. return 0;
  44. }
  45. static const struct udevice_id clk_fixed_factor_match[] = {
  46. {
  47. .compatible = "fixed-factor-clock",
  48. },
  49. { /* sentinel */ }
  50. };
  51. U_BOOT_DRIVER(clk_fixed_factor) = {
  52. .name = "fixed_factor_clock",
  53. .id = UCLASS_CLK,
  54. .of_match = clk_fixed_factor_match,
  55. .of_to_plat = clk_fixed_factor_of_to_plat,
  56. .plat_auto = sizeof(struct clk_fixed_factor),
  57. .ops = &clk_fixed_factor_ops,
  58. };