clk-mux.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  7. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  8. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  9. *
  10. * Simple multiplexer clock implementation
  11. */
  12. /*
  13. * U-Boot CCF porting node:
  14. *
  15. * The Linux kernel - as of tag: 5.0-rc3 is using also the imx_clk_fixup_mux()
  16. * version of CCF mux. It is used on e.g. imx6q to provide fixes (like
  17. * imx_cscmr1_fixup) for broken HW.
  18. *
  19. * At least for IMX6Q (but NOT IMX6QP) it is important when we set the parent
  20. * clock.
  21. */
  22. #include <common.h>
  23. #include <clk.h>
  24. #include <clk-uclass.h>
  25. #include <dm/device.h>
  26. #include <dm/devres.h>
  27. #include <dm/uclass.h>
  28. #include <linux/bitops.h>
  29. #include <malloc.h>
  30. #include <asm/io.h>
  31. #include <linux/clk-provider.h>
  32. #include <linux/err.h>
  33. #include "clk.h"
  34. #define UBOOT_DM_CLK_CCF_MUX "ccf_clk_mux"
  35. int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
  36. unsigned int val)
  37. {
  38. struct clk_mux *mux = to_clk_mux(clk);
  39. int num_parents = mux->num_parents;
  40. if (table) {
  41. int i;
  42. for (i = 0; i < num_parents; i++)
  43. if (table[i] == val)
  44. return i;
  45. return -EINVAL;
  46. }
  47. if (val && (flags & CLK_MUX_INDEX_BIT))
  48. val = ffs(val) - 1;
  49. if (val && (flags & CLK_MUX_INDEX_ONE))
  50. val--;
  51. if (val >= num_parents)
  52. return -EINVAL;
  53. return val;
  54. }
  55. unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
  56. {
  57. unsigned int val = index;
  58. if (table) {
  59. val = table[index];
  60. } else {
  61. if (flags & CLK_MUX_INDEX_BIT)
  62. val = 1 << index;
  63. if (flags & CLK_MUX_INDEX_ONE)
  64. val++;
  65. }
  66. return val;
  67. }
  68. u8 clk_mux_get_parent(struct clk *clk)
  69. {
  70. struct clk_mux *mux = to_clk_mux(clk);
  71. u32 val;
  72. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  73. val = mux->io_mux_val;
  74. #else
  75. val = readl(mux->reg);
  76. #endif
  77. val >>= mux->shift;
  78. val &= mux->mask;
  79. return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
  80. }
  81. static int clk_fetch_parent_index(struct clk *clk,
  82. struct clk *parent)
  83. {
  84. struct clk_mux *mux = to_clk_mux(clk);
  85. int i;
  86. if (!parent)
  87. return -EINVAL;
  88. for (i = 0; i < mux->num_parents; i++) {
  89. if (!strcmp(parent->dev->name, mux->parent_names[i]))
  90. return i;
  91. }
  92. return -EINVAL;
  93. }
  94. static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
  95. {
  96. struct clk_mux *mux = to_clk_mux(clk);
  97. int index;
  98. u32 val;
  99. u32 reg;
  100. index = clk_fetch_parent_index(clk, parent);
  101. if (index < 0) {
  102. printf("Could not fetch index\n");
  103. return index;
  104. }
  105. val = clk_mux_index_to_val(mux->table, mux->flags, index);
  106. if (mux->flags & CLK_MUX_HIWORD_MASK) {
  107. reg = mux->mask << (mux->shift + 16);
  108. } else {
  109. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  110. reg = mux->io_mux_val;
  111. #else
  112. reg = readl(mux->reg);
  113. #endif
  114. reg &= ~(mux->mask << mux->shift);
  115. }
  116. val = val << mux->shift;
  117. reg |= val;
  118. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  119. mux->io_mux_val = reg;
  120. #else
  121. writel(reg, mux->reg);
  122. #endif
  123. return 0;
  124. }
  125. const struct clk_ops clk_mux_ops = {
  126. .get_rate = clk_generic_get_rate,
  127. .set_parent = clk_mux_set_parent,
  128. };
  129. struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
  130. const char * const *parent_names, u8 num_parents,
  131. unsigned long flags,
  132. void __iomem *reg, u8 shift, u32 mask,
  133. u8 clk_mux_flags, u32 *table)
  134. {
  135. struct clk_mux *mux;
  136. struct clk *clk;
  137. u8 width = 0;
  138. int ret;
  139. if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
  140. width = fls(mask) - ffs(mask) + 1;
  141. if (width + shift > 16) {
  142. pr_err("mux value exceeds LOWORD field\n");
  143. return ERR_PTR(-EINVAL);
  144. }
  145. }
  146. /* allocate the mux */
  147. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  148. if (!mux)
  149. return ERR_PTR(-ENOMEM);
  150. /* U-boot specific assignments */
  151. mux->parent_names = parent_names;
  152. mux->num_parents = num_parents;
  153. /* struct clk_mux assignments */
  154. mux->reg = reg;
  155. mux->shift = shift;
  156. mux->mask = mask;
  157. mux->flags = clk_mux_flags;
  158. mux->table = table;
  159. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  160. mux->io_mux_val = *(u32 *)reg;
  161. #endif
  162. clk = &mux->clk;
  163. clk->flags = flags;
  164. /*
  165. * Read the current mux setup - so we assign correct parent.
  166. *
  167. * Changing parent would require changing internals of udevice struct
  168. * for the corresponding clock (to do that define .set_parent() method).
  169. */
  170. ret = clk_register(clk, UBOOT_DM_CLK_CCF_MUX, name,
  171. parent_names[clk_mux_get_parent(clk)]);
  172. if (ret) {
  173. kfree(mux);
  174. return ERR_PTR(ret);
  175. }
  176. return clk;
  177. }
  178. struct clk *clk_register_mux_table(struct device *dev, const char *name,
  179. const char * const *parent_names, u8 num_parents,
  180. unsigned long flags,
  181. void __iomem *reg, u8 shift, u32 mask,
  182. u8 clk_mux_flags, u32 *table)
  183. {
  184. struct clk *clk;
  185. clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
  186. flags, reg, shift, mask, clk_mux_flags,
  187. table);
  188. if (IS_ERR(clk))
  189. return ERR_CAST(clk);
  190. return clk;
  191. }
  192. struct clk *clk_register_mux(struct device *dev, const char *name,
  193. const char * const *parent_names, u8 num_parents,
  194. unsigned long flags,
  195. void __iomem *reg, u8 shift, u8 width,
  196. u8 clk_mux_flags)
  197. {
  198. u32 mask = BIT(width) - 1;
  199. return clk_register_mux_table(dev, name, parent_names, num_parents,
  200. flags, reg, shift, mask, clk_mux_flags,
  201. NULL);
  202. }
  203. U_BOOT_DRIVER(ccf_clk_mux) = {
  204. .name = UBOOT_DM_CLK_CCF_MUX,
  205. .id = UCLASS_CLK,
  206. .ops = &clk_mux_ops,
  207. .flags = DM_FLAG_PRE_RELOC,
  208. };