clk-divider.c 6.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 DENX Software Engineering
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  7. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  8. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  9. *
  10. */
  11. #include <common.h>
  12. #include <asm/io.h>
  13. #include <malloc.h>
  14. #include <clk-uclass.h>
  15. #include <dm/device.h>
  16. #include <dm/devres.h>
  17. #include <dm/uclass.h>
  18. #include <dm/lists.h>
  19. #include <dm/device-internal.h>
  20. #include <linux/bug.h>
  21. #include <linux/clk-provider.h>
  22. #include <linux/err.h>
  23. #include <linux/log2.h>
  24. #include <div64.h>
  25. #include <clk.h>
  26. #include "clk.h"
  27. #define UBOOT_DM_CLK_CCF_DIVIDER "ccf_clk_divider"
  28. unsigned int clk_divider_get_table_div(const struct clk_div_table *table,
  29. unsigned int val)
  30. {
  31. const struct clk_div_table *clkt;
  32. for (clkt = table; clkt->div; clkt++)
  33. if (clkt->val == val)
  34. return clkt->div;
  35. return 0;
  36. }
  37. static unsigned int _get_div(const struct clk_div_table *table,
  38. unsigned int val, unsigned long flags, u8 width)
  39. {
  40. if (flags & CLK_DIVIDER_ONE_BASED)
  41. return val;
  42. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  43. return 1 << val;
  44. if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  45. return val ? val : clk_div_mask(width) + 1;
  46. if (table)
  47. return clk_divider_get_table_div(table, val);
  48. return val + 1;
  49. }
  50. unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
  51. unsigned int val,
  52. const struct clk_div_table *table,
  53. unsigned long flags, unsigned long width)
  54. {
  55. unsigned int div;
  56. div = _get_div(table, val, flags, width);
  57. if (!div) {
  58. WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
  59. "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  60. clk_hw_get_name(hw));
  61. return parent_rate;
  62. }
  63. return DIV_ROUND_UP_ULL((u64)parent_rate, div);
  64. }
  65. static ulong clk_divider_recalc_rate(struct clk *clk)
  66. {
  67. struct clk_divider *divider = to_clk_divider(clk);
  68. unsigned long parent_rate = clk_get_parent_rate(clk);
  69. unsigned int val;
  70. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  71. val = divider->io_divider_val;
  72. #else
  73. val = readl(divider->reg);
  74. #endif
  75. val >>= divider->shift;
  76. val &= clk_div_mask(divider->width);
  77. return divider_recalc_rate(clk, parent_rate, val, divider->table,
  78. divider->flags, divider->width);
  79. }
  80. bool clk_divider_is_valid_table_div(const struct clk_div_table *table,
  81. unsigned int div)
  82. {
  83. const struct clk_div_table *clkt;
  84. for (clkt = table; clkt->div; clkt++)
  85. if (clkt->div == div)
  86. return true;
  87. return false;
  88. }
  89. bool clk_divider_is_valid_div(const struct clk_div_table *table,
  90. unsigned int div, unsigned long flags)
  91. {
  92. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  93. return is_power_of_2(div);
  94. if (table)
  95. return clk_divider_is_valid_table_div(table, div);
  96. return true;
  97. }
  98. unsigned int clk_divider_get_table_val(const struct clk_div_table *table,
  99. unsigned int div)
  100. {
  101. const struct clk_div_table *clkt;
  102. for (clkt = table; clkt->div; clkt++)
  103. if (clkt->div == div)
  104. return clkt->val;
  105. return 0;
  106. }
  107. static unsigned int _get_val(const struct clk_div_table *table,
  108. unsigned int div, unsigned long flags, u8 width)
  109. {
  110. if (flags & CLK_DIVIDER_ONE_BASED)
  111. return div;
  112. if (flags & CLK_DIVIDER_POWER_OF_TWO)
  113. return __ffs(div);
  114. if (flags & CLK_DIVIDER_MAX_AT_ZERO)
  115. return (div == clk_div_mask(width) + 1) ? 0 : div;
  116. if (table)
  117. return clk_divider_get_table_val(table, div);
  118. return div - 1;
  119. }
  120. int divider_get_val(unsigned long rate, unsigned long parent_rate,
  121. const struct clk_div_table *table, u8 width,
  122. unsigned long flags)
  123. {
  124. unsigned int div, value;
  125. div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
  126. if (!clk_divider_is_valid_div(table, div, flags))
  127. return -EINVAL;
  128. value = _get_val(table, div, flags, width);
  129. return min_t(unsigned int, value, clk_div_mask(width));
  130. }
  131. static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
  132. {
  133. struct clk_divider *divider = to_clk_divider(clk);
  134. unsigned long parent_rate = clk_get_parent_rate(clk);
  135. int value;
  136. u32 val;
  137. value = divider_get_val(rate, parent_rate, divider->table,
  138. divider->width, divider->flags);
  139. if (value < 0)
  140. return value;
  141. if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
  142. val = clk_div_mask(divider->width) << (divider->shift + 16);
  143. } else {
  144. val = readl(divider->reg);
  145. val &= ~(clk_div_mask(divider->width) << divider->shift);
  146. }
  147. val |= (u32)value << divider->shift;
  148. writel(val, divider->reg);
  149. return clk_get_rate(clk);
  150. }
  151. const struct clk_ops clk_divider_ops = {
  152. .get_rate = clk_divider_recalc_rate,
  153. .set_rate = clk_divider_set_rate,
  154. };
  155. static struct clk *_register_divider(struct device *dev, const char *name,
  156. const char *parent_name, unsigned long flags,
  157. void __iomem *reg, u8 shift, u8 width,
  158. u8 clk_divider_flags, const struct clk_div_table *table)
  159. {
  160. struct clk_divider *div;
  161. struct clk *clk;
  162. int ret;
  163. if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
  164. if (width + shift > 16) {
  165. pr_warn("divider value exceeds LOWORD field\n");
  166. return ERR_PTR(-EINVAL);
  167. }
  168. }
  169. /* allocate the divider */
  170. div = kzalloc(sizeof(*div), GFP_KERNEL);
  171. if (!div)
  172. return ERR_PTR(-ENOMEM);
  173. /* struct clk_divider assignments */
  174. div->reg = reg;
  175. div->shift = shift;
  176. div->width = width;
  177. div->flags = clk_divider_flags;
  178. div->table = table;
  179. #if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
  180. div->io_divider_val = *(u32 *)reg;
  181. #endif
  182. /* register the clock */
  183. clk = &div->clk;
  184. clk->flags = flags;
  185. ret = clk_register(clk, UBOOT_DM_CLK_CCF_DIVIDER, name, parent_name);
  186. if (ret) {
  187. kfree(div);
  188. return ERR_PTR(ret);
  189. }
  190. return clk;
  191. }
  192. struct clk *clk_register_divider(struct device *dev, const char *name,
  193. const char *parent_name, unsigned long flags,
  194. void __iomem *reg, u8 shift, u8 width,
  195. u8 clk_divider_flags)
  196. {
  197. struct clk *clk;
  198. clk = _register_divider(dev, name, parent_name, flags, reg, shift,
  199. width, clk_divider_flags, NULL);
  200. if (IS_ERR(clk))
  201. return ERR_CAST(clk);
  202. return clk;
  203. }
  204. U_BOOT_DRIVER(ccf_clk_divider) = {
  205. .name = UBOOT_DM_CLK_CCF_DIVIDER,
  206. .id = UCLASS_CLK,
  207. .ops = &clk_divider_ops,
  208. .flags = DM_FLAG_PRE_RELOC,
  209. };