sam9x60.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
  4. *
  5. * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
  6. *
  7. * Based on sam9x60.c on Linux.
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dt-bindings/clk/at91.h>
  13. #include <linux/clk-provider.h>
  14. #include "pmc.h"
  15. /**
  16. * Clock identifiers to be used in conjunction with macros like
  17. * AT91_TO_CLK_ID()
  18. *
  19. * @ID_MD_SLCK: TD slow clock identifier
  20. * @ID_TD_SLCK: MD slow clock identifier
  21. * @ID_MAIN_XTAL: Main Xtal clock identifier
  22. * @ID_MAIN_RC: Main RC clock identifier
  23. * @ID_MAIN_RC_OSC: Main RC Oscillator clock identifier
  24. * @ID_MAIN_OSC: Main Oscillator clock identifier
  25. * @ID_MAINCK: MAINCK clock identifier
  26. * @ID_PLL_U_FRAC: UPLL fractional clock identifier
  27. * @ID_PLL_U_DIV: UPLL divider clock identifier
  28. * @ID_PLL_A_FRAC: APLL fractional clock identifier
  29. * @ID_PLL_A_DIV: APLL divider clock identifier
  30. * @ID_MCK: MCK clock identifier
  31. * @ID_UTMI: UTMI clock identifier
  32. * @ID_PROG0: Programmable 0 clock identifier
  33. * @ID_PROG1: Programmable 1 clock identifier
  34. * @ID_PCK0: PCK0 system clock identifier
  35. * @ID_PCK1: PCK1 system clock identifier
  36. * @ID_DDR: DDR system clock identifier
  37. * @ID_QSPI: QSPI system clock identifier
  38. *
  39. * Note: if changing the values of this enums please sync them with
  40. * device tree
  41. */
  42. enum pmc_clk_ids {
  43. ID_MD_SLCK = 0,
  44. ID_TD_SLCK = 1,
  45. ID_MAIN_XTAL = 2,
  46. ID_MAIN_RC = 3,
  47. ID_MAIN_RC_OSC = 4,
  48. ID_MAIN_OSC = 5,
  49. ID_MAINCK = 6,
  50. ID_PLL_U_FRAC = 7,
  51. ID_PLL_U_DIV = 8,
  52. ID_PLL_A_FRAC = 9,
  53. ID_PLL_A_DIV = 10,
  54. ID_MCK = 11,
  55. ID_UTMI = 12,
  56. ID_PROG0 = 13,
  57. ID_PROG1 = 14,
  58. ID_PCK0 = 15,
  59. ID_PCK1 = 16,
  60. ID_DDR = 17,
  61. ID_QSPI = 18,
  62. ID_MAX,
  63. };
  64. /**
  65. * PLL type identifiers
  66. * @PLL_TYPE_FRAC: fractional PLL identifier
  67. * @PLL_TYPE_DIV: divider PLL identifier
  68. */
  69. enum pll_type {
  70. PLL_TYPE_FRAC,
  71. PLL_TYPE_DIV,
  72. };
  73. /* Clock names used as parents for multiple clocks. */
  74. static const char *clk_names[] = {
  75. [ID_MAIN_RC_OSC] = "main_rc_osc",
  76. [ID_MAIN_OSC] = "main_osc",
  77. [ID_MAINCK] = "mainck",
  78. [ID_PLL_U_DIV] = "upll_divpmcck",
  79. [ID_PLL_A_DIV] = "plla_divpmcck",
  80. [ID_MCK] = "mck",
  81. };
  82. /* Fractional PLL output range. */
  83. static const struct clk_range plla_outputs[] = {
  84. { .min = 2343750, .max = 1200000000 },
  85. };
  86. static const struct clk_range upll_outputs[] = {
  87. { .min = 300000000, .max = 500000000 },
  88. };
  89. /* PLL characteristics. */
  90. static const struct clk_pll_characteristics apll_characteristics = {
  91. .input = { .min = 12000000, .max = 48000000 },
  92. .num_output = ARRAY_SIZE(plla_outputs),
  93. .output = plla_outputs,
  94. };
  95. static const struct clk_pll_characteristics upll_characteristics = {
  96. .input = { .min = 12000000, .max = 48000000 },
  97. .num_output = ARRAY_SIZE(upll_outputs),
  98. .output = upll_outputs,
  99. .upll = true,
  100. };
  101. /* Layout for fractional PLLs. */
  102. static const struct clk_pll_layout pll_layout_frac = {
  103. .mul_mask = GENMASK(31, 24),
  104. .frac_mask = GENMASK(21, 0),
  105. .mul_shift = 24,
  106. .frac_shift = 0,
  107. };
  108. /* Layout for DIV PLLs. */
  109. static const struct clk_pll_layout pll_layout_div = {
  110. .div_mask = GENMASK(7, 0),
  111. .endiv_mask = BIT(29),
  112. .div_shift = 0,
  113. .endiv_shift = 29,
  114. };
  115. /* MCK characteristics. */
  116. static const struct clk_master_characteristics mck_characteristics = {
  117. .output = { .min = 140000000, .max = 200000000 },
  118. .divisors = { 1, 2, 4, 3 },
  119. .have_div3_pres = 1,
  120. };
  121. /* MCK layout. */
  122. static const struct clk_master_layout mck_layout = {
  123. .mask = 0x373,
  124. .pres_shift = 4,
  125. .offset = 0x28,
  126. };
  127. /* Programmable clock layout. */
  128. static const struct clk_programmable_layout programmable_layout = {
  129. .pres_mask = 0xff,
  130. .pres_shift = 8,
  131. .css_mask = 0x1f,
  132. .have_slck_mck = 0,
  133. .is_pres_direct = 1,
  134. };
  135. /* Peripheral clock layout. */
  136. static const struct clk_pcr_layout pcr_layout = {
  137. .offset = 0x88,
  138. .cmd = BIT(31),
  139. .gckcss_mask = GENMASK(12, 8),
  140. .pid_mask = GENMASK(6, 0),
  141. };
  142. /**
  143. * PLL clocks description
  144. * @n: clock name
  145. * @p: clock parent
  146. * @l: clock layout
  147. * @t: clock type
  148. * @f: true if clock is fixed and not changeable by driver
  149. * @id: clock id corresponding to PLL driver
  150. * @cid: clock id corresponding to clock subsystem
  151. */
  152. static const struct {
  153. const char *n;
  154. const char *p;
  155. const struct clk_pll_layout *l;
  156. const struct clk_pll_characteristics *c;
  157. u8 t;
  158. u8 f;
  159. u8 id;
  160. u8 cid;
  161. } sam9x60_plls[] = {
  162. {
  163. .n = "plla_fracck",
  164. .p = "mainck",
  165. .l = &pll_layout_frac,
  166. .c = &apll_characteristics,
  167. .t = PLL_TYPE_FRAC,
  168. .f = 1,
  169. .id = 0,
  170. .cid = ID_PLL_A_FRAC,
  171. },
  172. {
  173. .n = "plla_divpmcck",
  174. .p = "plla_fracck",
  175. .l = &pll_layout_div,
  176. .c = &apll_characteristics,
  177. .t = PLL_TYPE_DIV,
  178. .f = 1,
  179. .id = 0,
  180. .cid = ID_PLL_A_DIV,
  181. },
  182. {
  183. .n = "upll_fracck",
  184. .p = "main_osc",
  185. .l = &pll_layout_frac,
  186. .c = &upll_characteristics,
  187. .t = PLL_TYPE_FRAC,
  188. .f = 1,
  189. .id = 1,
  190. .cid = ID_PLL_U_FRAC,
  191. },
  192. {
  193. .n = "upll_divpmcck",
  194. .p = "upll_fracck",
  195. .l = &pll_layout_div,
  196. .c = &upll_characteristics,
  197. .t = PLL_TYPE_DIV,
  198. .f = 1,
  199. .id = 1,
  200. .cid = ID_PLL_U_DIV,
  201. },
  202. };
  203. /**
  204. * Programmable clock description
  205. * @n: clock name
  206. * @cid: clock id corresponding to clock subsystem
  207. */
  208. static const struct {
  209. const char *n;
  210. u8 cid;
  211. } sam9x60_prog[] = {
  212. { .n = "prog0", .cid = ID_PROG0, },
  213. { .n = "prog1", .cid = ID_PROG1, },
  214. };
  215. /* Mux table for programmable clocks. */
  216. static u32 sam9x60_prog_mux_table[] = { 0, 1, 2, 3, 4, 5, };
  217. /**
  218. * System clock description
  219. * @n: clock name
  220. * @p: parent clock name
  221. * @id: clock id corresponding to system clock driver
  222. * @cid: clock id corresponding to clock subsystem
  223. */
  224. static const struct {
  225. const char *n;
  226. const char *p;
  227. u8 id;
  228. u8 cid;
  229. } sam9x60_systemck[] = {
  230. { .n = "ddrck", .p = "mck", .id = 2, .cid = ID_DDR, },
  231. { .n = "pck0", .p = "prog0", .id = 8, .cid = ID_PCK0, },
  232. { .n = "pck1", .p = "prog1", .id = 9, .cid = ID_PCK1, },
  233. { .n = "qspick", .p = "mck", .id = 19, .cid = ID_QSPI, },
  234. };
  235. /**
  236. * Peripheral clock description
  237. * @n: clock name
  238. * @id: clock id
  239. */
  240. static const struct {
  241. const char *n;
  242. u8 id;
  243. } sam9x60_periphck[] = {
  244. { .n = "pioA_clk", .id = 2, },
  245. { .n = "pioB_clk", .id = 3, },
  246. { .n = "pioC_clk", .id = 4, },
  247. { .n = "flex0_clk", .id = 5, },
  248. { .n = "flex1_clk", .id = 6, },
  249. { .n = "flex2_clk", .id = 7, },
  250. { .n = "flex3_clk", .id = 8, },
  251. { .n = "flex6_clk", .id = 9, },
  252. { .n = "flex7_clk", .id = 10, },
  253. { .n = "flex8_clk", .id = 11, },
  254. { .n = "sdmmc0_clk", .id = 12, },
  255. { .n = "flex4_clk", .id = 13, },
  256. { .n = "flex5_clk", .id = 14, },
  257. { .n = "flex9_clk", .id = 15, },
  258. { .n = "flex10_clk", .id = 16, },
  259. { .n = "tcb0_clk", .id = 17, },
  260. { .n = "pwm_clk", .id = 18, },
  261. { .n = "adc_clk", .id = 19, },
  262. { .n = "dma0_clk", .id = 20, },
  263. { .n = "matrix_clk", .id = 21, },
  264. { .n = "uhphs_clk", .id = 22, },
  265. { .n = "udphs_clk", .id = 23, },
  266. { .n = "macb0_clk", .id = 24, },
  267. { .n = "lcd_clk", .id = 25, },
  268. { .n = "sdmmc1_clk", .id = 26, },
  269. { .n = "macb1_clk", .id = 27, },
  270. { .n = "ssc_clk", .id = 28, },
  271. { .n = "can0_clk", .id = 29, },
  272. { .n = "can1_clk", .id = 30, },
  273. { .n = "flex11_clk", .id = 32, },
  274. { .n = "flex12_clk", .id = 33, },
  275. { .n = "i2s_clk", .id = 34, },
  276. { .n = "qspi_clk", .id = 35, },
  277. { .n = "gfx2d_clk", .id = 36, },
  278. { .n = "pit64b_clk", .id = 37, },
  279. { .n = "trng_clk", .id = 38, },
  280. { .n = "aes_clk", .id = 39, },
  281. { .n = "tdes_clk", .id = 40, },
  282. { .n = "sha_clk", .id = 41, },
  283. { .n = "classd_clk", .id = 42, },
  284. { .n = "isi_clk", .id = 43, },
  285. { .n = "pioD_clk", .id = 44, },
  286. { .n = "tcb1_clk", .id = 45, },
  287. { .n = "dbgu_clk", .id = 47, },
  288. { .n = "mpddr_clk", .id = 49, },
  289. };
  290. /**
  291. * Generic clock description
  292. * @n: clock name
  293. * @ep: extra parents parents names
  294. * @ep_mux_table: extra parents mux table
  295. * @ep_clk_mux_table: extra parents clock mux table (for CCF)
  296. * @r: clock output range
  297. * @ep_count: extra parents count
  298. * @id: clock id
  299. */
  300. static const struct {
  301. const char *n;
  302. struct clk_range r;
  303. u8 id;
  304. } sam9x60_gck[] = {
  305. { .n = "flex0_gclk", .id = 5, },
  306. { .n = "flex1_gclk", .id = 6, },
  307. { .n = "flex2_gclk", .id = 7, },
  308. { .n = "flex3_gclk", .id = 8, },
  309. { .n = "flex6_gclk", .id = 9, },
  310. { .n = "flex7_gclk", .id = 10, },
  311. { .n = "flex8_gclk", .id = 11, },
  312. { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
  313. { .n = "flex4_gclk", .id = 13, },
  314. { .n = "flex5_gclk", .id = 14, },
  315. { .n = "flex9_gclk", .id = 15, },
  316. { .n = "flex10_gclk", .id = 16, },
  317. { .n = "tcb0_gclk", .id = 17, },
  318. { .n = "adc_gclk", .id = 19, },
  319. { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, },
  320. { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
  321. { .n = "flex11_gclk", .id = 32, },
  322. { .n = "flex12_gclk", .id = 33, },
  323. { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 }, },
  324. { .n = "pit64b_gclk", .id = 37, },
  325. { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, },
  326. { .n = "tcb1_gclk", .id = 45, },
  327. { .n = "dbgu_gclk", .id = 47, },
  328. };
  329. #define prepare_mux_table(_allocs, _index, _dst, _src, _num, _label) \
  330. do { \
  331. int _i; \
  332. (_dst) = kzalloc(sizeof(*(_dst)) * (_num), GFP_KERNEL); \
  333. if (!(_dst)) { \
  334. ret = -ENOMEM; \
  335. goto _label; \
  336. } \
  337. (_allocs)[(_index)++] = (_dst); \
  338. for (_i = 0; _i < (_num); _i++) \
  339. (_dst)[_i] = (_src)[_i]; \
  340. } while (0)
  341. static int sam9x60_clk_probe(struct udevice *dev)
  342. {
  343. void __iomem *base = (void *)devfdt_get_addr_ptr(dev);
  344. unsigned int *clkmuxallocs[64], *muxallocs[64];
  345. const char *p[10];
  346. unsigned int cm[10], m[10], *tmpclkmux, *tmpmux;
  347. struct clk clk, *c;
  348. int ret, muxallocindex = 0, clkmuxallocindex = 0, i;
  349. static const struct clk_range r = { 0, 0 };
  350. if (!base)
  351. return -EINVAL;
  352. memset(muxallocs, 0, ARRAY_SIZE(muxallocs));
  353. memset(clkmuxallocs, 0, ARRAY_SIZE(clkmuxallocs));
  354. ret = clk_get_by_index(dev, 0, &clk);
  355. if (ret)
  356. return ret;
  357. ret = clk_get_by_id(clk.id, &c);
  358. if (ret)
  359. return ret;
  360. clk_names[ID_TD_SLCK] = kmemdup(clk_hw_get_name(c),
  361. strlen(clk_hw_get_name(c)) + 1,
  362. GFP_KERNEL);
  363. if (!clk_names[ID_TD_SLCK])
  364. return -ENOMEM;
  365. ret = clk_get_by_index(dev, 1, &clk);
  366. if (ret)
  367. return ret;
  368. ret = clk_get_by_id(clk.id, &c);
  369. if (ret)
  370. return ret;
  371. clk_names[ID_MD_SLCK] = kmemdup(clk_hw_get_name(c),
  372. strlen(clk_hw_get_name(c)) + 1,
  373. GFP_KERNEL);
  374. if (!clk_names[ID_MD_SLCK])
  375. return -ENOMEM;
  376. ret = clk_get_by_index(dev, 2, &clk);
  377. if (ret)
  378. return ret;
  379. clk_names[ID_MAIN_XTAL] = kmemdup(clk_hw_get_name(&clk),
  380. strlen(clk_hw_get_name(&clk)) + 1,
  381. GFP_KERNEL);
  382. if (!clk_names[ID_MAIN_XTAL])
  383. return -ENOMEM;
  384. ret = clk_get_by_index(dev, 3, &clk);
  385. if (ret)
  386. goto fail;
  387. clk_names[ID_MAIN_RC] = kmemdup(clk_hw_get_name(&clk),
  388. strlen(clk_hw_get_name(&clk)) + 1,
  389. GFP_KERNEL);
  390. if (ret)
  391. goto fail;
  392. /* Register main rc oscillator. */
  393. c = at91_clk_main_rc(base, clk_names[ID_MAIN_RC_OSC],
  394. clk_names[ID_MAIN_RC]);
  395. if (IS_ERR(c)) {
  396. ret = PTR_ERR(c);
  397. goto fail;
  398. }
  399. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC), c);
  400. /* Register main oscillator. */
  401. c = at91_clk_main_osc(base, clk_names[ID_MAIN_OSC],
  402. clk_names[ID_MAIN_XTAL], false);
  403. if (IS_ERR(c)) {
  404. ret = PTR_ERR(c);
  405. goto fail;
  406. }
  407. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC), c);
  408. /* Register mainck. */
  409. p[0] = clk_names[ID_MAIN_RC_OSC];
  410. p[1] = clk_names[ID_MAIN_OSC];
  411. cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_RC_OSC);
  412. cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAIN_OSC);
  413. prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 2,
  414. fail);
  415. c = at91_clk_sam9x5_main(base, clk_names[ID_MAINCK], p,
  416. 2, tmpclkmux, PMC_TYPE_CORE);
  417. if (IS_ERR(c)) {
  418. ret = PTR_ERR(c);
  419. goto fail;
  420. }
  421. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK), c);
  422. /* Register PLL fracs clocks. */
  423. for (i = 0; i < ARRAY_SIZE(sam9x60_plls); i++) {
  424. if (sam9x60_plls[i].t != PLL_TYPE_FRAC)
  425. continue;
  426. c = sam9x60_clk_register_frac_pll(base, sam9x60_plls[i].n,
  427. sam9x60_plls[i].p,
  428. sam9x60_plls[i].id,
  429. sam9x60_plls[i].c,
  430. sam9x60_plls[i].l,
  431. sam9x60_plls[i].f);
  432. if (IS_ERR(c)) {
  433. ret = PTR_ERR(c);
  434. goto fail;
  435. }
  436. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
  437. }
  438. /* Register PLL div clocks. */
  439. for (i = 0; i < ARRAY_SIZE(sam9x60_plls); i++) {
  440. if (sam9x60_plls[i].t != PLL_TYPE_DIV)
  441. continue;
  442. c = sam9x60_clk_register_div_pll(base, sam9x60_plls[i].n,
  443. sam9x60_plls[i].p,
  444. sam9x60_plls[i].id,
  445. sam9x60_plls[i].c,
  446. sam9x60_plls[i].l,
  447. sam9x60_plls[i].f);
  448. if (IS_ERR(c)) {
  449. ret = PTR_ERR(c);
  450. goto fail;
  451. }
  452. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_plls[i].cid), c);
  453. }
  454. /* Register MCK clock. */
  455. p[0] = clk_names[ID_MD_SLCK];
  456. p[1] = clk_names[ID_MAINCK];
  457. p[2] = clk_names[ID_PLL_A_DIV];
  458. p[3] = clk_names[ID_PLL_U_DIV];
  459. cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
  460. cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
  461. cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
  462. cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
  463. prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm, 4,
  464. fail);
  465. c = at91_clk_register_master(base, clk_names[ID_MCK], p, 4, &mck_layout,
  466. &mck_characteristics, tmpclkmux);
  467. if (IS_ERR(c)) {
  468. ret = PTR_ERR(c);
  469. goto fail;
  470. }
  471. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK), c);
  472. /* Register programmable clocks. */
  473. p[0] = clk_names[ID_MD_SLCK];
  474. p[1] = clk_names[ID_TD_SLCK];
  475. p[2] = clk_names[ID_MAINCK];
  476. p[3] = clk_names[ID_MCK];
  477. p[4] = clk_names[ID_PLL_A_DIV];
  478. p[5] = clk_names[ID_PLL_U_DIV];
  479. cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
  480. cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
  481. cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
  482. cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
  483. cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
  484. cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
  485. for (i = 0; i < ARRAY_SIZE(sam9x60_prog); i++) {
  486. prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
  487. 6, fail);
  488. c = at91_clk_register_programmable(base, sam9x60_prog[i].n, p,
  489. 10, i, &programmable_layout,
  490. tmpclkmux,
  491. sam9x60_prog_mux_table);
  492. if (IS_ERR(c)) {
  493. ret = PTR_ERR(c);
  494. goto fail;
  495. }
  496. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_CORE, sam9x60_prog[i].cid), c);
  497. }
  498. /* System clocks. */
  499. for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
  500. c = at91_clk_register_system(base, sam9x60_systemck[i].n,
  501. sam9x60_systemck[i].p,
  502. sam9x60_systemck[i].id);
  503. if (IS_ERR(c)) {
  504. ret = PTR_ERR(c);
  505. goto fail;
  506. }
  507. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_SYSTEM, sam9x60_systemck[i].cid),
  508. c);
  509. }
  510. /* Peripheral clocks. */
  511. for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
  512. c = at91_clk_register_sam9x5_peripheral(base, &pcr_layout,
  513. sam9x60_periphck[i].n,
  514. clk_names[ID_MCK],
  515. sam9x60_periphck[i].id,
  516. &r);
  517. if (IS_ERR(c)) {
  518. ret = PTR_ERR(c);
  519. goto fail;
  520. }
  521. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_PERIPHERAL,
  522. sam9x60_periphck[i].id), c);
  523. }
  524. /* Generic clocks. */
  525. p[0] = clk_names[ID_MD_SLCK];
  526. p[1] = clk_names[ID_TD_SLCK];
  527. p[2] = clk_names[ID_MAINCK];
  528. p[3] = clk_names[ID_MCK];
  529. p[4] = clk_names[ID_PLL_A_DIV];
  530. p[5] = clk_names[ID_PLL_U_DIV];
  531. m[0] = 0;
  532. m[1] = 1;
  533. m[2] = 2;
  534. m[3] = 3;
  535. m[4] = 4;
  536. m[5] = 5;
  537. cm[0] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MD_SLCK);
  538. cm[1] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_TD_SLCK);
  539. cm[2] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MAINCK);
  540. cm[3] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_MCK);
  541. cm[4] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_A_DIV);
  542. cm[5] = AT91_TO_CLK_ID(PMC_TYPE_CORE, ID_PLL_U_DIV);
  543. for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
  544. prepare_mux_table(clkmuxallocs, clkmuxallocindex, tmpclkmux, cm,
  545. 6, fail);
  546. prepare_mux_table(muxallocs, muxallocindex, tmpmux, m,
  547. 6, fail);
  548. c = at91_clk_register_generic(base, &pcr_layout,
  549. sam9x60_gck[i].n, p, tmpclkmux,
  550. tmpmux, 6, sam9x60_gck[i].id,
  551. &sam9x60_gck[i].r);
  552. if (IS_ERR(c)) {
  553. ret = PTR_ERR(c);
  554. goto fail;
  555. }
  556. clk_dm(AT91_TO_CLK_ID(PMC_TYPE_GCK, sam9x60_gck[i].id), c);
  557. }
  558. return 0;
  559. fail:
  560. for (i = 0; i < ARRAY_SIZE(muxallocs); i++)
  561. kfree(muxallocs[i]);
  562. for (i = 0; i < ARRAY_SIZE(clkmuxallocs); i++)
  563. kfree(clkmuxallocs[i]);
  564. return ret;
  565. }
  566. static const struct udevice_id sam9x60_clk_ids[] = {
  567. { .compatible = "microchip,sam9x60-pmc" },
  568. { /* Sentinel. */ },
  569. };
  570. U_BOOT_DRIVER(at91_sam9x60_pmc) = {
  571. .name = "at91-sam9x60-pmc",
  572. .id = UCLASS_CLK,
  573. .of_match = sam9x60_clk_ids,
  574. .ops = &at91_clk_ops,
  575. .probe = sam9x60_clk_probe,
  576. .flags = DM_FLAG_PRE_RELOC,
  577. };