clk-n5x.h 6.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
  4. */
  5. #ifndef _CLK_N5X_
  6. #define _CLK_N5X_
  7. #ifndef __ASSEMBLY__
  8. #include <linux/bitops.h>
  9. #endif
  10. #define CM_REG_READL(plat, reg) \
  11. readl((plat)->regs + (reg))
  12. #define CM_REG_WRITEL(plat, data, reg) \
  13. writel(data, (plat)->regs + (reg))
  14. #define CM_REG_CLRBITS(plat, reg, clear) \
  15. clrbits_le32((plat)->regs + (reg), (clear))
  16. #define CM_REG_SETBITS(plat, reg, set) \
  17. setbits_le32((plat)->regs + (reg), (set))
  18. struct cm_config {
  19. /* main group */
  20. u32 main_pll_mpuclk;
  21. u32 main_pll_nocclk;
  22. u32 main_pll_nocdiv;
  23. u32 main_pll_pllglob;
  24. u32 main_pll_plldiv;
  25. u32 main_pll_plloutdiv;
  26. u32 spare_1[4];
  27. /* peripheral group */
  28. u32 per_pll_emacctl;
  29. u32 per_pll_gpiodiv;
  30. u32 per_pll_pllglob;
  31. u32 per_pll_plldiv;
  32. u32 per_pll_plloutdiv;
  33. u32 spare_2[4];
  34. /* altera group */
  35. u32 alt_emacactr;
  36. u32 alt_emacbctr;
  37. u32 alt_emacptpctr;
  38. u32 alt_gpiodbctr;
  39. u32 alt_sdmmcctr;
  40. u32 alt_s2fuser0ctr;
  41. u32 alt_s2fuser1ctr;
  42. u32 alt_psirefctr;
  43. /* incoming clock */
  44. u32 hps_osc_clk_hz;
  45. u32 fpga_clk_hz;
  46. u32 spare_3[3];
  47. /* memory clock group */
  48. u32 mem_memdiv;
  49. u32 mem_pllglob;
  50. u32 mem_plldiv;
  51. u32 mem_plloutdiv;
  52. u32 spare_4[4];
  53. };
  54. /* Clock Manager registers */
  55. #define CLKMGR_CTRL 0
  56. #define CLKMGR_STAT 4
  57. #define CLKMGR_TESTIOCTRL 8
  58. #define CLKMGR_INTRGEN 0x0c
  59. #define CLKMGR_INTRMSK 0x10
  60. #define CLKMGR_INTRCLR 0x14
  61. #define CLKMGR_INTRSTS 0x18
  62. #define CLKMGR_INTRSTK 0x1c
  63. #define CLKMGR_INTRRAW 0x20
  64. /* Clock Manager Main PPL group registers */
  65. #define CLKMGR_MAINPLL_EN 0x24
  66. #define CLKMGR_MAINPLL_ENS 0x28
  67. #define CLKMGR_MAINPLL_ENR 0x2c
  68. #define CLKMGR_MAINPLL_BYPASS 0x30
  69. #define CLKMGR_MAINPLL_BYPASSS 0x34
  70. #define CLKMGR_MAINPLL_BYPASSR 0x38
  71. #define CLKMGR_MAINPLL_MPUCLK 0x3c
  72. #define CLKMGR_MAINPLL_NOCCLK 0x40
  73. #define CLKMGR_MAINPLL_NOCDIV 0x44
  74. #define CLKMGR_MAINPLL_PLLGLOB 0x48
  75. #define CLKMGR_MAINPLL_PLLCTRL 0x4c
  76. #define CLKMGR_MAINPLL_PLLDIV 0x50
  77. #define CLKMGR_MAINPLL_PLLOUTDIV 0x54
  78. #define CLKMGR_MAINPLL_LOSTLOCK 0x58
  79. /* Clock Manager Peripheral PPL group registers */
  80. #define CLKMGR_PERPLL_EN 0x7c
  81. #define CLKMGR_PERPLL_ENS 0x80
  82. #define CLKMGR_PERPLL_ENR 0x84
  83. #define CLKMGR_PERPLL_BYPASS 0x88
  84. #define CLKMGR_PERPLL_BYPASSS 0x8c
  85. #define CLKMGR_PERPLL_BYPASSR 0x90
  86. #define CLKMGR_PERPLL_EMACCTL 0x94
  87. #define CLKMGR_PERPLL_GPIODIV 0x98
  88. #define CLKMGR_PERPLL_PLLGLOB 0x9c
  89. #define CLKMGR_PERPLL_PLLCTRL 0xa0
  90. #define CLKMGR_PERPLL_PLLDIV 0xa4
  91. #define CLKMGR_PERPLL_PLLOUTDIV 0xa8
  92. #define CLKMGR_PERPLL_LOSTLOCK 0xac
  93. /* Clock Manager Altera group registers */
  94. #define CLKMGR_ALTR_EMACACTR 0xd4
  95. #define CLKMGR_ALTR_EMACBCTR 0xd8
  96. #define CLKMGR_ALTR_EMACPTPCTR 0xdc
  97. #define CLKMGR_ALTR_GPIODBCTR 0xe0
  98. #define CLKMGR_ALTR_SDMMCCTR 0xe4
  99. #define CLKMGR_ALTR_S2FUSER0CTR 0xe8
  100. #define CLKMGR_ALTR_S2FUSER1CTR 0xec
  101. #define CLKMGR_ALTR_PSIREFCTR 0xf0
  102. #define CLKMGR_ALTR_EXTCNTRST 0xf4
  103. #define CLKMGR_CTRL_BOOTMODE BIT(0)
  104. #define CLKMGR_STAT_BUSY BIT(0)
  105. #define CLKMGR_STAT_MAINPLL_LOCKED BIT(8)
  106. #define CLKMGR_STAT_MAIN_TRANS BIT(9)
  107. #define CLKMGR_STAT_PERPLL_LOCKED BIT(16)
  108. #define CLKMGR_STAT_PERF_TRANS BIT(17)
  109. #define CLKMGR_STAT_BOOTMODE BIT(24)
  110. #define CLKMGR_STAT_BOOTCLKSRC BIT(25)
  111. #define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
  112. (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)
  113. #define CLKMGR_INTER_MAINPLLLOCKED_MASK BIT(0)
  114. #define CLKMGR_INTER_PERPLLLOCKED_MASK BIT(1)
  115. #define CLKMGR_INTER_MAINPLLLOST_MASK BIT(2)
  116. #define CLKMGR_INTER_PERPLLLOST_MASK BIT(3)
  117. #define CLKMGR_CLKSRC_MASK GENMASK(18, 16)
  118. #define CLKMGR_CLKSRC_OFFSET 16
  119. #define CLKMGR_CLKSRC_MAIN 0
  120. #define CLKMGR_CLKSRC_PER 1
  121. #define CLKMGR_CLKSRC_OSC1 2
  122. #define CLKMGR_CLKSRC_INTOSC 3
  123. #define CLKMGR_CLKSRC_FPGA 4
  124. #define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
  125. #define CLKMGR_BYPASS_MAINPLL_ALL 0x7
  126. #define CLKMGR_BYPASS_PERPLL_ALL 0x7f
  127. #define CLKMGR_NOCDIV_L4MAIN_OFFSET 0
  128. #define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8
  129. #define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16
  130. #define CLKMGR_NOCDIV_CSATCLK_OFFSET 24
  131. #define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26
  132. #define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28
  133. #define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
  134. #define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16)
  135. #define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16
  136. #define CLKMGR_PLLGLOB_LOSTLOCK_BYPASS_EN_MASK BIT(28)
  137. #define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
  138. #define CLKMGR_VCO_PSRC_EOSC1 0
  139. #define CLKMGR_VCO_PSRC_INTOSC 1
  140. #define CLKMGR_VCO_PSRC_F2S 2
  141. #define CLKMGR_PLLCTRL_BYPASS_MASK BIT(0)
  142. #define CLKMGR_PLLCTRL_RST_N_MASK BIT(1)
  143. #define CLKMGR_PLLDIV_REFCLKDIV_MASK GENMASK(5, 0)
  144. #define CLKMGR_PLLDIV_FDIV_MASK GENMASK(16, 8)
  145. #define CLKMGR_PLLDIV_OUTDIV_QDIV_MASK GENMASK(26, 24)
  146. #define CLKMGR_PLLDIV_RANGE_MASK GENMASK(30, 28)
  147. #define CLKMGR_PLLDIV_REFCLKDIV_OFFSET 0
  148. #define CLKMGR_PLLDIV_FDIV_OFFSET 8
  149. #define CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET 24
  150. #define CLKMGR_PLLDIV_RANGE_OFFSET 28
  151. #define CLKMGR_PLLOUTDIV_C0CNT_MASK GENMASK(4, 0)
  152. #define CLKMGR_PLLOUTDIV_C1CNT_MASK GENMASK(12, 8)
  153. #define CLKMGR_PLLOUTDIV_C2CNT_MASK GENMASK(20, 16)
  154. #define CLKMGR_PLLOUTDIV_C3CNT_MASK GENMASK(28, 24)
  155. #define CLKMGR_PLLOUTDIV_C0CNT_OFFSET 0
  156. #define CLKMGR_PLLOUTDIV_C1CNT_OFFSET 8
  157. #define CLKMGR_PLLOUTDIV_C2CNT_OFFSET 16
  158. #define CLKMGR_PLLOUTDIV_C3CNT_OFFSET 24
  159. #define CLKMGR_PLLCX_EN_SET_MSK BIT(27)
  160. #define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
  161. #define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16)
  162. #define CLKMGR_VCOCALIB_MSCNT_OFFSET 16
  163. #define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0)
  164. #define CLKMGR_VCOCALIB_MSCNT_CONST 100
  165. #define CLKMGR_VCOCALIB_HSCNT_CONST 4
  166. #define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
  167. #define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
  168. #define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
  169. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26
  170. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26)
  171. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27
  172. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27)
  173. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28
  174. #define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
  175. #define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16
  176. #define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16)
  177. #define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0
  178. #define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0)
  179. #define CLKMGR_ALT_EXTCNTRST_ALLCNTRST_MASK GENMASK(15, 0)
  180. #endif /* _CLK_N5X_ */