clk-arria10.c 8.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <asm/io.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <dm/devres.h>
  12. #include <dm/lists.h>
  13. #include <dm/util.h>
  14. #include <linux/bitops.h>
  15. #include <asm/global_data.h>
  16. #include <asm/arch/clock_manager.h>
  17. enum socfpga_a10_clk_type {
  18. SOCFPGA_A10_CLK_MAIN_PLL,
  19. SOCFPGA_A10_CLK_PER_PLL,
  20. SOCFPGA_A10_CLK_PERIP_CLK,
  21. SOCFPGA_A10_CLK_GATE_CLK,
  22. SOCFPGA_A10_CLK_UNKNOWN_CLK,
  23. };
  24. struct socfpga_a10_clk_plat {
  25. enum socfpga_a10_clk_type type;
  26. struct clk_bulk clks;
  27. u32 regs;
  28. /* Fixed divider */
  29. u16 fix_div;
  30. /* Control register */
  31. u16 ctl_reg;
  32. /* Divider register */
  33. u16 div_reg;
  34. u8 div_len;
  35. u8 div_off;
  36. /* Clock gating register */
  37. u16 gate_reg;
  38. u8 gate_bit;
  39. };
  40. static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk)
  41. {
  42. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  43. u32 reg, maxval;
  44. if (plat->clks.count == 0)
  45. return 0;
  46. if (plat->clks.count == 1) {
  47. *upclk = &plat->clks.clks[0];
  48. return 0;
  49. }
  50. if (!plat->ctl_reg) {
  51. dev_err(clk->dev, "Invalid control register\n");
  52. return -EINVAL;
  53. }
  54. reg = readl(plat->regs + plat->ctl_reg);
  55. /* Assume PLLs are ON for now */
  56. if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
  57. reg = (reg >> 8) & 0x3;
  58. maxval = 2;
  59. } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
  60. reg = (reg >> 8) & 0x3;
  61. maxval = 3;
  62. } else {
  63. reg = (reg >> 16) & 0x7;
  64. maxval = 4;
  65. }
  66. if (reg > maxval) {
  67. dev_err(clk->dev, "Invalid clock source\n");
  68. return -EINVAL;
  69. }
  70. *upclk = &plat->clks.clks[reg];
  71. return 0;
  72. }
  73. static int socfpga_a10_clk_endisable(struct clk *clk, bool enable)
  74. {
  75. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  76. struct clk *upclk = NULL;
  77. int ret;
  78. if (!enable && plat->gate_reg)
  79. clrbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
  80. ret = socfpga_a10_clk_get_upstream(clk, &upclk);
  81. if (ret)
  82. return ret;
  83. if (upclk) {
  84. if (enable)
  85. clk_enable(upclk);
  86. else
  87. clk_disable(upclk);
  88. }
  89. if (enable && plat->gate_reg)
  90. setbits_le32(plat->regs + plat->gate_reg, BIT(plat->gate_bit));
  91. return 0;
  92. }
  93. static int socfpga_a10_clk_enable(struct clk *clk)
  94. {
  95. return socfpga_a10_clk_endisable(clk, true);
  96. }
  97. static int socfpga_a10_clk_disable(struct clk *clk)
  98. {
  99. return socfpga_a10_clk_endisable(clk, false);
  100. }
  101. static ulong socfpga_a10_clk_get_rate(struct clk *clk)
  102. {
  103. struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev);
  104. struct clk *upclk = NULL;
  105. ulong rate = 0, reg, numer, denom;
  106. int ret;
  107. ret = socfpga_a10_clk_get_upstream(clk, &upclk);
  108. if (ret || !upclk)
  109. return 0;
  110. rate = clk_get_rate(upclk);
  111. if (plat->type == SOCFPGA_A10_CLK_MAIN_PLL) {
  112. reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
  113. numer = reg & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
  114. denom = (reg >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
  115. CLKMGR_MAINPLL_VCO1_DENOM_MSK;
  116. rate /= denom + 1;
  117. rate *= numer + 1;
  118. } else if (plat->type == SOCFPGA_A10_CLK_PER_PLL) {
  119. reg = readl(plat->regs + plat->ctl_reg + 4); /* VCO1 */
  120. numer = reg & CLKMGR_PERPLL_VCO1_NUMER_MSK;
  121. denom = (reg >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
  122. CLKMGR_PERPLL_VCO1_DENOM_MSK;
  123. rate /= denom + 1;
  124. rate *= numer + 1;
  125. } else {
  126. rate /= plat->fix_div;
  127. if (plat->fix_div == 1 && plat->ctl_reg) {
  128. reg = readl(plat->regs + plat->ctl_reg);
  129. reg &= 0x7ff;
  130. rate /= reg + 1;
  131. }
  132. if (plat->div_reg) {
  133. reg = readl(plat->regs + plat->div_reg);
  134. reg >>= plat->div_off;
  135. reg &= (1 << plat->div_len) - 1;
  136. if (plat->type == SOCFPGA_A10_CLK_PERIP_CLK)
  137. rate /= reg + 1;
  138. if (plat->type == SOCFPGA_A10_CLK_GATE_CLK)
  139. rate /= 1 << reg;
  140. }
  141. }
  142. return rate;
  143. }
  144. static struct clk_ops socfpga_a10_clk_ops = {
  145. .enable = socfpga_a10_clk_enable,
  146. .disable = socfpga_a10_clk_disable,
  147. .get_rate = socfpga_a10_clk_get_rate,
  148. };
  149. /*
  150. * This workaround tries to fix the massively broken generated "handoff" DT,
  151. * which contains duplicate clock nodes without any connection to the clock
  152. * manager DT node. Yet, those "handoff" DT nodes contain configuration of
  153. * the fixed input clock of the Arria10 which are missing from the base DT
  154. * for Arria10.
  155. *
  156. * This workaround sets up upstream clock for the fixed input clocks of the
  157. * A10 described in the base DT such that they map to the fixed clock from
  158. * the "handoff" DT. This does not fully match how the clock look on the
  159. * A10, but it is the least intrusive way to fix this mess.
  160. */
  161. static void socfpga_a10_handoff_workaround(struct udevice *dev)
  162. {
  163. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  164. const void *fdt = gd->fdt_blob;
  165. struct clk_bulk *bulk = &plat->clks;
  166. int i, ret, offset = dev_of_offset(dev);
  167. static const char * const socfpga_a10_fixedclk_map[] = {
  168. "osc1", "altera_arria10_hps_eosc1",
  169. "cb_intosc_ls_clk", "altera_arria10_hps_cb_intosc_ls",
  170. "f2s_free_clk", "altera_arria10_hps_f2h_free",
  171. };
  172. if (fdt_node_check_compatible(fdt, offset, "fixed-clock"))
  173. return;
  174. for (i = 0; i < ARRAY_SIZE(socfpga_a10_fixedclk_map); i += 2)
  175. if (!strcmp(dev->name, socfpga_a10_fixedclk_map[i]))
  176. break;
  177. if (i == ARRAY_SIZE(socfpga_a10_fixedclk_map))
  178. return;
  179. ret = uclass_get_device_by_name(UCLASS_CLK,
  180. socfpga_a10_fixedclk_map[i + 1], &dev);
  181. if (ret)
  182. return;
  183. bulk->count = 1;
  184. bulk->clks = devm_kcalloc(dev, bulk->count,
  185. sizeof(struct clk), GFP_KERNEL);
  186. if (!bulk->clks)
  187. return;
  188. ret = clk_request(dev, &bulk->clks[0]);
  189. if (ret)
  190. free(bulk->clks);
  191. }
  192. static int socfpga_a10_clk_bind(struct udevice *dev)
  193. {
  194. const void *fdt = gd->fdt_blob;
  195. int offset = dev_of_offset(dev);
  196. bool pre_reloc_only = !(gd->flags & GD_FLG_RELOC);
  197. const char *name;
  198. int ret;
  199. for (offset = fdt_first_subnode(fdt, offset);
  200. offset > 0;
  201. offset = fdt_next_subnode(fdt, offset)) {
  202. name = fdt_get_name(fdt, offset, NULL);
  203. if (!name)
  204. return -EINVAL;
  205. if (!strcmp(name, "clocks")) {
  206. offset = fdt_first_subnode(fdt, offset);
  207. name = fdt_get_name(fdt, offset, NULL);
  208. if (!name)
  209. return -EINVAL;
  210. }
  211. /* Filter out supported sub-clock */
  212. if (fdt_node_check_compatible(fdt, offset,
  213. "altr,socfpga-a10-pll-clock") &&
  214. fdt_node_check_compatible(fdt, offset,
  215. "altr,socfpga-a10-perip-clk") &&
  216. fdt_node_check_compatible(fdt, offset,
  217. "altr,socfpga-a10-gate-clk") &&
  218. fdt_node_check_compatible(fdt, offset, "fixed-clock"))
  219. continue;
  220. if (pre_reloc_only &&
  221. !ofnode_pre_reloc(offset_to_ofnode(offset)))
  222. continue;
  223. ret = device_bind_driver_to_node(dev, "clk-a10", name,
  224. offset_to_ofnode(offset),
  225. NULL);
  226. if (ret)
  227. return ret;
  228. }
  229. return 0;
  230. }
  231. static int socfpga_a10_clk_probe(struct udevice *dev)
  232. {
  233. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  234. struct socfpga_a10_clk_plat *pplat;
  235. struct udevice *pdev;
  236. const void *fdt = gd->fdt_blob;
  237. int offset = dev_of_offset(dev);
  238. clk_get_bulk(dev, &plat->clks);
  239. socfpga_a10_handoff_workaround(dev);
  240. if (!fdt_node_check_compatible(fdt, offset, "altr,clk-mgr")) {
  241. plat->regs = dev_read_addr(dev);
  242. } else {
  243. pdev = dev_get_parent(dev);
  244. if (!pdev)
  245. return -ENODEV;
  246. pplat = dev_get_plat(pdev);
  247. if (!pplat)
  248. return -EINVAL;
  249. plat->ctl_reg = dev_read_u32_default(dev, "reg", 0x0);
  250. plat->regs = pplat->regs;
  251. }
  252. if (!fdt_node_check_compatible(fdt, offset,
  253. "altr,socfpga-a10-pll-clock")) {
  254. /* Main PLL has 3 upstream clock */
  255. if (plat->clks.count == 3)
  256. plat->type = SOCFPGA_A10_CLK_MAIN_PLL;
  257. else
  258. plat->type = SOCFPGA_A10_CLK_PER_PLL;
  259. } else if (!fdt_node_check_compatible(fdt, offset,
  260. "altr,socfpga-a10-perip-clk")) {
  261. plat->type = SOCFPGA_A10_CLK_PERIP_CLK;
  262. } else if (!fdt_node_check_compatible(fdt, offset,
  263. "altr,socfpga-a10-gate-clk")) {
  264. plat->type = SOCFPGA_A10_CLK_GATE_CLK;
  265. } else {
  266. plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
  267. }
  268. return 0;
  269. }
  270. static int socfpga_a10_of_to_plat(struct udevice *dev)
  271. {
  272. struct socfpga_a10_clk_plat *plat = dev_get_plat(dev);
  273. unsigned int divreg[3], gatereg[2];
  274. int ret;
  275. plat->type = SOCFPGA_A10_CLK_UNKNOWN_CLK;
  276. plat->fix_div = dev_read_u32_default(dev, "fixed-divider", 1);
  277. ret = dev_read_u32_array(dev, "div-reg", divreg, ARRAY_SIZE(divreg));
  278. if (!ret) {
  279. plat->div_reg = divreg[0];
  280. plat->div_len = divreg[2];
  281. plat->div_off = divreg[1];
  282. }
  283. ret = dev_read_u32_array(dev, "clk-gate", gatereg, ARRAY_SIZE(gatereg));
  284. if (!ret) {
  285. plat->gate_reg = gatereg[0];
  286. plat->gate_bit = gatereg[1];
  287. }
  288. return 0;
  289. }
  290. static const struct udevice_id socfpga_a10_clk_match[] = {
  291. { .compatible = "altr,clk-mgr" },
  292. {}
  293. };
  294. U_BOOT_DRIVER(socfpga_a10_clk) = {
  295. .name = "clk-a10",
  296. .id = UCLASS_CLK,
  297. .of_match = socfpga_a10_clk_match,
  298. .ops = &socfpga_a10_clk_ops,
  299. .bind = socfpga_a10_clk_bind,
  300. .probe = socfpga_a10_clk_probe,
  301. .of_to_plat = socfpga_a10_of_to_plat,
  302. .plat_auto = sizeof(struct socfpga_a10_clk_plat),
  303. };