cache-v5l2.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Andes Technology Corporation
  4. * Rick Chen, Andes Technology Corporation <rick@andestech.com>
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <cache.h>
  9. #include <dm.h>
  10. #include <hang.h>
  11. #include <asm/global_data.h>
  12. #include <asm/io.h>
  13. #include <dm/ofnode.h>
  14. #include <linux/bitops.h>
  15. struct l2cache {
  16. volatile u64 configure;
  17. volatile u64 control;
  18. volatile u64 hpm0;
  19. volatile u64 hpm1;
  20. volatile u64 hpm2;
  21. volatile u64 hpm3;
  22. volatile u64 error_status;
  23. volatile u64 ecc_error;
  24. volatile u64 cctl_command0;
  25. volatile u64 cctl_access_line0;
  26. volatile u64 cctl_command1;
  27. volatile u64 cctl_access_line1;
  28. volatile u64 cctl_command2;
  29. volatile u64 cctl_access_line2;
  30. volatile u64 cctl_command3;
  31. volatile u64 cctl_access_line4;
  32. volatile u64 cctl_status;
  33. };
  34. /* Control Register */
  35. #define L2_ENABLE 0x1
  36. /* prefetch */
  37. #define IPREPETCH_OFF 3
  38. #define DPREPETCH_OFF 5
  39. #define IPREPETCH_MSK (3 << IPREPETCH_OFF)
  40. #define DPREPETCH_MSK (3 << DPREPETCH_OFF)
  41. /* tag ram */
  42. #define TRAMOCTL_OFF 8
  43. #define TRAMICTL_OFF 10
  44. #define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
  45. #define TRAMICTL_MSK BIT(TRAMICTL_OFF)
  46. /* data ram */
  47. #define DRAMOCTL_OFF 11
  48. #define DRAMICTL_OFF 13
  49. #define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
  50. #define DRAMICTL_MSK BIT(DRAMICTL_OFF)
  51. /* CCTL Command Register */
  52. #define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
  53. #define L2_WBINVAL_ALL 0x12
  54. /* CCTL Status Register */
  55. #define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
  56. #define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
  57. #define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
  58. #define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
  59. DECLARE_GLOBAL_DATA_PTR;
  60. struct v5l2_plat {
  61. struct l2cache *regs;
  62. u32 iprefetch;
  63. u32 dprefetch;
  64. u32 tram_ctl[2];
  65. u32 dram_ctl[2];
  66. };
  67. static int v5l2_enable(struct udevice *dev)
  68. {
  69. struct v5l2_plat *plat = dev_get_plat(dev);
  70. volatile struct l2cache *regs = plat->regs;
  71. if (regs)
  72. setbits_le32(&regs->control, L2_ENABLE);
  73. return 0;
  74. }
  75. static int v5l2_disable(struct udevice *dev)
  76. {
  77. struct v5l2_plat *plat = dev_get_plat(dev);
  78. volatile struct l2cache *regs = plat->regs;
  79. u8 hart = gd->arch.boot_hart;
  80. void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
  81. if ((regs) && (readl(&regs->control) & L2_ENABLE)) {
  82. writel(L2_WBINVAL_ALL, cctlcmd);
  83. while ((readl(&regs->cctl_status) & CCTL_STATUS_MSK(hart))) {
  84. if ((readl(&regs->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
  85. printf("L2 flush illegal! hanging...");
  86. hang();
  87. }
  88. }
  89. clrbits_le32(&regs->control, L2_ENABLE);
  90. }
  91. return 0;
  92. }
  93. static int v5l2_of_to_plat(struct udevice *dev)
  94. {
  95. struct v5l2_plat *plat = dev_get_plat(dev);
  96. struct l2cache *regs;
  97. regs = (struct l2cache *)dev_read_addr(dev);
  98. plat->regs = regs;
  99. plat->iprefetch = -EINVAL;
  100. plat->dprefetch = -EINVAL;
  101. plat->tram_ctl[0] = -EINVAL;
  102. plat->dram_ctl[0] = -EINVAL;
  103. /* Instruction and data fetch prefetch depth */
  104. dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
  105. dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
  106. /* Set tag RAM and data RAM setup and output cycle */
  107. dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
  108. dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
  109. return 0;
  110. }
  111. static int v5l2_probe(struct udevice *dev)
  112. {
  113. struct v5l2_plat *plat = dev_get_plat(dev);
  114. struct l2cache *regs = plat->regs;
  115. u32 ctl_val;
  116. ctl_val = readl(&regs->control);
  117. if (!(ctl_val & L2_ENABLE))
  118. ctl_val |= L2_ENABLE;
  119. if (plat->iprefetch != -EINVAL) {
  120. ctl_val &= ~(IPREPETCH_MSK);
  121. ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
  122. }
  123. if (plat->dprefetch != -EINVAL) {
  124. ctl_val &= ~(DPREPETCH_MSK);
  125. ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
  126. }
  127. if (plat->tram_ctl[0] != -EINVAL) {
  128. ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
  129. ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
  130. ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
  131. }
  132. if (plat->dram_ctl[0] != -EINVAL) {
  133. ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
  134. ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
  135. ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
  136. }
  137. writel(ctl_val, &regs->control);
  138. return 0;
  139. }
  140. static const struct udevice_id v5l2_cache_ids[] = {
  141. { .compatible = "v5l2cache" },
  142. {}
  143. };
  144. static const struct cache_ops v5l2_cache_ops = {
  145. .enable = v5l2_enable,
  146. .disable = v5l2_disable,
  147. };
  148. U_BOOT_DRIVER(v5l2_cache) = {
  149. .name = "v5l2_cache",
  150. .id = UCLASS_CACHE,
  151. .of_match = v5l2_cache_ids,
  152. .of_to_plat = v5l2_of_to_plat,
  153. .probe = v5l2_probe,
  154. .plat_auto = sizeof(struct v5l2_plat),
  155. .ops = &v5l2_cache_ops,
  156. .flags = DM_FLAG_PRE_RELOC,
  157. };