ihs_axi.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. *
  6. * (C) Copyright 2017, 2018
  7. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  8. */
  9. #include <common.h>
  10. #include <axi.h>
  11. #include <dm.h>
  12. #include <log.h>
  13. #include <regmap.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. /**
  17. * struct ihs_axi_regs - Structure for the register map of a IHS AXI device
  18. * @interrupt_status: Status register to indicate certain events (e.g.
  19. * error during transfer, transfer complete, etc.)
  20. * @interrupt_enable_control: Register to both control which statuses will be
  21. * indicated in the interrupt_status register, and
  22. * to change bus settings
  23. * @address_lsb: Least significant 16-bit word of the address of a
  24. * device to transfer data from/to
  25. * @address_msb: Most significant 16-bit word of the address of a
  26. * device to transfer data from/to
  27. * @write_data_lsb: Least significant 16-bit word of the data to be
  28. * written to a device
  29. * @write_data_msb: Most significant 16-bit word of the data to be
  30. * written to a device
  31. * @read_data_lsb: Least significant 16-bit word of the data read
  32. * from a device
  33. * @read_data_msb: Most significant 16-bit word of the data read
  34. * from a device
  35. */
  36. struct ihs_axi_regs {
  37. u16 interrupt_status;
  38. u16 interrupt_enable_control;
  39. u16 address_lsb;
  40. u16 address_msb;
  41. u16 write_data_lsb;
  42. u16 write_data_msb;
  43. u16 read_data_lsb;
  44. u16 read_data_msb;
  45. };
  46. /**
  47. * ihs_axi_set() - Convenience macro to set values in register map
  48. * @map: The register map to write to
  49. * @member: The member of the ihs_axi_regs structure to write
  50. * @val: The value to write to the register map
  51. */
  52. #define ihs_axi_set(map, member, val) \
  53. regmap_set(map, struct ihs_axi_regs, member, val)
  54. /**
  55. * ihs_axi_get() - Convenience macro to read values from register map
  56. * @map: The register map to read from
  57. * @member: The member of the ihs_axi_regs structure to read
  58. * @valp: Pointer to a buffer to receive the value read
  59. */
  60. #define ihs_axi_get(map, member, valp) \
  61. regmap_get(map, struct ihs_axi_regs, member, valp)
  62. /**
  63. * struct ihs_axi_priv - Private data structure of IHS AXI devices
  64. * @map: Register map for the IHS AXI device
  65. */
  66. struct ihs_axi_priv {
  67. struct regmap *map;
  68. };
  69. /**
  70. * enum status_reg - Description of bits in the interrupt_status register
  71. * @STATUS_READ_COMPLETE_EVENT: A read transfer was completed
  72. * @STATUS_WRITE_COMPLETE_EVENT: A write transfer was completed
  73. * @STATUS_TIMEOUT_EVENT: A timeout has occurred during the transfer
  74. * @STATUS_ERROR_EVENT: A error has occurred during the transfer
  75. * @STATUS_AXI_INT: A AXI interrupt has occurred
  76. * @STATUS_READ_DATA_AVAILABLE: Data is available to be read
  77. * @STATUS_BUSY: The bus is busy
  78. * @STATUS_INIT_DONE: The bus has finished initializing
  79. */
  80. enum status_reg {
  81. STATUS_READ_COMPLETE_EVENT = BIT(15),
  82. STATUS_WRITE_COMPLETE_EVENT = BIT(14),
  83. STATUS_TIMEOUT_EVENT = BIT(13),
  84. STATUS_ERROR_EVENT = BIT(12),
  85. STATUS_AXI_INT = BIT(11),
  86. STATUS_READ_DATA_AVAILABLE = BIT(7),
  87. STATUS_BUSY = BIT(6),
  88. STATUS_INIT_DONE = BIT(5),
  89. };
  90. /**
  91. * enum control_reg - Description of bit fields in the interrupt_enable_control
  92. * register
  93. * @CONTROL_READ_COMPLETE_EVENT_ENABLE: STATUS_READ_COMPLETE_EVENT will be
  94. * raised in the interrupt_status register
  95. * @CONTROL_WRITE_COMPLETE_EVENT_ENABLE: STATUS_WRITE_COMPLETE_EVENT will be
  96. * raised in the interrupt_status register
  97. * @CONTROL_TIMEOUT_EVENT_ENABLE: STATUS_TIMEOUT_EVENT will be raised in
  98. * the interrupt_status register
  99. * @CONTROL_ERROR_EVENT_ENABLE: STATUS_ERROR_EVENT will be raised in
  100. * the interrupt_status register
  101. * @CONTROL_AXI_INT_ENABLE: STATUS_AXI_INT will be raised in the
  102. * interrupt_status register
  103. * @CONTROL_CMD_NOP: Configure bus to send a NOP command
  104. * for the next transfer
  105. * @CONTROL_CMD_WRITE: Configure bus to do a write transfer
  106. * @CONTROL_CMD_WRITE_POST_INC: Auto-increment address after write
  107. * transfer
  108. * @CONTROL_CMD_READ: Configure bus to do a read transfer
  109. * @CONTROL_CMD_READ_POST_INC: Auto-increment address after read
  110. * transfer
  111. */
  112. enum control_reg {
  113. CONTROL_READ_COMPLETE_EVENT_ENABLE = BIT(15),
  114. CONTROL_WRITE_COMPLETE_EVENT_ENABLE = BIT(14),
  115. CONTROL_TIMEOUT_EVENT_ENABLE = BIT(13),
  116. CONTROL_ERROR_EVENT_ENABLE = BIT(12),
  117. CONTROL_AXI_INT_ENABLE = BIT(11),
  118. CONTROL_CMD_NOP = 0x0,
  119. CONTROL_CMD_WRITE = 0x8,
  120. CONTROL_CMD_WRITE_POST_INC = 0x9,
  121. CONTROL_CMD_READ = 0xa,
  122. CONTROL_CMD_READ_POST_INC = 0xb,
  123. };
  124. /**
  125. * enum axi_cmd - Determine if transfer is read or write transfer
  126. * @AXI_CMD_READ: The transfer should be a read transfer
  127. * @AXI_CMD_WRITE: The transfer should be a write transfer
  128. */
  129. enum axi_cmd {
  130. AXI_CMD_READ,
  131. AXI_CMD_WRITE,
  132. };
  133. /**
  134. * ihs_axi_transfer() - Run transfer on the AXI bus
  135. * @bus: The AXI bus device on which to run the transfer on
  136. * @address: The address to use in the transfer (i.e. which address to
  137. * read/write from/to)
  138. * @cmd: Should the transfer be a read or write transfer?
  139. *
  140. * Return: 0 if OK, -ve on error
  141. */
  142. static int ihs_axi_transfer(struct udevice *bus, ulong address,
  143. enum axi_cmd cmd)
  144. {
  145. struct ihs_axi_priv *priv = dev_get_priv(bus);
  146. /* Try waiting for events up to 10 times */
  147. const uint WAIT_TRIES = 10;
  148. u16 wait_mask = STATUS_TIMEOUT_EVENT |
  149. STATUS_ERROR_EVENT;
  150. u16 complete_flag;
  151. u16 status;
  152. uint k;
  153. if (cmd == AXI_CMD_READ) {
  154. complete_flag = STATUS_READ_COMPLETE_EVENT;
  155. cmd = CONTROL_CMD_READ;
  156. } else {
  157. complete_flag = STATUS_WRITE_COMPLETE_EVENT;
  158. cmd = CONTROL_CMD_WRITE;
  159. }
  160. wait_mask |= complete_flag;
  161. /* Lower 16 bit */
  162. ihs_axi_set(priv->map, address_lsb, address & 0xffff);
  163. /* Upper 16 bit */
  164. ihs_axi_set(priv->map, address_msb, (address >> 16) & 0xffff);
  165. ihs_axi_set(priv->map, interrupt_status, wait_mask);
  166. ihs_axi_set(priv->map, interrupt_enable_control, cmd);
  167. for (k = WAIT_TRIES; k > 0; --k) {
  168. ihs_axi_get(priv->map, interrupt_status, &status);
  169. if (status & wait_mask)
  170. break;
  171. udelay(1);
  172. }
  173. /*
  174. * k == 0 -> Tries ran out with no event we were waiting for actually
  175. * occurring.
  176. */
  177. if (!k)
  178. ihs_axi_get(priv->map, interrupt_status, &status);
  179. if (status & complete_flag)
  180. return 0;
  181. if (status & STATUS_ERROR_EVENT) {
  182. debug("%s: Error occurred during transfer\n", bus->name);
  183. return -EIO;
  184. }
  185. debug("%s: Transfer timed out\n", bus->name);
  186. return -ETIMEDOUT;
  187. }
  188. /*
  189. * API
  190. */
  191. static int ihs_axi_read(struct udevice *dev, ulong address, void *data,
  192. enum axi_size_t size)
  193. {
  194. struct ihs_axi_priv *priv = dev_get_priv(dev);
  195. int ret;
  196. u16 data_lsb, data_msb;
  197. u32 *p = data;
  198. if (size != AXI_SIZE_32) {
  199. debug("%s: transfer size '%d' not supported\n",
  200. dev->name, size);
  201. return -ENOSYS;
  202. }
  203. ret = ihs_axi_transfer(dev, address, AXI_CMD_READ);
  204. if (ret < 0) {
  205. debug("%s: Error during AXI transfer (err = %d)\n",
  206. dev->name, ret);
  207. return ret;
  208. }
  209. ihs_axi_get(priv->map, read_data_lsb, &data_lsb);
  210. ihs_axi_get(priv->map, read_data_msb, &data_msb);
  211. /* Assemble data from two 16-bit words */
  212. *p = (data_msb << 16) | data_lsb;
  213. return 0;
  214. }
  215. static int ihs_axi_write(struct udevice *dev, ulong address, void *data,
  216. enum axi_size_t size)
  217. {
  218. struct ihs_axi_priv *priv = dev_get_priv(dev);
  219. int ret;
  220. u32 *p = data;
  221. if (size != AXI_SIZE_32) {
  222. debug("%s: transfer size '%d' not supported\n",
  223. dev->name, size);
  224. return -ENOSYS;
  225. }
  226. /* Lower 16 bit */
  227. ihs_axi_set(priv->map, write_data_lsb, *p & 0xffff);
  228. /* Upper 16 bit */
  229. ihs_axi_set(priv->map, write_data_msb, (*p >> 16) & 0xffff);
  230. ret = ihs_axi_transfer(dev, address, AXI_CMD_WRITE);
  231. if (ret < 0) {
  232. debug("%s: Error during AXI transfer (err = %d)\n",
  233. dev->name, ret);
  234. return ret;
  235. }
  236. return 0;
  237. }
  238. static const struct udevice_id ihs_axi_ids[] = {
  239. { .compatible = "gdsys,ihs_axi" },
  240. { /* sentinel */ }
  241. };
  242. static const struct axi_ops ihs_axi_ops = {
  243. .read = ihs_axi_read,
  244. .write = ihs_axi_write,
  245. };
  246. static int ihs_axi_probe(struct udevice *dev)
  247. {
  248. struct ihs_axi_priv *priv = dev_get_priv(dev);
  249. regmap_init_mem(dev_ofnode(dev), &priv->map);
  250. return 0;
  251. }
  252. U_BOOT_DRIVER(ihs_axi_bus) = {
  253. .name = "ihs_axi_bus",
  254. .id = UCLASS_AXI,
  255. .of_match = ihs_axi_ids,
  256. .ops = &ihs_axi_ops,
  257. .priv_auto = sizeof(struct ihs_axi_priv),
  258. .probe = ihs_axi_probe,
  259. };