sata_sil3114.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * This is a driver for Silicon Image sil3114 sata chip modelled on
  7. * the ata_piix driver
  8. */
  9. #include <common.h>
  10. #include <blk.h>
  11. #include <log.h>
  12. #include <part.h>
  13. #include <pci.h>
  14. #include <command.h>
  15. #include <config.h>
  16. #include <asm/byteorder.h>
  17. #include <asm/io.h>
  18. #include <ide.h>
  19. #include <sata.h>
  20. #include <libata.h>
  21. #include <linux/delay.h>
  22. #include "sata_sil3114.h"
  23. /* Convert sectorsize to wordsize */
  24. #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  25. /* Forwards */
  26. u8 sil3114_spin_up (int num);
  27. u8 sil3114_spin_down (int num);
  28. static int sata_bus_softreset (int num);
  29. static void sata_identify (int num, int dev);
  30. static u8 check_power_mode (int num);
  31. static void sata_port (struct sata_ioports *ioport);
  32. static void set_Feature_cmd (int num, int dev);
  33. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  34. unsigned int max, u8 usealtstatus);
  35. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
  36. static void msleep (int count);
  37. static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
  38. static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
  39. static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  40. {
  41. while (words--) {
  42. __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
  43. }
  44. }
  45. static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  46. {
  47. while (words--) {
  48. *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
  49. }
  50. return 0;
  51. }
  52. static int sata_bus_softreset (int num)
  53. {
  54. u8 status = 0;
  55. port[num].dev_mask = 1;
  56. port[num].ctl_reg = 0x08; /*Default value of control reg */
  57. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  58. udelay(10);
  59. writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
  60. udelay(10);
  61. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  62. /* spec mandates ">= 2ms" before checking status.
  63. * We wait 150ms, because that was the magic delay used for
  64. * ATAPI devices in Hale Landis's ATADRVR, for the period of time
  65. * between when the ATA command register is written, and then
  66. * status is checked. Because waiting for "a while" before
  67. * checking status is fine, post SRST, we perform this magic
  68. * delay here as well.
  69. */
  70. msleep (150);
  71. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
  72. while ((status & ATA_BUSY)) {
  73. msleep (100);
  74. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
  75. }
  76. if (status & ATA_BUSY) {
  77. printf ("ata%u is slow to respond,plz be patient\n", num);
  78. }
  79. while ((status & ATA_BUSY)) {
  80. msleep (100);
  81. status = sata_chk_status (&port[num].ioaddr, 0);
  82. }
  83. if (status & ATA_BUSY) {
  84. printf ("ata%u failed to respond : ", num);
  85. printf ("bus reset failed\n");
  86. port[num].dev_mask = 0;
  87. return 1;
  88. }
  89. return 0;
  90. }
  91. static void sata_identify (int num, int dev)
  92. {
  93. u8 cmd = 0, status = 0, devno = num;
  94. u16 iobuf[ATA_SECTOR_WORDS];
  95. u64 n_sectors = 0;
  96. memset (iobuf, 0, sizeof (iobuf));
  97. if (!(port[num].dev_mask & 0x01)) {
  98. printf ("dev%d is not present on port#%d\n", dev, num);
  99. return;
  100. }
  101. debug ("port=%d dev=%d\n", num, dev);
  102. status = 0;
  103. cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
  104. writeb (cmd, port[num].ioaddr.command_addr);
  105. readb (port[num].ioaddr.altstatus_addr);
  106. udelay(10);
  107. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
  108. if (status & ATA_ERR) {
  109. printf ("\ndevice not responding\n");
  110. port[num].dev_mask &= ~0x01;
  111. return;
  112. }
  113. input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
  114. ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
  115. debug ("Specific config: %x\n", iobuf[2]);
  116. /* we require LBA and DMA support (bits 8 & 9 of word 49) */
  117. if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
  118. debug ("ata%u: no dma/lba\n", num);
  119. }
  120. #ifdef DEBUG
  121. ata_dump_id (iobuf);
  122. #endif
  123. n_sectors = ata_id_n_sectors (iobuf);
  124. if (n_sectors == 0) {
  125. port[num].dev_mask &= ~0x01;
  126. return;
  127. }
  128. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
  129. ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
  130. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
  131. ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
  132. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
  133. ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
  134. /* TODO - atm we asume harddisk ie not removable */
  135. sata_dev_desc[devno].removable = 0;
  136. sata_dev_desc[devno].lba = (u32) n_sectors;
  137. debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
  138. #ifdef CONFIG_LBA48
  139. if (iobuf[83] & (1 << 10)) {
  140. sata_dev_desc[devno].lba48 = 1;
  141. } else {
  142. sata_dev_desc[devno].lba48 = 0;
  143. }
  144. #endif
  145. /* assuming HD */
  146. sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
  147. sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
  148. sata_dev_desc[devno].lun = 0; /* just to fill something in... */
  149. }
  150. static void set_Feature_cmd (int num, int dev)
  151. {
  152. u8 status = 0;
  153. if (!(port[num].dev_mask & 0x01)) {
  154. debug ("dev%d is not present on port#%d\n", dev, num);
  155. return;
  156. }
  157. writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
  158. writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
  159. writeb (0, port[num].ioaddr.lbal_addr);
  160. writeb (0, port[num].ioaddr.lbam_addr);
  161. writeb (0, port[num].ioaddr.lbah_addr);
  162. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  163. writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
  164. udelay(50);
  165. msleep (150);
  166. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  167. if ((status & (ATA_BUSY | ATA_ERR))) {
  168. printf ("Error : status 0x%02x\n", status);
  169. port[num].dev_mask &= ~0x01;
  170. }
  171. }
  172. u8 sil3114_spin_down (int num)
  173. {
  174. u8 status = 0;
  175. debug ("Spin down disk\n");
  176. if (!(port[num].dev_mask & 0x01)) {
  177. debug ("Device ata%d is not present\n", num);
  178. return 1;
  179. }
  180. if ((status = check_power_mode (num)) == 0x00) {
  181. debug ("Already in standby\n");
  182. return 0;
  183. }
  184. if (status == 0x01) {
  185. printf ("Failed to check power mode on ata%d\n", num);
  186. return 1;
  187. }
  188. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  189. printf ("Device ata%d not ready\n", num);
  190. return 1;
  191. }
  192. writeb (0x00, port[num].ioaddr.feature_addr);
  193. writeb (0x00, port[num].ioaddr.nsect_addr);
  194. writeb (0x00, port[num].ioaddr.lbal_addr);
  195. writeb (0x00, port[num].ioaddr.lbam_addr);
  196. writeb (0x00, port[num].ioaddr.lbah_addr);
  197. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  198. writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
  199. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  200. if ((status & (ATA_BUSY | ATA_ERR))) {
  201. printf ("Error waiting for disk spin down: status 0x%02x\n",
  202. status);
  203. port[num].dev_mask &= ~0x01;
  204. return 1;
  205. }
  206. return 0;
  207. }
  208. u8 sil3114_spin_up (int num)
  209. {
  210. u8 status = 0;
  211. debug ("Spin up disk\n");
  212. if (!(port[num].dev_mask & 0x01)) {
  213. debug ("Device ata%d is not present\n", num);
  214. return 1;
  215. }
  216. if ((status = check_power_mode (num)) != 0x00) {
  217. if (status == 0x01) {
  218. printf ("Failed to check power mode on ata%d\n", num);
  219. return 1;
  220. } else {
  221. /* should be up and running already */
  222. return 0;
  223. }
  224. }
  225. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  226. printf ("Device ata%d not ready\n", num);
  227. return 1;
  228. }
  229. debug ("Stautus of device check: %d\n", status);
  230. writeb (0x00, port[num].ioaddr.feature_addr);
  231. writeb (0x00, port[num].ioaddr.nsect_addr);
  232. writeb (0x00, port[num].ioaddr.lbal_addr);
  233. writeb (0x00, port[num].ioaddr.lbam_addr);
  234. writeb (0x00, port[num].ioaddr.lbah_addr);
  235. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  236. writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
  237. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  238. if ((status & (ATA_BUSY | ATA_ERR))) {
  239. printf ("Error waiting for disk spin up: status 0x%02x\n",
  240. status);
  241. port[num].dev_mask &= ~0x01;
  242. return 1;
  243. }
  244. /* Wait for disk to enter Active state */
  245. do {
  246. msleep (10);
  247. status = check_power_mode (num);
  248. } while ((status == 0x00) || (status == 0x80));
  249. if (status == 0x01) {
  250. printf ("Falied waiting for disk to spin up\n");
  251. return 1;
  252. }
  253. return 0;
  254. }
  255. /* Return value is not the usual here
  256. * 0x00 - Device stand by
  257. * 0x01 - Operation failed
  258. * 0x80 - Device idle
  259. * 0xff - Device active
  260. */
  261. static u8 check_power_mode (int num)
  262. {
  263. u8 status = 0;
  264. u8 res = 0;
  265. if (!(port[num].dev_mask & 0x01)) {
  266. debug ("Device ata%d is not present\n", num);
  267. return 1;
  268. }
  269. if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
  270. printf ("Device ata%d not ready\n", num);
  271. return 1;
  272. }
  273. writeb (0, port[num].ioaddr.feature_addr);
  274. writeb (0, port[num].ioaddr.nsect_addr);
  275. writeb (0, port[num].ioaddr.lbal_addr);
  276. writeb (0, port[num].ioaddr.lbam_addr);
  277. writeb (0, port[num].ioaddr.lbah_addr);
  278. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  279. writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
  280. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  281. if ((status & (ATA_BUSY | ATA_ERR))) {
  282. printf
  283. ("Error waiting for check power mode complete : status 0x%02x\n",
  284. status);
  285. port[num].dev_mask &= ~0x01;
  286. return 1;
  287. }
  288. res = readb (port[num].ioaddr.nsect_addr);
  289. debug ("Check powermode: %d\n", res);
  290. return res;
  291. }
  292. static void sata_port (struct sata_ioports *ioport)
  293. {
  294. ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
  295. ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
  296. ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
  297. ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
  298. ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
  299. ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
  300. ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
  301. ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
  302. ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
  303. ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
  304. }
  305. static u8 wait_for_irq (int num, unsigned int max)
  306. {
  307. u32 port = iobase[5];
  308. switch (num) {
  309. case 0:
  310. port += VND_TF_CNST_CH0;
  311. break;
  312. case 1:
  313. port += VND_TF_CNST_CH1;
  314. break;
  315. case 2:
  316. port += VND_TF_CNST_CH2;
  317. break;
  318. case 3:
  319. port += VND_TF_CNST_CH3;
  320. break;
  321. default:
  322. return 1;
  323. }
  324. do {
  325. if (readl (port) & VND_TF_CNST_INTST) {
  326. break;
  327. }
  328. udelay(1000);
  329. max--;
  330. } while ((max > 0));
  331. return (max == 0);
  332. }
  333. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  334. unsigned int max, u8 usealtstatus)
  335. {
  336. u8 status;
  337. do {
  338. if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
  339. break;
  340. }
  341. udelay(1000);
  342. max--;
  343. } while ((status & bits) && (max > 0));
  344. return status;
  345. }
  346. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
  347. {
  348. if (!usealtstatus) {
  349. return readb (ioaddr->status_addr);
  350. } else {
  351. return readb (ioaddr->altstatus_addr);
  352. }
  353. }
  354. static void msleep (int count)
  355. {
  356. int i;
  357. for (i = 0; i < count; i++)
  358. udelay(1000);
  359. }
  360. /* Read up to 255 sectors
  361. *
  362. * Returns sectors read
  363. */
  364. static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
  365. uchar lba48)
  366. {
  367. u8 sr = 0;
  368. u8 status;
  369. u64 blknr = (u64) block;
  370. if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
  371. printf ("Device ata%d not ready\n", device);
  372. return 0;
  373. }
  374. /* Set up transfer */
  375. #ifdef CONFIG_LBA48
  376. if (lba48) {
  377. /* write high bits */
  378. writeb (0, port[device].ioaddr.nsect_addr);
  379. writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
  380. writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
  381. writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
  382. }
  383. #endif
  384. writeb (blkcnt, port[device].ioaddr.nsect_addr);
  385. writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
  386. writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
  387. writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
  388. #ifdef CONFIG_LBA48
  389. if (lba48) {
  390. writeb (ATA_LBA, port[device].ioaddr.device_addr);
  391. writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
  392. } else
  393. #endif
  394. {
  395. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  396. port[device].ioaddr.device_addr);
  397. writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
  398. }
  399. status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
  400. if (status & ATA_BUSY) {
  401. u8 err = 0;
  402. printf ("Device %d not responding status %d\n", device, status);
  403. err = readb (port[device].ioaddr.error_addr);
  404. printf ("Error reg = 0x%x\n", err);
  405. return (sr);
  406. }
  407. while (blkcnt--) {
  408. if (wait_for_irq (device, 500)) {
  409. printf ("ata%u irq failed\n", device);
  410. return sr;
  411. }
  412. status = sata_chk_status (&port[device].ioaddr, 0);
  413. if (status & ATA_ERR) {
  414. printf ("ata%u error %d\n", device,
  415. readb (port[device].ioaddr.error_addr));
  416. return sr;
  417. }
  418. /* Read one sector */
  419. input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
  420. buff += ATA_SECTOR_WORDS;
  421. sr++;
  422. }
  423. return sr;
  424. }
  425. ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
  426. {
  427. ulong n = 0, sread;
  428. u16 *buffer = (u16 *) buff;
  429. u8 status = 0;
  430. u64 blknr = (u64) block;
  431. unsigned char lba48 = 0;
  432. #ifdef CONFIG_LBA48
  433. if (blknr > 0xfffffff) {
  434. if (!sata_dev_desc[device].lba48) {
  435. printf ("Drive doesn't support 48-bit addressing\n");
  436. return 0;
  437. }
  438. /* more than 28 bits used, use 48bit mode */
  439. lba48 = 1;
  440. }
  441. #endif
  442. while (blkcnt > 0) {
  443. if (blkcnt > 255) {
  444. sread = 255;
  445. } else {
  446. sread = blkcnt;
  447. }
  448. status = do_one_read (device, blknr, sread, buffer, lba48);
  449. if (status != sread) {
  450. printf ("Read failed\n");
  451. return n;
  452. }
  453. blkcnt -= sread;
  454. blknr += sread;
  455. n += sread;
  456. buffer += sread * ATA_SECTOR_WORDS;
  457. }
  458. return n;
  459. }
  460. ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
  461. {
  462. ulong n = 0;
  463. u16 *buffer = (u16 *) buff;
  464. unsigned char status = 0, num = 0;
  465. u64 blknr = (u64) block;
  466. #ifdef CONFIG_LBA48
  467. unsigned char lba48 = 0;
  468. if (blknr > 0xfffffff) {
  469. if (!sata_dev_desc[device].lba48) {
  470. printf ("Drive doesn't support 48-bit addressing\n");
  471. return 0;
  472. }
  473. /* more than 28 bits used, use 48bit mode */
  474. lba48 = 1;
  475. }
  476. #endif
  477. /*Port Number */
  478. num = device;
  479. while (blkcnt-- > 0) {
  480. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
  481. if (status & ATA_BUSY) {
  482. printf ("ata%u failed to respond\n", port[num].port_no);
  483. return n;
  484. }
  485. #ifdef CONFIG_LBA48
  486. if (lba48) {
  487. /* write high bits */
  488. writeb (0, port[num].ioaddr.nsect_addr);
  489. writeb ((blknr >> 24) & 0xFF,
  490. port[num].ioaddr.lbal_addr);
  491. writeb ((blknr >> 32) & 0xFF,
  492. port[num].ioaddr.lbam_addr);
  493. writeb ((blknr >> 40) & 0xFF,
  494. port[num].ioaddr.lbah_addr);
  495. }
  496. #endif
  497. writeb (1, port[num].ioaddr.nsect_addr);
  498. writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
  499. writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
  500. writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
  501. #ifdef CONFIG_LBA48
  502. if (lba48) {
  503. writeb (ATA_LBA, port[num].ioaddr.device_addr);
  504. writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
  505. } else
  506. #endif
  507. {
  508. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  509. port[num].ioaddr.device_addr);
  510. writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
  511. }
  512. msleep (50);
  513. /*may take up to 4 sec */
  514. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
  515. if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
  516. printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
  517. device, (ulong) blknr, status);
  518. return (n);
  519. }
  520. output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
  521. readb (port[num].ioaddr.altstatus_addr);
  522. udelay(50);
  523. ++n;
  524. ++blknr;
  525. buffer += ATA_SECTOR_WORDS;
  526. }
  527. return n;
  528. }
  529. /* Driver implementation */
  530. static u8 sil_get_device_cache_line (pci_dev_t pdev)
  531. {
  532. u8 cache_line = 0;
  533. pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
  534. return cache_line;
  535. }
  536. int init_sata (int dev)
  537. {
  538. static u8 init_done = 0;
  539. static int res = 1;
  540. pci_dev_t devno;
  541. u8 cls = 0;
  542. u16 cmd = 0;
  543. u32 sconf = 0;
  544. if (init_done) {
  545. return res;
  546. }
  547. init_done = 1;
  548. if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
  549. res = 1;
  550. return res;
  551. }
  552. /* Read out all BARs, even though we only use MMIO from BAR5 */
  553. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
  554. pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
  555. pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
  556. pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
  557. pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
  558. pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
  559. if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
  560. (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
  561. (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
  562. printf ("Error no base addr for SATA controller\n");
  563. res = 1;
  564. return res;
  565. }
  566. /* mask off unused bits */
  567. iobase[0] &= 0xfffffffc;
  568. iobase[1] &= 0xfffffff8;
  569. iobase[2] &= 0xfffffffc;
  570. iobase[3] &= 0xfffffff8;
  571. iobase[4] &= 0xfffffff0;
  572. iobase[5] &= 0xfffffc00;
  573. /* from sata_sil in Linux kernel */
  574. cls = sil_get_device_cache_line (devno);
  575. if (cls) {
  576. cls >>= 3;
  577. cls++; /* cls = (line_size/8)+1 */
  578. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
  579. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
  580. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
  581. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
  582. } else {
  583. printf ("Cache line not set. Driver may not function\n");
  584. }
  585. /* Enable operation */
  586. pci_read_config_word (devno, PCI_COMMAND, &cmd);
  587. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  588. pci_write_config_word (devno, PCI_COMMAND, cmd);
  589. /* Disable interrupt usage */
  590. pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
  591. sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
  592. pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
  593. res = 0;
  594. return res;
  595. }
  596. int reset_sata(int dev)
  597. {
  598. return 0;
  599. }
  600. /* Check if device is connected to port */
  601. int sata_bus_probe (int portno)
  602. {
  603. u32 port = iobase[5];
  604. u32 val;
  605. switch (portno) {
  606. case 0:
  607. port += VND_SSTATUS_CH0;
  608. break;
  609. case 1:
  610. port += VND_SSTATUS_CH1;
  611. break;
  612. case 2:
  613. port += VND_SSTATUS_CH2;
  614. break;
  615. case 3:
  616. port += VND_SSTATUS_CH3;
  617. break;
  618. default:
  619. return 0;
  620. }
  621. val = readl (port);
  622. if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
  623. return 1;
  624. } else {
  625. return 0;
  626. }
  627. }
  628. int sata_phy_reset (int portno)
  629. {
  630. u32 port = iobase[5];
  631. u32 val;
  632. switch (portno) {
  633. case 0:
  634. port += VND_SCONTROL_CH0;
  635. break;
  636. case 1:
  637. port += VND_SCONTROL_CH1;
  638. break;
  639. case 2:
  640. port += VND_SCONTROL_CH2;
  641. break;
  642. case 3:
  643. port += VND_SCONTROL_CH3;
  644. break;
  645. default:
  646. return 0;
  647. }
  648. val = readl (port);
  649. writel (val | SATA_SC_DET_RST, port);
  650. msleep (150);
  651. writel (val & ~SATA_SC_DET_RST, port);
  652. return 0;
  653. }
  654. int scan_sata (int dev)
  655. {
  656. /* A bit brain dead, but the code has a legacy */
  657. switch (dev) {
  658. case 0:
  659. port[0].port_no = 0;
  660. port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
  661. port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
  662. (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
  663. port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
  664. break;
  665. #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
  666. case 1:
  667. port[1].port_no = 0;
  668. port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
  669. port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
  670. (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
  671. port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
  672. break;
  673. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
  674. case 2:
  675. port[2].port_no = 0;
  676. port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
  677. port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
  678. (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
  679. port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
  680. break;
  681. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
  682. case 3:
  683. port[3].port_no = 0;
  684. port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
  685. port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
  686. (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
  687. port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
  688. break;
  689. #endif
  690. default:
  691. printf ("Tried to scan unknown port: ata%d\n", dev);
  692. return 1;
  693. }
  694. /* Initialize other registers */
  695. sata_port (&port[dev].ioaddr);
  696. /* Check for attached device */
  697. if (!sata_bus_probe (dev)) {
  698. port[dev].port_state = 0;
  699. debug ("SATA#%d port is not present\n", dev);
  700. } else {
  701. debug ("SATA#%d port is present\n", dev);
  702. if (sata_bus_softreset (dev)) {
  703. /* soft reset failed, try a hard one */
  704. sata_phy_reset (dev);
  705. if (sata_bus_softreset (dev)) {
  706. port[dev].port_state = 0;
  707. } else {
  708. port[dev].port_state = 1;
  709. }
  710. } else {
  711. port[dev].port_state = 1;
  712. }
  713. }
  714. if (port[dev].port_state == 1) {
  715. /* Probe device and set xfer mode */
  716. sata_identify (dev, 0);
  717. set_Feature_cmd (dev, 0);
  718. }
  719. return 0;
  720. }