sata_sil.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Tang Yuantian <b29983@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <log.h>
  10. #include <pci.h>
  11. #include <command.h>
  12. #include <asm/byteorder.h>
  13. #include <malloc.h>
  14. #include <asm/io.h>
  15. #include <fis.h>
  16. #include <sata.h>
  17. #include <libata.h>
  18. #include <sata.h>
  19. #include <linux/delay.h>
  20. #if CONFIG_IS_ENABLED(BLK)
  21. #include <dm.h>
  22. #include <blk.h>
  23. #include <dm/device-internal.h>
  24. #endif
  25. #include "sata_sil.h"
  26. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  27. /* just compatible ahci_ops */
  28. struct sil_ops {
  29. int *rev0;
  30. int *rev1;
  31. int (*scan)(struct udevice *dev);
  32. };
  33. static struct sata_info sata_info;
  34. static struct pci_device_id supported[] = {
  35. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131) },
  36. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132) },
  37. { PCI_DEVICE(PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124) },
  38. {}
  39. };
  40. static void sil_sata_dump_fis(struct sata_fis_d2h *s)
  41. {
  42. printf("Status FIS dump:\n");
  43. printf("fis_type: %02x\n", s->fis_type);
  44. printf("pm_port_i: %02x\n", s->pm_port_i);
  45. printf("status: %02x\n", s->status);
  46. printf("error: %02x\n", s->error);
  47. printf("lba_low: %02x\n", s->lba_low);
  48. printf("lba_mid: %02x\n", s->lba_mid);
  49. printf("lba_high: %02x\n", s->lba_high);
  50. printf("device: %02x\n", s->device);
  51. printf("lba_low_exp: %02x\n", s->lba_low_exp);
  52. printf("lba_mid_exp: %02x\n", s->lba_mid_exp);
  53. printf("lba_high_exp: %02x\n", s->lba_high_exp);
  54. printf("res1: %02x\n", s->res1);
  55. printf("sector_count: %02x\n", s->sector_count);
  56. printf("sector_count_exp: %02x\n", s->sector_count_exp);
  57. }
  58. static const char *sata_spd_string(unsigned int speed)
  59. {
  60. static const char * const spd_str[] = {
  61. "1.5 Gbps",
  62. "3.0 Gbps",
  63. "6.0 Gbps",
  64. };
  65. if ((speed - 1) > 2)
  66. return "<unknown>";
  67. return spd_str[speed - 1];
  68. }
  69. static u32 ata_wait_register(void *reg, u32 mask,
  70. u32 val, int timeout_msec)
  71. {
  72. u32 tmp;
  73. tmp = readl(reg);
  74. while ((tmp & mask) == val && timeout_msec > 0) {
  75. mdelay(1);
  76. timeout_msec--;
  77. tmp = readl(reg);
  78. }
  79. return tmp;
  80. }
  81. static void sil_config_port(void *port)
  82. {
  83. /* configure IRQ WoC */
  84. writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
  85. /* zero error counters. */
  86. writew(0x8000, port + PORT_DECODE_ERR_THRESH);
  87. writew(0x8000, port + PORT_CRC_ERR_THRESH);
  88. writew(0x8000, port + PORT_HSHK_ERR_THRESH);
  89. writew(0x0000, port + PORT_DECODE_ERR_CNT);
  90. writew(0x0000, port + PORT_CRC_ERR_CNT);
  91. writew(0x0000, port + PORT_HSHK_ERR_CNT);
  92. /* always use 64bit activation */
  93. writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
  94. /* clear port multiplier enable and resume bits */
  95. writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
  96. }
  97. static int sil_init_port(void *port)
  98. {
  99. u32 tmp;
  100. writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
  101. ata_wait_register(port + PORT_CTRL_STAT,
  102. PORT_CS_INIT, PORT_CS_INIT, 100);
  103. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  104. PORT_CS_RDY, 0, 100);
  105. if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
  106. return 1;
  107. return 0;
  108. }
  109. static void sil_read_fis(struct sil_sata *sata, int tag,
  110. struct sata_fis_d2h *fis)
  111. {
  112. void *port = sata->port;
  113. struct sil_prb *prb;
  114. int i;
  115. u32 *src, *dst;
  116. prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
  117. src = (u32 *)&prb->fis;
  118. dst = (u32 *)fis;
  119. for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
  120. *dst++ = readl(src++);
  121. }
  122. static int sil_exec_cmd(struct sil_sata *sata, struct sil_cmd_block *pcmd,
  123. int tag)
  124. {
  125. void *port = sata->port;
  126. u64 paddr = virt_to_bus(sata->devno, pcmd);
  127. u32 irq_mask, irq_stat;
  128. int rc;
  129. writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
  130. /* better to add momery barrior here */
  131. writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
  132. writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
  133. irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
  134. irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
  135. 0, 10000);
  136. /* clear IRQs */
  137. writel(irq_mask, port + PORT_IRQ_STAT);
  138. irq_stat >>= PORT_IRQ_RAW_SHIFT;
  139. if (irq_stat & PORT_IRQ_COMPLETE)
  140. rc = 0;
  141. else {
  142. /* force port into known state */
  143. sil_init_port(port);
  144. if (irq_stat & PORT_IRQ_ERROR)
  145. rc = 1; /* error */
  146. else
  147. rc = 2; /* busy */
  148. }
  149. return rc;
  150. }
  151. static int sil_cmd_set_feature(struct sil_sata *sata)
  152. {
  153. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  154. struct sata_fis_d2h fis;
  155. u8 udma_cap;
  156. int ret;
  157. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  158. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  159. pcmd->prb.fis.pm_port_c = (1 << 7);
  160. pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
  161. pcmd->prb.fis.features = SETFEATURES_XFER;
  162. /* First check the device capablity */
  163. udma_cap = (u8)(sata->udma & 0xff);
  164. debug("udma_cap %02x\n", udma_cap);
  165. if (udma_cap == ATA_UDMA6)
  166. pcmd->prb.fis.sector_count = XFER_UDMA_6;
  167. if (udma_cap == ATA_UDMA5)
  168. pcmd->prb.fis.sector_count = XFER_UDMA_5;
  169. if (udma_cap == ATA_UDMA4)
  170. pcmd->prb.fis.sector_count = XFER_UDMA_4;
  171. if (udma_cap == ATA_UDMA3)
  172. pcmd->prb.fis.sector_count = XFER_UDMA_3;
  173. ret = sil_exec_cmd(sata, pcmd, 0);
  174. if (ret) {
  175. sil_read_fis(sata, 0, &fis);
  176. printf("Err: exe cmd(0x%x).\n",
  177. readl(sata->port + PORT_SERROR));
  178. sil_sata_dump_fis(&fis);
  179. return 1;
  180. }
  181. return 0;
  182. }
  183. static void sil_sata_init_wcache(struct sil_sata *sata, u16 *id)
  184. {
  185. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  186. sata->wcache = 1;
  187. if (ata_id_has_flush(id))
  188. sata->flush = 1;
  189. if (ata_id_has_flush_ext(id))
  190. sata->flush_ext = 1;
  191. }
  192. static void sil_sata_set_feature_by_id(struct sil_sata *sata, u16 *id)
  193. {
  194. #ifdef CONFIG_LBA48
  195. /* Check if support LBA48 */
  196. if (ata_id_has_lba48(id)) {
  197. sata->lba48 = 1;
  198. debug("Device supports LBA48\n");
  199. } else {
  200. debug("Device supports LBA28\n");
  201. }
  202. #endif
  203. sil_sata_init_wcache(sata, id);
  204. sil_cmd_set_feature(sata);
  205. }
  206. static int sil_cmd_identify_device(struct sil_sata *sata, u16 *id)
  207. {
  208. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  209. struct sata_fis_d2h fis;
  210. int ret;
  211. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  212. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  213. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  214. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  215. pcmd->prb.fis.pm_port_c = (1 << 7);
  216. pcmd->prb.fis.command = ATA_CMD_ID_ATA;
  217. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
  218. pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
  219. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  220. ret = sil_exec_cmd(sata, pcmd, 0);
  221. if (ret) {
  222. sil_read_fis(sata, 0, &fis);
  223. printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
  224. sil_sata_dump_fis(&fis);
  225. return 1;
  226. }
  227. ata_swap_buf_le16(id, ATA_ID_WORDS);
  228. return 0;
  229. }
  230. static int sil_cmd_soft_reset(struct sil_sata *sata)
  231. {
  232. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  233. struct sata_fis_d2h fis;
  234. void *port = sata->port;
  235. int ret;
  236. /* put the port into known state */
  237. if (sil_init_port(port)) {
  238. printf("SRST: port %d not ready\n", sata->id);
  239. return 1;
  240. }
  241. memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
  242. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
  243. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  244. pcmd->prb.fis.pm_port_c = 0xf;
  245. ret = sil_exec_cmd(sata, &cmdb, 0);
  246. if (ret) {
  247. sil_read_fis(sata, 0, &fis);
  248. printf("SRST cmd error.\n");
  249. sil_sata_dump_fis(&fis);
  250. return 1;
  251. }
  252. return 0;
  253. }
  254. static ulong sil_sata_rw_cmd(struct sil_sata *sata, ulong start, ulong blkcnt,
  255. u8 *buffer, int is_write)
  256. {
  257. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  258. struct sata_fis_d2h fis;
  259. u64 block;
  260. int ret;
  261. block = (u64)start;
  262. memset(pcmd, 0, sizeof(struct sil_cmd_block));
  263. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  264. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  265. pcmd->prb.fis.pm_port_c = (1 << 7);
  266. if (is_write) {
  267. pcmd->prb.fis.command = ATA_CMD_WRITE;
  268. pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
  269. } else {
  270. pcmd->prb.fis.command = ATA_CMD_READ;
  271. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  272. }
  273. pcmd->prb.fis.device = ATA_LBA;
  274. pcmd->prb.fis.device |= (block >> 24) & 0xf;
  275. pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
  276. pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
  277. pcmd->prb.fis.lba_low = block & 0xff;
  278. pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
  279. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
  280. pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
  281. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  282. ret = sil_exec_cmd(sata, pcmd, 0);
  283. if (ret) {
  284. sil_read_fis(sata, 0, &fis);
  285. printf("Err: rw cmd(0x%08x).\n",
  286. readl(sata->port + PORT_SERROR));
  287. sil_sata_dump_fis(&fis);
  288. return 1;
  289. }
  290. return blkcnt;
  291. }
  292. static ulong sil_sata_rw_cmd_ext(struct sil_sata *sata, ulong start,
  293. ulong blkcnt, u8 *buffer, int is_write)
  294. {
  295. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  296. struct sata_fis_d2h fis;
  297. u64 block;
  298. int ret;
  299. block = (u64)start;
  300. memset(pcmd, 0, sizeof(struct sil_cmd_block));
  301. pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
  302. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  303. pcmd->prb.fis.pm_port_c = (1 << 7);
  304. if (is_write) {
  305. pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
  306. pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
  307. } else {
  308. pcmd->prb.fis.command = ATA_CMD_READ_EXT;
  309. pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
  310. }
  311. pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
  312. pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
  313. pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
  314. pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
  315. pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
  316. pcmd->prb.fis.lba_low = block & 0xff;
  317. pcmd->prb.fis.device = ATA_LBA;
  318. pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
  319. pcmd->prb.fis.sector_count = blkcnt & 0xff;
  320. pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
  321. pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
  322. pcmd->sge.flags = cpu_to_le32(SGE_TRM);
  323. ret = sil_exec_cmd(sata, pcmd, 0);
  324. if (ret) {
  325. sil_read_fis(sata, 0, &fis);
  326. printf("Err: rw ext cmd(0x%08x).\n",
  327. readl(sata->port + PORT_SERROR));
  328. sil_sata_dump_fis(&fis);
  329. return 1;
  330. }
  331. return blkcnt;
  332. }
  333. static ulong sil_sata_rw_lba28(struct sil_sata *sata, ulong blknr,
  334. lbaint_t blkcnt, const void *buffer,
  335. int is_write)
  336. {
  337. ulong start, blks, max_blks;
  338. u8 *addr;
  339. start = blknr;
  340. blks = blkcnt;
  341. addr = (u8 *)buffer;
  342. max_blks = ATA_MAX_SECTORS;
  343. do {
  344. if (blks > max_blks) {
  345. sil_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  346. start += max_blks;
  347. blks -= max_blks;
  348. addr += ATA_SECT_SIZE * max_blks;
  349. } else {
  350. sil_sata_rw_cmd(sata, start, blks, addr, is_write);
  351. start += blks;
  352. blks = 0;
  353. addr += ATA_SECT_SIZE * blks;
  354. }
  355. } while (blks != 0);
  356. return blkcnt;
  357. }
  358. static ulong sil_sata_rw_lba48(struct sil_sata *sata, ulong blknr,
  359. lbaint_t blkcnt, const void *buffer,
  360. int is_write)
  361. {
  362. ulong start, blks, max_blks;
  363. u8 *addr;
  364. start = blknr;
  365. blks = blkcnt;
  366. addr = (u8 *)buffer;
  367. max_blks = ATA_MAX_SECTORS_LBA48;
  368. do {
  369. if (blks > max_blks) {
  370. sil_sata_rw_cmd_ext(sata, start, max_blks,
  371. addr, is_write);
  372. start += max_blks;
  373. blks -= max_blks;
  374. addr += ATA_SECT_SIZE * max_blks;
  375. } else {
  376. sil_sata_rw_cmd_ext(sata, start, blks,
  377. addr, is_write);
  378. start += blks;
  379. blks = 0;
  380. addr += ATA_SECT_SIZE * blks;
  381. }
  382. } while (blks != 0);
  383. return blkcnt;
  384. }
  385. static void sil_sata_cmd_flush_cache(struct sil_sata *sata)
  386. {
  387. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  388. memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
  389. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  390. pcmd->prb.fis.pm_port_c = (1 << 7);
  391. pcmd->prb.fis.command = ATA_CMD_FLUSH;
  392. sil_exec_cmd(sata, pcmd, 0);
  393. }
  394. static void sil_sata_cmd_flush_cache_ext(struct sil_sata *sata)
  395. {
  396. struct sil_cmd_block cmdb, *pcmd = &cmdb;
  397. memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
  398. pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  399. pcmd->prb.fis.pm_port_c = (1 << 7);
  400. pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
  401. sil_exec_cmd(sata, pcmd, 0);
  402. }
  403. /*
  404. * SATA interface between low level driver and command layer
  405. */
  406. #if !CONFIG_IS_ENABLED(BLK)
  407. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  408. {
  409. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  410. #else
  411. static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  412. void *buffer)
  413. {
  414. struct sil_sata_priv *priv = dev_get_plat(dev);
  415. int port_number = priv->port_num;
  416. struct sil_sata *sata = priv->sil_sata_desc[port_number];
  417. #endif
  418. ulong rc;
  419. if (sata->lba48)
  420. rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, READ_CMD);
  421. else
  422. rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, READ_CMD);
  423. return rc;
  424. }
  425. /*
  426. * SATA interface between low level driver and command layer
  427. */
  428. #if !CONFIG_IS_ENABLED(BLK)
  429. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  430. {
  431. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  432. #else
  433. ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  434. const void *buffer)
  435. {
  436. struct sil_sata_priv *priv = dev_get_plat(dev);
  437. int port_number = priv->port_num;
  438. struct sil_sata *sata = priv->sil_sata_desc[port_number];
  439. #endif
  440. ulong rc;
  441. if (sata->lba48) {
  442. rc = sil_sata_rw_lba48(sata, blknr, blkcnt, buffer, WRITE_CMD);
  443. if (sata->wcache && sata->flush_ext)
  444. sil_sata_cmd_flush_cache_ext(sata);
  445. } else {
  446. rc = sil_sata_rw_lba28(sata, blknr, blkcnt, buffer, WRITE_CMD);
  447. if (sata->wcache && sata->flush)
  448. sil_sata_cmd_flush_cache(sata);
  449. }
  450. return rc;
  451. }
  452. #if !CONFIG_IS_ENABLED(BLK)
  453. static int sil_init_sata(int dev)
  454. {
  455. #else
  456. static int sil_init_sata(struct udevice *uc_dev, int dev)
  457. {
  458. struct sil_sata_priv *priv = dev_get_plat(uc_dev);
  459. #endif
  460. struct sil_sata *sata;
  461. void *port;
  462. u32 tmp;
  463. int cnt;
  464. printf("SATA#%d:\n", dev);
  465. port = (void *)sata_info.iobase[1] +
  466. PORT_REGS_SIZE * (dev - sata_info.portbase);
  467. /* Initial PHY setting */
  468. writel(0x20c, port + PORT_PHY_CFG);
  469. /* clear port RST */
  470. tmp = readl(port + PORT_CTRL_STAT);
  471. if (tmp & PORT_CS_PORT_RST) {
  472. writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
  473. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  474. PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
  475. if (tmp & PORT_CS_PORT_RST)
  476. printf("Err: Failed to clear port RST\n");
  477. }
  478. /* Check if device is present */
  479. for (cnt = 0; cnt < 100; cnt++) {
  480. tmp = readl(port + PORT_SSTATUS);
  481. if ((tmp & 0xF) == 0x3)
  482. break;
  483. mdelay(1);
  484. }
  485. tmp = readl(port + PORT_SSTATUS);
  486. if ((tmp & 0xf) != 0x3) {
  487. printf(" (No RDY)\n");
  488. return 1;
  489. }
  490. /* Wait for port ready */
  491. tmp = ata_wait_register(port + PORT_CTRL_STAT,
  492. PORT_CS_RDY, PORT_CS_RDY, 100);
  493. if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
  494. printf("%d port not ready.\n", dev);
  495. return 1;
  496. }
  497. /* configure port */
  498. sil_config_port(port);
  499. /* Reset port */
  500. writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
  501. readl(port + PORT_CTRL_STAT);
  502. tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
  503. PORT_CS_DEV_RST, 100);
  504. if (tmp & PORT_CS_DEV_RST) {
  505. printf("%d port reset failed.\n", dev);
  506. return 1;
  507. }
  508. sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
  509. if (!sata) {
  510. printf("%d no memory.\n", dev);
  511. return 1;
  512. }
  513. memset((void *)sata, 0, sizeof(struct sil_sata));
  514. /* Save the private struct to block device struct */
  515. #if !CONFIG_IS_ENABLED(BLK)
  516. sata_dev_desc[dev].priv = (void *)sata;
  517. sata->devno = sata_info.devno;
  518. #else
  519. priv->sil_sata_desc[dev] = sata;
  520. priv->port_num = dev;
  521. sata->devno = uc_dev->parent;
  522. #endif
  523. sata->id = dev;
  524. sata->port = port;
  525. sprintf(sata->name, "SATA#%d", dev);
  526. sil_cmd_soft_reset(sata);
  527. tmp = readl(port + PORT_SSTATUS);
  528. tmp = (tmp >> 4) & 0xf;
  529. printf(" (%s)\n", sata_spd_string(tmp));
  530. return 0;
  531. }
  532. #if !CONFIG_IS_ENABLED(BLK)
  533. /*
  534. * SATA interface between low level driver and command layer
  535. */
  536. int init_sata(int dev)
  537. {
  538. static int init_done, idx;
  539. pci_dev_t devno;
  540. u16 word;
  541. if (init_done == 1 && dev < sata_info.maxport)
  542. goto init_start;
  543. init_done = 1;
  544. /* Find PCI device(s) */
  545. devno = pci_find_devices(supported, idx++);
  546. if (devno == -1)
  547. return 1;
  548. pci_read_config_word(devno, PCI_DEVICE_ID, &word);
  549. /* get the port count */
  550. word &= 0xf;
  551. sata_info.portbase = 0;
  552. sata_info.maxport = sata_info.portbase + word;
  553. sata_info.devno = devno;
  554. /* Read out all BARs */
  555. sata_info.iobase[0] = (ulong)pci_map_bar(devno,
  556. PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  557. sata_info.iobase[1] = (ulong)pci_map_bar(devno,
  558. PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
  559. /* mask out the unused bits */
  560. sata_info.iobase[0] &= 0xffffff80;
  561. sata_info.iobase[1] &= 0xfffffc00;
  562. /* Enable Bus Mastering and memory region */
  563. pci_write_config_word(devno, PCI_COMMAND,
  564. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  565. /* Check if mem accesses and Bus Mastering are enabled. */
  566. pci_read_config_word(devno, PCI_COMMAND, &word);
  567. if (!(word & PCI_COMMAND_MEMORY) ||
  568. (!(word & PCI_COMMAND_MASTER))) {
  569. printf("Error: Can not enable MEM access or Bus Mastering.\n");
  570. debug("PCI command: %04x\n", word);
  571. return 1;
  572. }
  573. /* GPIO off */
  574. writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
  575. /* clear global reset & mask interrupts during initialization */
  576. writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
  577. init_start:
  578. return sil_init_sata(dev);
  579. }
  580. int reset_sata(int dev)
  581. {
  582. return 0;
  583. }
  584. /*
  585. * SATA interface between low level driver and command layer
  586. */
  587. int scan_sata(int dev)
  588. {
  589. struct sil_sata *sata = (struct sil_sata *)sata_dev_desc[dev].priv;
  590. #else
  591. static int scan_sata(struct udevice *blk_dev, int dev)
  592. {
  593. struct blk_desc *desc = dev_get_uclass_plat(blk_dev);
  594. struct sil_sata_priv *priv = dev_get_plat(blk_dev);
  595. struct sil_sata *sata = priv->sil_sata_desc[dev];
  596. #endif
  597. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  598. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  599. unsigned char product[ATA_ID_PROD_LEN + 1];
  600. u16 *id;
  601. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  602. if (!id) {
  603. printf("Id malloc failed\n");
  604. return 1;
  605. }
  606. sil_cmd_identify_device(sata, id);
  607. sil_sata_set_feature_by_id(sata, id);
  608. /* Serial number */
  609. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  610. /* Firmware version */
  611. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  612. /* Product model */
  613. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  614. #if !CONFIG_IS_ENABLED(BLK)
  615. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  616. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  617. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  618. /* Totoal sectors */
  619. sata_dev_desc[dev].lba = ata_id_n_sectors(id);
  620. #ifdef CONFIG_LBA48
  621. sata_dev_desc[dev].lba48 = sata->lba48;
  622. #endif
  623. #else
  624. memcpy(desc->product, serial, sizeof(serial));
  625. memcpy(desc->revision, firmware, sizeof(firmware));
  626. memcpy(desc->vendor, product, sizeof(product));
  627. desc->lba = ata_id_n_sectors(id);
  628. #ifdef CONFIG_LBA48
  629. desc->lba48 = sata->lba48;
  630. #endif
  631. #endif
  632. #ifdef DEBUG
  633. ata_dump_id(id);
  634. #endif
  635. free((void *)id);
  636. return 0;
  637. }
  638. #if CONFIG_IS_ENABLED(BLK)
  639. static const struct blk_ops sata_sil_blk_ops = {
  640. .read = sata_read,
  641. .write = sata_write,
  642. };
  643. U_BOOT_DRIVER(sata_sil_driver) = {
  644. .name = "sata_sil_blk",
  645. .id = UCLASS_BLK,
  646. .ops = &sata_sil_blk_ops,
  647. .plat_auto = sizeof(struct sil_sata_priv),
  648. };
  649. static int sil_unbind_device(struct udevice *dev)
  650. {
  651. int ret;
  652. ret = device_remove(dev, DM_REMOVE_NORMAL);
  653. if (ret)
  654. return ret;
  655. ret = device_unbind(dev);
  656. if (ret)
  657. return ret;
  658. return 0;
  659. }
  660. static int sil_pci_probe(struct udevice *dev)
  661. {
  662. struct udevice *blk;
  663. int failed_number;
  664. char sata_name[10];
  665. pci_dev_t devno;
  666. u16 word;
  667. int ret;
  668. int i;
  669. failed_number = 0;
  670. /* Get PCI device number */
  671. devno = dm_pci_get_bdf(dev);
  672. if (devno == -1)
  673. return 1;
  674. dm_pci_read_config16(dev, PCI_DEVICE_ID, &word);
  675. /* get the port count */
  676. word &= 0xf;
  677. sata_info.portbase = 0;
  678. sata_info.maxport = sata_info.portbase + word;
  679. sata_info.devno = devno;
  680. /* Read out all BARs */
  681. sata_info.iobase[0] = (ulong)dm_pci_map_bar(dev,
  682. PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
  683. sata_info.iobase[1] = (ulong)dm_pci_map_bar(dev,
  684. PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
  685. /* mask out the unused bits */
  686. sata_info.iobase[0] &= 0xffffff80;
  687. sata_info.iobase[1] &= 0xfffffc00;
  688. /* Enable Bus Mastering and memory region */
  689. dm_pci_write_config16(dev, PCI_COMMAND,
  690. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  691. /* Check if mem accesses and Bus Mastering are enabled. */
  692. dm_pci_read_config16(dev, PCI_COMMAND, &word);
  693. if (!(word & PCI_COMMAND_MEMORY) ||
  694. (!(word & PCI_COMMAND_MASTER))) {
  695. printf("Error: Can not enable MEM access or Bus Mastering.\n");
  696. debug("PCI command: %04x\n", word);
  697. return 1;
  698. }
  699. /* GPIO off */
  700. writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
  701. /* clear global reset & mask interrupts during initialization */
  702. writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
  703. for (i = sata_info.portbase; i < sata_info.maxport; i++) {
  704. snprintf(sata_name, sizeof(sata_name), "sil_sata%d", i);
  705. ret = blk_create_devicef(dev, "sata_sil_blk", sata_name,
  706. IF_TYPE_SATA, -1, 512, 0, &blk);
  707. if (ret) {
  708. debug("Can't create device\n");
  709. return ret;
  710. }
  711. ret = sil_init_sata(blk, i);
  712. if (ret) {
  713. ret = sil_unbind_device(blk);
  714. if (ret)
  715. return ret;
  716. failed_number++;
  717. continue;
  718. }
  719. ret = scan_sata(blk, i);
  720. if (ret) {
  721. ret = sil_unbind_device(blk);
  722. if (ret)
  723. return ret;
  724. failed_number++;
  725. continue;
  726. }
  727. }
  728. if (failed_number == sata_info.maxport)
  729. return -ENODEV;
  730. else
  731. return 0;
  732. }
  733. static int sil_pci_remove(struct udevice *dev)
  734. {
  735. int i;
  736. struct sil_sata *sata;
  737. struct sil_sata_priv *priv;
  738. priv = dev_get_priv(dev);
  739. for (i = sata_info.portbase; i < sata_info.maxport; i++) {
  740. sata = priv->sil_sata_desc[i];
  741. if (sata)
  742. free(sata);
  743. }
  744. return 0;
  745. }
  746. static int sata_sil_scan(struct udevice *dev)
  747. {
  748. /* Nothing to do here */
  749. return 0;
  750. }
  751. struct sil_ops sata_sil_ops = {
  752. .scan = sata_sil_scan,
  753. };
  754. static const struct udevice_id sil_pci_ids[] = {
  755. { .compatible = "sil-pci-sample" },
  756. { }
  757. };
  758. U_BOOT_DRIVER(sil_ahci_pci) = {
  759. .name = "sil_ahci_pci",
  760. .id = UCLASS_AHCI,
  761. .of_match = sil_pci_ids,
  762. .ops = &sata_sil_ops,
  763. .probe = sil_pci_probe,
  764. .remove = sil_pci_remove,
  765. .priv_auto = sizeof(struct sil_sata_priv),
  766. };
  767. U_BOOT_PCI_DEVICE(sil_ahci_pci, supported);
  768. #endif