sata_mv.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, 2010.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
  7. */
  8. /*
  9. * This driver supports the SATA controller of some Mavell SoC's.
  10. * Here a (most likely incomplete) list of the supported SoC's:
  11. * - Kirkwood
  12. * - Armada 370
  13. * - Armada XP
  14. *
  15. * This driver implementation is an alternative to the already available
  16. * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
  17. * But this driver only supports PIO mode and as this new driver also
  18. * supports transfer via DMA, its much faster.
  19. *
  20. * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
  21. * by this driver. As they have an AHCI compatible SATA controller
  22. * integrated.
  23. */
  24. /*
  25. * TODO:
  26. * Better error recovery
  27. * No support for using PRDs (Thus max 64KB transfers)
  28. * No NCQ support
  29. * No port multiplier support
  30. */
  31. #include <common.h>
  32. #include <ahci.h>
  33. #include <blk.h>
  34. #include <cpu_func.h>
  35. #include <dm.h>
  36. #include <log.h>
  37. #include <asm/cache.h>
  38. #include <asm/global_data.h>
  39. #include <dm/device-internal.h>
  40. #include <dm/lists.h>
  41. #include <fis.h>
  42. #include <libata.h>
  43. #include <malloc.h>
  44. #include <sata.h>
  45. #include <linux/bitops.h>
  46. #include <linux/delay.h>
  47. #include <linux/errno.h>
  48. #include <asm/io.h>
  49. #include <linux/mbus.h>
  50. #include <asm/arch/soc.h>
  51. #if defined(CONFIG_ARCH_KIRKWOOD)
  52. #define SATAHC_BASE KW_SATA_BASE
  53. #else
  54. #define SATAHC_BASE MVEBU_AXP_SATA_BASE
  55. #endif
  56. #define SATA0_BASE (SATAHC_BASE + 0x2000)
  57. #define SATA1_BASE (SATAHC_BASE + 0x4000)
  58. /* EDMA registers */
  59. #define EDMA_CFG 0x000
  60. #define EDMA_CFG_NCQ (1 << 5)
  61. #define EDMA_CFG_EQUE (1 << 9)
  62. #define EDMA_TIMER 0x004
  63. #define EDMA_IECR 0x008
  64. #define EDMA_IEMR 0x00c
  65. #define EDMA_RQBA_HI 0x010
  66. #define EDMA_RQIPR 0x014
  67. #define EDMA_RQIPR_IPMASK (0x1f << 5)
  68. #define EDMA_RQIPR_IPSHIFT 5
  69. #define EDMA_RQOPR 0x018
  70. #define EDMA_RQOPR_OPMASK (0x1f << 5)
  71. #define EDMA_RQOPR_OPSHIFT 5
  72. #define EDMA_RSBA_HI 0x01c
  73. #define EDMA_RSIPR 0x020
  74. #define EDMA_RSIPR_IPMASK (0x1f << 3)
  75. #define EDMA_RSIPR_IPSHIFT 3
  76. #define EDMA_RSOPR 0x024
  77. #define EDMA_RSOPR_OPMASK (0x1f << 3)
  78. #define EDMA_RSOPR_OPSHIFT 3
  79. #define EDMA_CMD 0x028
  80. #define EDMA_CMD_ENEDMA (0x01 << 0)
  81. #define EDMA_CMD_DISEDMA (0x01 << 1)
  82. #define EDMA_CMD_ATARST (0x01 << 2)
  83. #define EDMA_CMD_FREEZE (0x01 << 4)
  84. #define EDMA_TEST_CTL 0x02c
  85. #define EDMA_STATUS 0x030
  86. #define EDMA_IORTO 0x034
  87. #define EDMA_CDTR 0x040
  88. #define EDMA_HLTCND 0x060
  89. #define EDMA_NTSR 0x094
  90. /* Basic DMA registers */
  91. #define BDMA_CMD 0x224
  92. #define BDMA_STATUS 0x228
  93. #define BDMA_DTLB 0x22c
  94. #define BDMA_DTHB 0x230
  95. #define BDMA_DRL 0x234
  96. #define BDMA_DRH 0x238
  97. /* SATA Interface registers */
  98. #define SIR_ICFG 0x050
  99. #define SIR_CFG_GEN2EN (0x1 << 7)
  100. #define SIR_PLL_CFG 0x054
  101. #define SIR_SSTATUS 0x300
  102. #define SSTATUS_DET_MASK (0x0f << 0)
  103. #define SIR_SERROR 0x304
  104. #define SIR_SCONTROL 0x308
  105. #define SIR_SCONTROL_DETEN (0x01 << 0)
  106. #define SIR_LTMODE 0x30c
  107. #define SIR_LTMODE_NELBE (0x01 << 7)
  108. #define SIR_PHYMODE3 0x310
  109. #define SIR_PHYMODE4 0x314
  110. #define SIR_PHYMODE1 0x32c
  111. #define SIR_PHYMODE2 0x330
  112. #define SIR_BIST_CTRL 0x334
  113. #define SIR_BIST_DW1 0x338
  114. #define SIR_BIST_DW2 0x33c
  115. #define SIR_SERR_IRQ_MASK 0x340
  116. #define SIR_SATA_IFCTRL 0x344
  117. #define SIR_SATA_TESTCTRL 0x348
  118. #define SIR_SATA_IFSTATUS 0x34c
  119. #define SIR_VEND_UNIQ 0x35c
  120. #define SIR_FIS_CFG 0x360
  121. #define SIR_FIS_IRQ_CAUSE 0x364
  122. #define SIR_FIS_IRQ_MASK 0x368
  123. #define SIR_FIS_DWORD0 0x370
  124. #define SIR_FIS_DWORD1 0x374
  125. #define SIR_FIS_DWORD2 0x378
  126. #define SIR_FIS_DWORD3 0x37c
  127. #define SIR_FIS_DWORD4 0x380
  128. #define SIR_FIS_DWORD5 0x384
  129. #define SIR_FIS_DWORD6 0x388
  130. #define SIR_PHYM9_GEN2 0x398
  131. #define SIR_PHYM9_GEN1 0x39c
  132. #define SIR_PHY_CFG 0x3a0
  133. #define SIR_PHYCTL 0x3a4
  134. #define SIR_PHYM10 0x3a8
  135. #define SIR_PHYM12 0x3b0
  136. /* Shadow registers */
  137. #define PIO_DATA 0x100
  138. #define PIO_ERR_FEATURES 0x104
  139. #define PIO_SECTOR_COUNT 0x108
  140. #define PIO_LBA_LOW 0x10c
  141. #define PIO_LBA_MID 0x110
  142. #define PIO_LBA_HI 0x114
  143. #define PIO_DEVICE 0x118
  144. #define PIO_CMD_STATUS 0x11c
  145. #define PIO_STATUS_ERR (0x01 << 0)
  146. #define PIO_STATUS_DRQ (0x01 << 3)
  147. #define PIO_STATUS_DF (0x01 << 5)
  148. #define PIO_STATUS_DRDY (0x01 << 6)
  149. #define PIO_STATUS_BSY (0x01 << 7)
  150. #define PIO_CTRL_ALTSTAT 0x120
  151. /* SATAHC arbiter registers */
  152. #define SATAHC_CFG 0x000
  153. #define SATAHC_RQOP 0x004
  154. #define SATAHC_RQIP 0x008
  155. #define SATAHC_ICT 0x00c
  156. #define SATAHC_ITT 0x010
  157. #define SATAHC_ICR 0x014
  158. #define SATAHC_ICR_PORT0 (0x01 << 0)
  159. #define SATAHC_ICR_PORT1 (0x01 << 1)
  160. #define SATAHC_MIC 0x020
  161. #define SATAHC_MIM 0x024
  162. #define SATAHC_LED_CFG 0x02c
  163. #define REQUEST_QUEUE_SIZE 32
  164. #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
  165. struct crqb {
  166. u32 dtb_low; /* DW0 */
  167. u32 dtb_high; /* DW1 */
  168. u32 control_flags; /* DW2 */
  169. u32 drb_count; /* DW3 */
  170. u32 ata_cmd_feat; /* DW4 */
  171. u32 ata_addr; /* DW5 */
  172. u32 ata_addr_exp; /* DW6 */
  173. u32 ata_sect_count; /* DW7 */
  174. };
  175. #define CRQB_ALIGN 0x400
  176. #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
  177. #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
  178. #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
  179. #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
  180. #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
  181. #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
  182. #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
  183. #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
  184. #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
  185. #define CRQB_CMDFEAT_CMDSHIFT 16
  186. #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
  187. #define CRQB_CMDFEAT_FEATSHIFT 24
  188. #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
  189. #define CRQB_ADDR_LBA_LOWSHIFT 0
  190. #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
  191. #define CRQB_ADDR_LBA_MIDSHIFT 8
  192. #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
  193. #define CRQB_ADDR_LBA_HIGHSHIFT 16
  194. #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
  195. #define CRQB_ADDR_DEVICE_SHIFT 24
  196. #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
  197. #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
  198. #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
  199. #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
  200. #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
  201. #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
  202. #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
  203. #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
  204. #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
  205. #define CRQB_SECTCOUNT_COUNT_SHIFT 0
  206. #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
  207. #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
  208. #define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
  209. #define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
  210. struct eprd {
  211. u32 phyaddr_low;
  212. u32 bytecount_eot;
  213. u32 phyaddr_hi;
  214. u32 reserved;
  215. };
  216. #define EPRD_PHYADDR_MASK 0xfffffffe
  217. #define EPRD_BYTECOUNT_MASK 0x0000ffff
  218. #define EPRD_EOT (0x01 << 31)
  219. struct crpb {
  220. u32 id;
  221. u32 flags;
  222. u32 timestamp;
  223. };
  224. #define CRPB_ALIGN 0x100
  225. #define READ_CMD 0
  226. #define WRITE_CMD 1
  227. /*
  228. * Since we don't use PRDs yet max transfer size
  229. * is 64KB
  230. */
  231. #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
  232. /* Keep track if hw is initialized or not */
  233. static u32 hw_init;
  234. struct mv_priv {
  235. char name[12];
  236. u32 link;
  237. u32 regbase;
  238. u32 queue_depth;
  239. u16 pio;
  240. u16 mwdma;
  241. u16 udma;
  242. int dev_nr;
  243. void *crqb_alloc;
  244. struct crqb *request;
  245. void *crpb_alloc;
  246. struct crpb *response;
  247. };
  248. static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
  249. {
  250. ulong start;
  251. start = get_timer(0);
  252. do {
  253. if ((in_le32(addr) & mask) == val)
  254. return 0;
  255. } while (get_timer(start) < timeout_msec);
  256. return -ETIMEDOUT;
  257. }
  258. /* Cut from sata_mv in linux kernel */
  259. static int mv_stop_edma_engine(struct udevice *dev, int port)
  260. {
  261. struct mv_priv *priv = dev_get_plat(dev);
  262. int i;
  263. /* Disable eDMA. The disable bit auto clears. */
  264. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
  265. /* Wait for the chip to confirm eDMA is off. */
  266. for (i = 10000; i > 0; i--) {
  267. u32 reg = in_le32(priv->regbase + EDMA_CMD);
  268. if (!(reg & EDMA_CMD_ENEDMA)) {
  269. debug("EDMA stop on port %d succesful\n", port);
  270. return 0;
  271. }
  272. udelay(10);
  273. }
  274. debug("EDMA stop on port %d failed\n", port);
  275. return -1;
  276. }
  277. static int mv_start_edma_engine(struct udevice *dev, int port)
  278. {
  279. struct mv_priv *priv = dev_get_plat(dev);
  280. u32 tmp;
  281. /* Check preconditions */
  282. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  283. if ((tmp & SSTATUS_DET_MASK) != 0x03) {
  284. printf("Device error on port: %d\n", port);
  285. return -1;
  286. }
  287. tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
  288. if (tmp & (ATA_BUSY | ATA_DRQ)) {
  289. printf("Device not ready on port: %d\n", port);
  290. return -1;
  291. }
  292. /* Clear interrupt cause */
  293. out_le32(priv->regbase + EDMA_IECR, 0x0);
  294. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  295. tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
  296. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  297. /* Configure edma operation */
  298. tmp = in_le32(priv->regbase + EDMA_CFG);
  299. tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
  300. tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
  301. out_le32(priv->regbase + EDMA_CFG, tmp);
  302. out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
  303. /* Configure fis, set all to no-wait for now */
  304. out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
  305. /* Setup request queue */
  306. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  307. out_le32(priv->regbase + EDMA_RQIPR, priv->request);
  308. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  309. /* Setup response queue */
  310. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  311. out_le32(priv->regbase + EDMA_RSOPR, priv->response);
  312. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  313. /* Start edma */
  314. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
  315. return 0;
  316. }
  317. static int mv_reset_channel(struct udevice *dev, int port)
  318. {
  319. struct mv_priv *priv = dev_get_plat(dev);
  320. /* Make sure edma is stopped */
  321. mv_stop_edma_engine(dev, port);
  322. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
  323. udelay(25); /* allow reset propagation */
  324. out_le32(priv->regbase + EDMA_CMD, 0);
  325. mdelay(10);
  326. return 0;
  327. }
  328. static void mv_reset_port(struct udevice *dev, int port)
  329. {
  330. struct mv_priv *priv = dev_get_plat(dev);
  331. mv_reset_channel(dev, port);
  332. out_le32(priv->regbase + EDMA_CMD, 0x0);
  333. out_le32(priv->regbase + EDMA_CFG, 0x101f);
  334. out_le32(priv->regbase + EDMA_IECR, 0x0);
  335. out_le32(priv->regbase + EDMA_IEMR, 0x0);
  336. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  337. out_le32(priv->regbase + EDMA_RQIPR, 0x0);
  338. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  339. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  340. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  341. out_le32(priv->regbase + EDMA_RSOPR, 0x0);
  342. out_le32(priv->regbase + EDMA_IORTO, 0xfa);
  343. }
  344. static void mv_reset_one_hc(void)
  345. {
  346. out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
  347. out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
  348. out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
  349. }
  350. static int probe_port(struct udevice *dev, int port)
  351. {
  352. struct mv_priv *priv = dev_get_plat(dev);
  353. int tries, tries2, set15 = 0;
  354. u32 tmp;
  355. debug("Probe port: %d\n", port);
  356. for (tries = 0; tries < 2; tries++) {
  357. /* Clear SError */
  358. out_le32(priv->regbase + SIR_SERROR, 0x0);
  359. /* trigger com-init */
  360. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  361. tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
  362. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  363. mdelay(1);
  364. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  365. tries2 = 5;
  366. do {
  367. tmp = (tmp & 0x0f0) | 0x300;
  368. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  369. mdelay(10);
  370. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  371. } while ((tmp & 0xf0f) != 0x300 && tries2--);
  372. mdelay(10);
  373. for (tries2 = 0; tries2 < 200; tries2++) {
  374. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  375. if ((tmp & SSTATUS_DET_MASK) == 0x03) {
  376. debug("Found device on port\n");
  377. return 0;
  378. }
  379. mdelay(1);
  380. }
  381. if ((tmp & SSTATUS_DET_MASK) == 0) {
  382. debug("No device attached on port %d\n", port);
  383. return -ENODEV;
  384. }
  385. if (!set15) {
  386. /* Try on 1.5Gb/S */
  387. debug("Try 1.5Gb link\n");
  388. set15 = 1;
  389. out_le32(priv->regbase + SIR_SCONTROL, 0x304);
  390. tmp = in_le32(priv->regbase + SIR_ICFG);
  391. tmp &= ~SIR_CFG_GEN2EN;
  392. out_le32(priv->regbase + SIR_ICFG, tmp);
  393. mv_reset_channel(dev, port);
  394. }
  395. }
  396. debug("Failed to probe port\n");
  397. return -1;
  398. }
  399. /* Get request queue in pointer */
  400. static int get_reqip(struct udevice *dev, int port)
  401. {
  402. struct mv_priv *priv = dev_get_plat(dev);
  403. u32 tmp;
  404. tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
  405. tmp = tmp >> EDMA_RQIPR_IPSHIFT;
  406. return tmp;
  407. }
  408. static void set_reqip(struct udevice *dev, int port, int reqin)
  409. {
  410. struct mv_priv *priv = dev_get_plat(dev);
  411. u32 tmp;
  412. tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
  413. tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
  414. out_le32(priv->regbase + EDMA_RQIPR, tmp);
  415. }
  416. /* Get next available slot, ignoring possible overwrite */
  417. static int get_next_reqip(struct udevice *dev, int port)
  418. {
  419. int slot = get_reqip(dev, port);
  420. slot = (slot + 1) % REQUEST_QUEUE_SIZE;
  421. return slot;
  422. }
  423. /* Get response queue in pointer */
  424. static int get_rspip(struct udevice *dev, int port)
  425. {
  426. struct mv_priv *priv = dev_get_plat(dev);
  427. u32 tmp;
  428. tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
  429. tmp = tmp >> EDMA_RSIPR_IPSHIFT;
  430. return tmp;
  431. }
  432. /* Get response queue out pointer */
  433. static int get_rspop(struct udevice *dev, int port)
  434. {
  435. struct mv_priv *priv = dev_get_plat(dev);
  436. u32 tmp;
  437. tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
  438. tmp = tmp >> EDMA_RSOPR_OPSHIFT;
  439. return tmp;
  440. }
  441. /* Get next response queue pointer */
  442. static int get_next_rspop(struct udevice *dev, int port)
  443. {
  444. return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
  445. }
  446. /* Set response queue pointer */
  447. static void set_rspop(struct udevice *dev, int port, int reqin)
  448. {
  449. struct mv_priv *priv = dev_get_plat(dev);
  450. u32 tmp;
  451. tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
  452. tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
  453. out_le32(priv->regbase + EDMA_RSOPR, tmp);
  454. }
  455. static int wait_dma_completion(struct udevice *dev, int port, int index,
  456. u32 timeout_msec)
  457. {
  458. u32 tmp, res;
  459. tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
  460. res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
  461. tmp, timeout_msec);
  462. if (res)
  463. printf("Failed to wait for completion on port %d\n", port);
  464. return res;
  465. }
  466. static void process_responses(struct udevice *dev, int port)
  467. {
  468. #ifdef DEBUG
  469. struct mv_priv *priv = dev_get_plat(dev);
  470. #endif
  471. u32 tmp;
  472. u32 outind = get_rspop(dev, port);
  473. /* Ack interrupts */
  474. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  475. if (port == 0)
  476. tmp &= ~(BIT(0) | BIT(8));
  477. else
  478. tmp &= ~(BIT(1) | BIT(9));
  479. tmp &= ~(BIT(4));
  480. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  481. while (get_rspip(dev, port) != outind) {
  482. #ifdef DEBUG
  483. debug("Response index %d flags %08x on port %d\n", outind,
  484. priv->response[outind].flags, port);
  485. #endif
  486. outind = get_next_rspop(dev, port);
  487. set_rspop(dev, port, outind);
  488. }
  489. }
  490. static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
  491. struct sata_fis_h2d *cfis,
  492. u8 *buffer, u32 len, u32 iswrite)
  493. {
  494. struct mv_priv *priv = dev_get_plat(dev);
  495. struct crqb *req;
  496. int slot;
  497. u32 start;
  498. if (len >= 64 * 1024) {
  499. printf("We only support <64K transfers for now\n");
  500. return -1;
  501. }
  502. /* Initialize request */
  503. slot = get_reqip(dev, port);
  504. memset(&priv->request[slot], 0, sizeof(struct crqb));
  505. req = &priv->request[slot];
  506. req->dtb_low = (u32)buffer;
  507. /* Dont use PRDs */
  508. req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
  509. req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
  510. req->control_flags |=
  511. ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
  512. & CRQB_CNTRLFLAGS_PMPORTMASK);
  513. req->drb_count = len;
  514. req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
  515. CRQB_CMDFEAT_CMDMASK;
  516. req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
  517. CRQB_CMDFEAT_FEATMASK;
  518. req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
  519. CRQB_ADDR_LBA_LOWMASK;
  520. req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
  521. CRQB_ADDR_LBA_MIDMASK;
  522. req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
  523. CRQB_ADDR_LBA_HIGHMASK;
  524. req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
  525. CRQB_ADDR_DEVICE_MASK;
  526. req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
  527. CRQB_ADDR_LBA_LOW_EXP_MASK;
  528. req->ata_addr_exp |=
  529. (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
  530. CRQB_ADDR_LBA_MID_EXP_MASK;
  531. req->ata_addr_exp |=
  532. (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
  533. CRQB_ADDR_LBA_HIGH_EXP_MASK;
  534. req->ata_addr_exp |=
  535. (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
  536. CRQB_ADDR_FEATURE_EXP_MASK;
  537. req->ata_sect_count =
  538. (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
  539. CRQB_SECTCOUNT_COUNT_MASK;
  540. req->ata_sect_count |=
  541. (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
  542. CRQB_SECTCOUNT_COUNT_EXP_MASK;
  543. /* Flush data */
  544. start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
  545. flush_dcache_range(start,
  546. start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
  547. /* Trigger operation */
  548. slot = get_next_reqip(dev, port);
  549. set_reqip(dev, port, slot);
  550. /* Wait for completion */
  551. if (wait_dma_completion(dev, port, slot, 10000)) {
  552. printf("ATA operation timed out\n");
  553. return -1;
  554. }
  555. process_responses(dev, port);
  556. /* Invalidate data on read */
  557. if (buffer && len) {
  558. start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
  559. invalidate_dcache_range(start,
  560. start + ALIGN(len, ARCH_DMA_MINALIGN));
  561. }
  562. return len;
  563. }
  564. static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
  565. u32 blkcnt,
  566. u8 *buffer, int is_write)
  567. {
  568. struct sata_fis_h2d cfis;
  569. u32 res;
  570. u64 block;
  571. block = (u64)start;
  572. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  573. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  574. cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  575. cfis.lba_high_exp = (block >> 40) & 0xff;
  576. cfis.lba_mid_exp = (block >> 32) & 0xff;
  577. cfis.lba_low_exp = (block >> 24) & 0xff;
  578. cfis.lba_high = (block >> 16) & 0xff;
  579. cfis.lba_mid = (block >> 8) & 0xff;
  580. cfis.lba_low = block & 0xff;
  581. cfis.device = ATA_LBA;
  582. cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
  583. cfis.sector_count = blkcnt & 0xff;
  584. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  585. ATA_SECT_SIZE * blkcnt, is_write);
  586. return res >= 0 ? blkcnt : res;
  587. }
  588. static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
  589. u32 blkcnt, u8 *buffer, int is_write)
  590. {
  591. struct sata_fis_h2d cfis;
  592. lbaint_t block;
  593. u32 res;
  594. block = start;
  595. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  596. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  597. cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  598. cfis.device = ATA_LBA;
  599. cfis.device |= (block >> 24) & 0xf;
  600. cfis.lba_high = (block >> 16) & 0xff;
  601. cfis.lba_mid = (block >> 8) & 0xff;
  602. cfis.lba_low = block & 0xff;
  603. cfis.sector_count = (u8)(blkcnt & 0xff);
  604. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  605. ATA_SECT_SIZE * blkcnt, is_write);
  606. return res >= 0 ? blkcnt : res;
  607. }
  608. static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
  609. lbaint_t blkcnt, void *buffer, int is_write)
  610. {
  611. struct blk_desc *desc = dev_get_uclass_plat(dev);
  612. lbaint_t start, blks;
  613. u8 *addr;
  614. int max_blks;
  615. debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
  616. start = blknr;
  617. blks = blkcnt;
  618. addr = (u8 *)buffer;
  619. max_blks = MV_ATA_MAX_SECTORS;
  620. do {
  621. if (blks > max_blks) {
  622. if (desc->lba48) {
  623. mv_sata_rw_cmd_ext(dev, port, start, max_blks,
  624. addr, is_write);
  625. } else {
  626. mv_sata_rw_cmd(dev, port, start, max_blks,
  627. addr, is_write);
  628. }
  629. start += max_blks;
  630. blks -= max_blks;
  631. addr += ATA_SECT_SIZE * max_blks;
  632. } else {
  633. if (desc->lba48) {
  634. mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
  635. is_write);
  636. } else {
  637. mv_sata_rw_cmd(dev, port, start, blks, addr,
  638. is_write);
  639. }
  640. start += blks;
  641. blks = 0;
  642. addr += ATA_SECT_SIZE * blks;
  643. }
  644. } while (blks != 0);
  645. return blkcnt;
  646. }
  647. static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
  648. struct sata_fis_h2d *cfis, u8 *buffer,
  649. u32 len, u32 iswrite)
  650. {
  651. struct mv_priv *priv = dev_get_plat(dev);
  652. int i;
  653. u16 *tp;
  654. debug("%s\n", __func__);
  655. out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
  656. out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
  657. out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
  658. out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
  659. out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
  660. out_le32(priv->regbase + PIO_DEVICE, cfis->device);
  661. out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
  662. if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
  663. ATA_BUSY, 0x0, 10000)) {
  664. debug("Failed to wait for completion\n");
  665. return -1;
  666. }
  667. if (len > 0) {
  668. tp = (u16 *)buffer;
  669. for (i = 0; i < len / 2; i++) {
  670. if (iswrite)
  671. out_le16(priv->regbase + PIO_DATA, *tp++);
  672. else
  673. *tp++ = in_le16(priv->regbase + PIO_DATA);
  674. }
  675. }
  676. return len;
  677. }
  678. static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
  679. {
  680. struct sata_fis_h2d h2d;
  681. int len;
  682. memset(&h2d, 0, sizeof(struct sata_fis_h2d));
  683. h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  684. h2d.command = ATA_CMD_ID_ATA;
  685. /* Give device time to get operational */
  686. mdelay(10);
  687. /* During cold start, with some HDDs, the first ATA ID command does
  688. * not populate the ID words. In fact, the first ATA ID
  689. * command will only power up the drive, and then the ATA ID command
  690. * processing is lost in the process.
  691. */
  692. len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
  693. ATA_ID_WORDS * 2, READ_CMD);
  694. /* If drive capacity has been filled in, then it was successfully
  695. * identified (the drive has been powered up before, i.e.
  696. * this function is invoked during a reboot)
  697. */
  698. if (ata_id_n_sectors(id) != 0)
  699. return len;
  700. /* Issue the 2nd ATA ID command to make sure the ID words are
  701. * populated properly.
  702. */
  703. mdelay(10);
  704. len = mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
  705. ATA_ID_WORDS * 2, READ_CMD);
  706. if (ata_id_n_sectors(id) != 0)
  707. return len;
  708. printf("Err: Failed to identify SATA device %d\n", port);
  709. return -ENODEV;
  710. }
  711. static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
  712. {
  713. struct mv_priv *priv = dev_get_plat(dev);
  714. priv->pio = id[ATA_ID_PIO_MODES];
  715. priv->mwdma = id[ATA_ID_MWDMA_MODES];
  716. priv->udma = id[ATA_ID_UDMA_MODES];
  717. debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
  718. priv->udma);
  719. }
  720. static void mv_sata_set_features(struct udevice *dev, int port)
  721. {
  722. struct mv_priv *priv = dev_get_plat(dev);
  723. struct sata_fis_h2d cfis;
  724. u8 udma_cap;
  725. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  726. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  727. cfis.command = ATA_CMD_SET_FEATURES;
  728. cfis.features = SETFEATURES_XFER;
  729. /* First check the device capablity */
  730. udma_cap = (u8) (priv->udma & 0xff);
  731. if (udma_cap == ATA_UDMA6)
  732. cfis.sector_count = XFER_UDMA_6;
  733. if (udma_cap == ATA_UDMA5)
  734. cfis.sector_count = XFER_UDMA_5;
  735. if (udma_cap == ATA_UDMA4)
  736. cfis.sector_count = XFER_UDMA_4;
  737. if (udma_cap == ATA_UDMA3)
  738. cfis.sector_count = XFER_UDMA_3;
  739. mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
  740. }
  741. /*
  742. * Initialize SATA memory windows
  743. */
  744. static void mvsata_ide_conf_mbus_windows(void)
  745. {
  746. const struct mbus_dram_target_info *dram;
  747. int i;
  748. dram = mvebu_mbus_dram_info();
  749. /* Disable windows, Set Size/Base to 0 */
  750. for (i = 0; i < 4; i++) {
  751. writel(0, MVSATA_WIN_CONTROL(i));
  752. writel(0, MVSATA_WIN_BASE(i));
  753. }
  754. for (i = 0; i < dram->num_cs; i++) {
  755. const struct mbus_dram_window *cs = dram->cs + i;
  756. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  757. (dram->mbus_dram_target_id << 4) | 1,
  758. MVSATA_WIN_CONTROL(i));
  759. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  760. }
  761. }
  762. static int sata_mv_init_sata(struct udevice *dev, int port)
  763. {
  764. struct mv_priv *priv = dev_get_plat(dev);
  765. debug("Initialize sata dev: %d\n", port);
  766. if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
  767. printf("Invalid sata device %d\n", port);
  768. return -1;
  769. }
  770. /* Allocate and align request buffer */
  771. priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
  772. CRQB_ALIGN);
  773. if (!priv->crqb_alloc) {
  774. printf("Unable to allocate memory for request queue\n");
  775. return -ENOMEM;
  776. }
  777. memset(priv->crqb_alloc, 0,
  778. sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
  779. priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
  780. ~(CRQB_ALIGN - 1));
  781. /* Allocate and align response buffer */
  782. priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
  783. CRPB_ALIGN);
  784. if (!priv->crpb_alloc) {
  785. printf("Unable to allocate memory for response queue\n");
  786. return -ENOMEM;
  787. }
  788. memset(priv->crpb_alloc, 0,
  789. sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
  790. priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
  791. ~(CRPB_ALIGN - 1));
  792. sprintf(priv->name, "SATA%d", port);
  793. priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
  794. if (!hw_init) {
  795. debug("Initialize sata hw\n");
  796. hw_init = 1;
  797. mv_reset_one_hc();
  798. mvsata_ide_conf_mbus_windows();
  799. }
  800. mv_reset_port(dev, port);
  801. if (probe_port(dev, port)) {
  802. priv->link = 0;
  803. return -ENODEV;
  804. }
  805. priv->link = 1;
  806. return 0;
  807. }
  808. static int sata_mv_scan_sata(struct udevice *dev, int port)
  809. {
  810. struct blk_desc *desc = dev_get_uclass_plat(dev);
  811. struct mv_priv *priv = dev_get_plat(dev);
  812. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  813. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  814. unsigned char product[ATA_ID_PROD_LEN + 1];
  815. u64 n_sectors;
  816. u16 *id;
  817. if (!priv->link)
  818. return -ENODEV;
  819. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  820. if (!id) {
  821. printf("Failed to malloc id data\n");
  822. return -ENOMEM;
  823. }
  824. mv_sata_identify(dev, port, id);
  825. ata_swap_buf_le16(id, ATA_ID_WORDS);
  826. #ifdef DEBUG
  827. ata_dump_id(id);
  828. #endif
  829. /* Serial number */
  830. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  831. memcpy(desc->product, serial, sizeof(serial));
  832. /* Firmware version */
  833. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  834. memcpy(desc->revision, firmware, sizeof(firmware));
  835. /* Product model */
  836. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  837. memcpy(desc->vendor, product, sizeof(product));
  838. /* Total sectors */
  839. n_sectors = ata_id_n_sectors(id);
  840. desc->lba = n_sectors;
  841. /* Check if support LBA48 */
  842. if (ata_id_has_lba48(id)) {
  843. desc->lba48 = 1;
  844. debug("Device support LBA48\n");
  845. }
  846. /* Get the NCQ queue depth from device */
  847. priv->queue_depth = ata_id_queue_depth(id);
  848. /* Get the xfer mode from device */
  849. mv_sata_xfer_mode(dev, port, id);
  850. /* Set the xfer mode to highest speed */
  851. mv_sata_set_features(dev, port);
  852. /* Start up */
  853. mv_start_edma_engine(dev, port);
  854. return 0;
  855. }
  856. static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
  857. lbaint_t blkcnt, void *buffer)
  858. {
  859. struct mv_priv *priv = dev_get_plat(blk);
  860. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  861. buffer, READ_CMD);
  862. }
  863. static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
  864. lbaint_t blkcnt, const void *buffer)
  865. {
  866. struct mv_priv *priv = dev_get_plat(blk);
  867. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  868. (void *)buffer, WRITE_CMD);
  869. }
  870. static const struct blk_ops sata_mv_blk_ops = {
  871. .read = sata_mv_read,
  872. .write = sata_mv_write,
  873. };
  874. U_BOOT_DRIVER(sata_mv_driver) = {
  875. .name = "sata_mv_blk",
  876. .id = UCLASS_BLK,
  877. .ops = &sata_mv_blk_ops,
  878. .plat_auto = sizeof(struct mv_priv),
  879. };
  880. static int sata_mv_probe(struct udevice *dev)
  881. {
  882. const void *blob = gd->fdt_blob;
  883. int node = dev_of_offset(dev);
  884. struct mv_priv *priv;
  885. struct udevice *blk;
  886. int nr_ports;
  887. int ret;
  888. int i;
  889. int status = -ENODEV; /* If the probe fails to detected any SATA port */
  890. /* Get number of ports of this SATA controller */
  891. nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
  892. CONFIG_SYS_SATA_MAX_DEVICE);
  893. for (i = 0; i < nr_ports; i++) {
  894. ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
  895. IF_TYPE_SATA, -1, 512, 0, &blk);
  896. if (ret) {
  897. debug("Can't create device\n");
  898. continue;
  899. }
  900. priv = dev_get_plat(blk);
  901. priv->dev_nr = i;
  902. /* Init SATA port */
  903. ret = sata_mv_init_sata(blk, i);
  904. if (ret) {
  905. debug("%s: Failed to init bus\n", __func__);
  906. continue;
  907. }
  908. /* Scan SATA port */
  909. ret = sata_mv_scan_sata(blk, i);
  910. if (ret) {
  911. debug("%s: Failed to scan bus\n", __func__);
  912. continue;
  913. }
  914. /* If we got here, the current SATA port was probed
  915. * successfully, so set the probe status to successful.
  916. */
  917. status = 0;
  918. }
  919. return status;
  920. }
  921. static int sata_mv_scan(struct udevice *dev)
  922. {
  923. /* Nothing to do here */
  924. return 0;
  925. }
  926. static const struct udevice_id sata_mv_ids[] = {
  927. { .compatible = "marvell,armada-370-sata" },
  928. { .compatible = "marvell,orion-sata" },
  929. { }
  930. };
  931. struct ahci_ops sata_mv_ahci_ops = {
  932. .scan = sata_mv_scan,
  933. };
  934. U_BOOT_DRIVER(sata_mv_ahci) = {
  935. .name = "sata_mv_ahci",
  936. .id = UCLASS_AHCI,
  937. .of_match = sata_mv_ids,
  938. .ops = &sata_mv_ahci_ops,
  939. .probe = sata_mv_probe,
  940. };