fsl_sata.h 9.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2007-2008 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Dave Liu <daveliu@freescale.com>
  6. */
  7. #ifndef __FSL_SATA_H__
  8. #define __FSL_SATA_H__
  9. #define SATA_HC_MAX_NUM 4 /* Max host controller numbers */
  10. #define SATA_HC_MAX_CMD 16 /* Max command queue depth per host controller */
  11. #define SATA_HC_MAX_PORT 16 /* Max port number per host controller */
  12. /*
  13. * SATA Host Controller Registers
  14. */
  15. typedef struct fsl_sata_reg {
  16. /* SATA command registers */
  17. u32 cqr; /* Command queue register */
  18. u8 res1[0x4];
  19. u32 car; /* Command active register */
  20. u8 res2[0x4];
  21. u32 ccr; /* Command completed register */
  22. u8 res3[0x4];
  23. u32 cer; /* Command error register */
  24. u8 res4[0x4];
  25. u32 der; /* Device error register */
  26. u32 chba; /* Command header base address */
  27. u32 hstatus; /* Host status register */
  28. u32 hcontrol; /* Host control register */
  29. u32 cqpmp; /* Port number queue register */
  30. u32 sig; /* Signature register */
  31. u32 icc; /* Interrupt coalescing control register */
  32. u8 res5[0xc4];
  33. /* SATA supperset registers */
  34. u32 sstatus; /* SATA interface status register */
  35. u32 serror; /* SATA interface error register */
  36. u32 scontrol; /* SATA interface control register */
  37. u32 snotification; /* SATA interface notification register */
  38. u8 res6[0x30];
  39. /* SATA control status registers */
  40. u32 transcfg; /* Transport layer configuration */
  41. u32 transstatus; /* Transport layer status */
  42. u32 linkcfg; /* Link layer configuration */
  43. u32 linkcfg1; /* Link layer configuration1 */
  44. u32 linkcfg2; /* Link layer configuration2 */
  45. u32 linkstatus; /* Link layer status */
  46. u32 linkstatus1; /* Link layer status1 */
  47. u32 phyctrlcfg; /* PHY control configuration */
  48. u8 res7[0x2b0];
  49. /* SATA system control registers */
  50. u32 syspr; /* System priority register - big endian */
  51. u8 res8[0xbec];
  52. } __attribute__ ((packed)) fsl_sata_reg_t;
  53. /* HStatus register
  54. */
  55. #define HSTATUS_ONOFF 0x80000000 /* Online/offline status */
  56. #define HSTATUS_FORCE_OFFLINE 0x40000000 /* In process going offline */
  57. #define HSTATUS_BIST_ERR 0x20000000
  58. /* Fatal error */
  59. #define HSTATUS_MASTER_ERR 0x00004000
  60. #define HSTATUS_DATA_UNDERRUN 0x00002000
  61. #define HSTATUS_DATA_OVERRUN 0x00001000
  62. #define HSTATUS_CRC_ERR_TX 0x00000800
  63. #define HSTATUS_CRC_ERR_RX 0x00000400
  64. #define HSTATUS_FIFO_OVERFLOW_TX 0x00000200
  65. #define HSTATUS_FIFO_OVERFLOW_RX 0x00000100
  66. #define HSTATUS_FATAL_ERR_ALL (HSTATUS_MASTER_ERR | \
  67. HSTATUS_DATA_UNDERRUN | \
  68. HSTATUS_DATA_OVERRUN | \
  69. HSTATUS_CRC_ERR_TX | \
  70. HSTATUS_CRC_ERR_RX | \
  71. HSTATUS_FIFO_OVERFLOW_TX | \
  72. HSTATUS_FIFO_OVERFLOW_RX)
  73. /* Interrupt status */
  74. #define HSTATUS_FATAL_ERR 0x00000020
  75. #define HSTATUS_PHY_RDY 0x00000010
  76. #define HSTATUS_SIGNATURE 0x00000008
  77. #define HSTATUS_SNOTIFY 0x00000004
  78. #define HSTATUS_DEVICE_ERR 0x00000002
  79. #define HSTATUS_CMD_COMPLETE 0x00000001
  80. /* HControl register
  81. */
  82. #define HCONTROL_ONOFF 0x80000000 /* Online or offline request */
  83. #define HCONTROL_FORCE_OFFLINE 0x40000000 /* Force offline request */
  84. #define HCONTROL_ENTERPRISE_EN 0x10000000 /* Enterprise mode enabled */
  85. #define HCONTROL_HDR_SNOOP 0x00000400 /* Command header snoop */
  86. #define HCONTROL_PMP_ATTACHED 0x00000200 /* Port multiplier attached */
  87. /* Interrupt enable */
  88. #define HCONTROL_FATAL_ERR 0x00000020
  89. #define HCONTROL_PHY_RDY 0x00000010
  90. #define HCONTROL_SIGNATURE 0x00000008
  91. #define HCONTROL_SNOTIFY 0x00000004
  92. #define HCONTROL_DEVICE_ERR 0x00000002
  93. #define HCONTROL_CMD_COMPLETE 0x00000001
  94. #define HCONTROL_INT_EN_ALL (HCONTROL_FATAL_ERR | \
  95. HCONTROL_PHY_RDY | \
  96. HCONTROL_SIGNATURE | \
  97. HCONTROL_SNOTIFY | \
  98. HCONTROL_DEVICE_ERR | \
  99. HCONTROL_CMD_COMPLETE)
  100. /* SStatus register
  101. */
  102. #define SSTATUS_IPM_MASK 0x00000780
  103. #define SSTATUS_IPM_NOPRESENT 0x00000000
  104. #define SSTATUS_IPM_ACTIVE 0x00000080
  105. #define SSTATUS_IPM_PATIAL 0x00000100
  106. #define SSTATUS_IPM_SLUMBER 0x00000300
  107. #define SSTATUS_SPD_MASK 0x000000f0
  108. #define SSTATUS_SPD_GEN1 0x00000010
  109. #define SSTATUS_SPD_GEN2 0x00000020
  110. #define SSTATUS_DET_MASK 0x0000000f
  111. #define SSTATUS_DET_NODEVICE 0x00000000
  112. #define SSTATUS_DET_DISCONNECT 0x00000001
  113. #define SSTATUS_DET_CONNECT 0x00000003
  114. #define SSTATUS_DET_PHY_OFFLINE 0x00000004
  115. /* SControl register
  116. */
  117. #define SCONTROL_SPM_MASK 0x0000f000
  118. #define SCONTROL_SPM_GO_PARTIAL 0x00001000
  119. #define SCONTROL_SPM_GO_SLUMBER 0x00002000
  120. #define SCONTROL_SPM_GO_ACTIVE 0x00004000
  121. #define SCONTROL_IPM_MASK 0x00000f00
  122. #define SCONTROL_IPM_NO_RESTRICT 0x00000000
  123. #define SCONTROL_IPM_PARTIAL 0x00000100
  124. #define SCONTROL_IPM_SLUMBER 0x00000200
  125. #define SCONTROL_IPM_PART_SLUM 0x00000300
  126. #define SCONTROL_SPD_MASK 0x000000f0
  127. #define SCONTROL_SPD_NO_RESTRICT 0x00000000
  128. #define SCONTROL_SPD_GEN1 0x00000010
  129. #define SCONTROL_SPD_GEN2 0x00000020
  130. #define SCONTROL_DET_MASK 0x0000000f
  131. #define SCONTROL_DET_HRESET 0x00000001
  132. #define SCONTROL_DET_DISABLE 0x00000004
  133. /* TransCfg register
  134. */
  135. #define TRANSCFG_DFIS_SIZE_SHIFT 16
  136. #define TRANSCFG_RX_WATER_MARK_MASK 0x0000001f
  137. /* PhyCtrlCfg register
  138. */
  139. #define PHYCTRLCFG_FPRFTI_MASK 0x00000018
  140. #define PHYCTRLCFG_LOOPBACK_MASK 0x0000000e
  141. /*
  142. * Command Header Entry
  143. */
  144. typedef struct cmd_hdr_entry {
  145. __le32 cda; /* Command Descriptor Address,
  146. 4 bytes aligned */
  147. __le32 prde_fis_len; /* Number of PRD entries and FIS length */
  148. __le32 ttl; /* Total transfer length */
  149. __le32 attribute; /* the attribute of command */
  150. } __attribute__ ((packed)) cmd_hdr_entry_t;
  151. #define SATA_HC_CMD_HDR_ENTRY_SIZE sizeof(struct cmd_hdr_entry)
  152. /* cda
  153. */
  154. #define CMD_HDR_CDA_ALIGN 4
  155. /* prde_fis_len
  156. */
  157. #define CMD_HDR_PRD_ENTRY_SHIFT 16
  158. #define CMD_HDR_PRD_ENTRY_MASK 0x003f0000
  159. #define CMD_HDR_FIS_LEN_SHIFT 2
  160. /* attribute
  161. */
  162. #define CMD_HDR_ATTR_RES 0x00000800 /* Reserved bit, should be 1 */
  163. #define CMD_HDR_ATTR_VBIST 0x00000400 /* Vendor BIST */
  164. #define CMD_HDR_ATTR_SNOOP 0x00000200 /* Snoop enable for all descriptor */
  165. #define CMD_HDR_ATTR_FPDMA 0x00000100 /* FPDMA queued command */
  166. #define CMD_HDR_ATTR_RESET 0x00000080 /* Reset - a SRST or device reset */
  167. #define CMD_HDR_ATTR_BIST 0x00000040 /* BIST - require the host to enter BIST mode */
  168. #define CMD_HDR_ATTR_ATAPI 0x00000020 /* ATAPI command */
  169. #define CMD_HDR_ATTR_TAG 0x0000001f /* TAG mask */
  170. /* command type
  171. */
  172. enum cmd_type {
  173. CMD_VENDOR_BIST,
  174. CMD_BIST,
  175. CMD_RESET, /* SRST or device reset */
  176. CMD_ATAPI,
  177. CMD_NCQ,
  178. CMD_ATA, /* None of all above */
  179. };
  180. /*
  181. * Command Header Table
  182. */
  183. typedef struct cmd_hdr_tbl {
  184. cmd_hdr_entry_t cmd_slot[SATA_HC_MAX_CMD];
  185. } __attribute__ ((packed)) cmd_hdr_tbl_t;
  186. #define SATA_HC_CMD_HDR_TBL_SIZE sizeof(struct cmd_hdr_tbl)
  187. #define SATA_HC_CMD_HDR_TBL_ALIGN 4
  188. /*
  189. * PRD entry - Physical Region Descriptor entry
  190. */
  191. typedef struct prd_entry {
  192. __le32 dba; /* Data base address, 4 bytes aligned */
  193. u32 res1;
  194. u32 res2;
  195. __le32 ext_c_ddc; /* Indirect PRD flags, snoop and data word count */
  196. } __attribute__ ((packed)) prd_entry_t;
  197. #define SATA_HC_CMD_DESC_PRD_SIZE sizeof(struct prd_entry)
  198. /* dba
  199. */
  200. #define PRD_ENTRY_DBA_ALIGN 4
  201. /* ext_c_ddc
  202. */
  203. #define PRD_ENTRY_EXT 0x80000000 /* extension flag */
  204. #ifdef CONFIG_FSL_SATA_V2
  205. #define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */
  206. #else
  207. #define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */
  208. #endif
  209. #define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */
  210. #define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1)
  211. /*
  212. * This SATA host controller supports a max of 16 direct PRD entries, but if use
  213. * chained indirect PRD entries, then the contollers supports upto a max of 63
  214. * entries including direct and indirect PRD entries.
  215. * The PRDT is an array of 63 PRD entries contigiously, but the PRD entries#15
  216. * will be setup as an indirect descriptor, pointing to it's next (contigious)
  217. * PRD entries#16.
  218. */
  219. #define SATA_HC_MAX_PRD 63 /* Max PRD entry numbers per command */
  220. #define SATA_HC_MAX_PRD_DIRECT 16 /* Direct PRDT entries */
  221. #define SATA_HC_MAX_PRD_USABLE (SATA_HC_MAX_PRD - 1)
  222. #define SATA_HC_MAX_XFER_LEN 0x4000000
  223. /*
  224. * PRDT - Physical Region Descriptor Table
  225. */
  226. typedef struct prdt {
  227. prd_entry_t prdt[SATA_HC_MAX_PRD];
  228. } __attribute__ ((packed)) prdt_t;
  229. /*
  230. * Command Descriptor
  231. */
  232. #define SATA_HC_CMD_DESC_CFIS_SIZE 32 /* bytes */
  233. #define SATA_HC_CMD_DESC_SFIS_SIZE 32 /* bytes */
  234. #define SATA_HC_CMD_DESC_ACMD_SIZE 16 /* bytes */
  235. #define SATA_HC_CMD_DESC_RES 16 /* bytes */
  236. typedef struct cmd_desc {
  237. u8 cfis[SATA_HC_CMD_DESC_CFIS_SIZE];
  238. u8 sfis[SATA_HC_CMD_DESC_SFIS_SIZE];
  239. u8 acmd[SATA_HC_CMD_DESC_ACMD_SIZE];
  240. u8 res[SATA_HC_CMD_DESC_RES];
  241. prd_entry_t prdt[SATA_HC_MAX_PRD];
  242. } __attribute__ ((packed)) cmd_desc_t;
  243. #define SATA_HC_CMD_DESC_SIZE sizeof(struct cmd_desc)
  244. #define SATA_HC_CMD_DESC_ALIGN 4
  245. /*
  246. * SATA device driver info
  247. */
  248. typedef struct fsl_sata_info {
  249. u32 sata_reg_base;
  250. u32 flags;
  251. } fsl_sata_info_t;
  252. #define FLAGS_DMA 0x00000000
  253. #define FLAGS_FPDMA 0x00000001
  254. /*
  255. * SATA device driver struct
  256. */
  257. typedef struct fsl_sata {
  258. char name[12];
  259. fsl_sata_reg_t *reg_base; /* the base address of controller register */
  260. void *cmd_hdr_tbl_offset; /* alloc address of command header table */
  261. cmd_hdr_tbl_t *cmd_hdr; /* aligned address of command header table */
  262. void *cmd_desc_offset; /* alloc address of command descriptor */
  263. cmd_desc_t *cmd_desc; /* aligned address of command descriptor */
  264. int link; /* PHY link status */
  265. /* device attribute */
  266. int ata_device_type; /* device type */
  267. int lba48;
  268. int queue_depth; /* Max NCQ queue depth */
  269. u16 pio;
  270. u16 mwdma;
  271. u16 udma;
  272. int wcache;
  273. int flush;
  274. int flush_ext;
  275. u32 dma_flag;
  276. } fsl_sata_t;
  277. #define READ_CMD 0
  278. #define WRITE_CMD 1
  279. #if CONFIG_IS_ENABLED(BLK)
  280. struct fsl_ata_priv {
  281. u32 base;
  282. u32 flag;
  283. u32 number;
  284. u32 offset;
  285. fsl_sata_t *fsl_sata;
  286. };
  287. #endif
  288. #endif /* __FSL_SATA_H__ */