fsl_sata.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  4. * Copyright 2019 NXP
  5. * Author: Dave Liu <daveliu@freescale.com>
  6. */
  7. #include <common.h>
  8. #include <blk.h>
  9. #include <command.h>
  10. #include <console.h>
  11. #include <cpu_func.h>
  12. #include <log.h>
  13. #include <asm/io.h>
  14. #include <asm/processor.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <malloc.h>
  17. #include <libata.h>
  18. #include <fis.h>
  19. #include <sata.h>
  20. #include <linux/delay.h>
  21. #include "fsl_sata.h"
  22. #if CONFIG_IS_ENABLED(BLK)
  23. #include <dm.h>
  24. #include <ahci.h>
  25. #include <blk.h>
  26. #include <dm/device-internal.h>
  27. #else
  28. #ifndef CONFIG_SYS_SATA1_FLAGS
  29. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  30. #endif
  31. #ifndef CONFIG_SYS_SATA2_FLAGS
  32. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  33. #endif
  34. static struct fsl_sata_info fsl_sata_info[] = {
  35. #ifdef CONFIG_SATA1
  36. {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
  37. #else
  38. {0, 0},
  39. #endif
  40. #ifdef CONFIG_SATA2
  41. {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
  42. #else
  43. {0, 0},
  44. #endif
  45. };
  46. #endif
  47. static inline void sdelay(unsigned long sec)
  48. {
  49. unsigned long i;
  50. for (i = 0; i < sec; i++)
  51. mdelay(1000);
  52. }
  53. static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
  54. {
  55. printf("Status FIS dump:\n\r");
  56. printf("fis_type: %02x\n\r", s->fis_type);
  57. printf("pm_port_i: %02x\n\r", s->pm_port_i);
  58. printf("status: %02x\n\r", s->status);
  59. printf("error: %02x\n\r", s->error);
  60. printf("lba_low: %02x\n\r", s->lba_low);
  61. printf("lba_mid: %02x\n\r", s->lba_mid);
  62. printf("lba_high: %02x\n\r", s->lba_high);
  63. printf("device: %02x\n\r", s->device);
  64. printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
  65. printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
  66. printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
  67. printf("res1: %02x\n\r", s->res1);
  68. printf("sector_count: %02x\n\r", s->sector_count);
  69. printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
  70. }
  71. static int ata_wait_register(unsigned __iomem *addr, u32 mask,
  72. u32 val, u32 timeout_msec)
  73. {
  74. int i;
  75. u32 temp;
  76. for (i = 0; (((temp = in_le32(addr)) & mask) != val)
  77. && i < timeout_msec; i++)
  78. mdelay(1);
  79. return (i < timeout_msec) ? 0 : -1;
  80. }
  81. #if !CONFIG_IS_ENABLED(BLK)
  82. int init_sata(int dev)
  83. #else
  84. static int init_sata(struct fsl_ata_priv *priv, int dev)
  85. #endif
  86. {
  87. u32 length, align;
  88. cmd_hdr_tbl_t *cmd_hdr;
  89. u32 cda;
  90. u32 val32;
  91. fsl_sata_reg_t __iomem *reg;
  92. u32 sig;
  93. int i;
  94. fsl_sata_t *sata;
  95. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  96. printf("the sata index %d is out of ranges\n\r", dev);
  97. return -1;
  98. }
  99. #ifdef CONFIG_MPC85xx
  100. if ((dev == 0) && (!is_serdes_configured(SATA1))) {
  101. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  102. return -1;
  103. }
  104. if ((dev == 1) && (!is_serdes_configured(SATA2))) {
  105. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  106. return -1;
  107. }
  108. #endif
  109. /* Allocate SATA device driver struct */
  110. sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
  111. if (!sata) {
  112. printf("alloc the sata device struct failed\n\r");
  113. return -1;
  114. }
  115. /* Zero all of the device driver struct */
  116. memset((void *)sata, 0, sizeof(fsl_sata_t));
  117. snprintf(sata->name, 12, "SATA%d:", dev);
  118. /* Set the controller register base address to device struct */
  119. #if !CONFIG_IS_ENABLED(BLK)
  120. sata_dev_desc[dev].priv = (void *)sata;
  121. reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
  122. sata->dma_flag = fsl_sata_info[dev].flags;
  123. #else
  124. reg = (fsl_sata_reg_t *)(priv->base + priv->offset * dev);
  125. sata->dma_flag = priv->flag;
  126. priv->fsl_sata = sata;
  127. #endif
  128. sata->reg_base = reg;
  129. /* Allocate the command header table, 4 bytes aligned */
  130. length = sizeof(struct cmd_hdr_tbl);
  131. align = SATA_HC_CMD_HDR_TBL_ALIGN;
  132. sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
  133. if (!sata->cmd_hdr_tbl_offset) {
  134. printf("alloc the command header failed\n\r");
  135. return -1;
  136. }
  137. cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
  138. & ~(align - 1));
  139. sata->cmd_hdr = cmd_hdr;
  140. /* Zero all of the command header table */
  141. memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
  142. /* Allocate command descriptor for all command */
  143. length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
  144. align = SATA_HC_CMD_DESC_ALIGN;
  145. sata->cmd_desc_offset = (void *)malloc(length + align);
  146. if (!sata->cmd_desc_offset) {
  147. printf("alloc the command descriptor failed\n\r");
  148. return -1;
  149. }
  150. sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
  151. & ~(align - 1));
  152. /* Zero all of command descriptor */
  153. memset((void *)sata->cmd_desc_offset, 0, length + align);
  154. /* Link the command descriptor to command header */
  155. for (i = 0; i < SATA_HC_MAX_CMD; i++) {
  156. cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
  157. & ~(CMD_HDR_CDA_ALIGN - 1);
  158. cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
  159. }
  160. /* To have safe state, force the controller offline */
  161. val32 = in_le32(&reg->hcontrol);
  162. val32 &= ~HCONTROL_ONOFF;
  163. val32 |= HCONTROL_FORCE_OFFLINE;
  164. out_le32(&reg->hcontrol, val32);
  165. /* Wait the controller offline */
  166. ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
  167. /* Set the command header base address to CHBA register to tell DMA */
  168. out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
  169. /* Snoop for the command header */
  170. val32 = in_le32(&reg->hcontrol);
  171. val32 |= HCONTROL_HDR_SNOOP;
  172. out_le32(&reg->hcontrol, val32);
  173. /* Disable all of interrupts */
  174. val32 = in_le32(&reg->hcontrol);
  175. val32 &= ~HCONTROL_INT_EN_ALL;
  176. out_le32(&reg->hcontrol, val32);
  177. /* Clear all of interrupts */
  178. val32 = in_le32(&reg->hstatus);
  179. out_le32(&reg->hstatus, val32);
  180. /* Set the ICC, no interrupt coalescing */
  181. out_le32(&reg->icc, 0x01000000);
  182. /* No PM attatched, the SATA device direct connect */
  183. out_le32(&reg->cqpmp, 0);
  184. /* Clear SError register */
  185. val32 = in_le32(&reg->serror);
  186. out_le32(&reg->serror, val32);
  187. /* Clear CER register */
  188. val32 = in_le32(&reg->cer);
  189. out_le32(&reg->cer, val32);
  190. /* Clear DER register */
  191. val32 = in_le32(&reg->der);
  192. out_le32(&reg->der, val32);
  193. /* No device detection or initialization action requested */
  194. out_le32(&reg->scontrol, 0x00000300);
  195. /* Configure the transport layer, default value */
  196. out_le32(&reg->transcfg, 0x08000016);
  197. /* Configure the link layer, default value */
  198. out_le32(&reg->linkcfg, 0x0000ff34);
  199. /* Bring the controller online */
  200. val32 = in_le32(&reg->hcontrol);
  201. val32 |= HCONTROL_ONOFF;
  202. out_le32(&reg->hcontrol, val32);
  203. mdelay(100);
  204. /* print sata device name */
  205. printf("%s ", sata->name);
  206. /* Wait PHY RDY signal changed for 500ms */
  207. ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
  208. HSTATUS_PHY_RDY, 500);
  209. /* Check PHYRDY */
  210. val32 = in_le32(&reg->hstatus);
  211. if (val32 & HSTATUS_PHY_RDY) {
  212. sata->link = 1;
  213. } else {
  214. sata->link = 0;
  215. printf("(No RDY)\n\r");
  216. return -1;
  217. }
  218. /* Wait for signature updated, which is 1st D2H */
  219. ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
  220. HSTATUS_SIGNATURE, 10000);
  221. if (val32 & HSTATUS_SIGNATURE) {
  222. sig = in_le32(&reg->sig);
  223. debug("Signature updated, the sig =%08x\n\r", sig);
  224. sata->ata_device_type = ata_dev_classify(sig);
  225. }
  226. /* Check the speed */
  227. val32 = in_le32(&reg->sstatus);
  228. if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
  229. printf("(1.5 Gbps)\n\r");
  230. else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
  231. printf("(3 Gbps)\n\r");
  232. return 0;
  233. }
  234. int reset_sata(int dev)
  235. {
  236. return 0;
  237. }
  238. static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
  239. {
  240. printf("\n\rSATA: %08x\n\r", (u32)reg);
  241. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  242. printf("CAR: %08x\n\r", in_le32(&reg->car));
  243. printf("CCR: %08x\n\r", in_le32(&reg->ccr));
  244. printf("CER: %08x\n\r", in_le32(&reg->cer));
  245. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  246. printf("DER: %08x\n\r", in_le32(&reg->der));
  247. printf("CHBA: %08x\n\r", in_le32(&reg->chba));
  248. printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
  249. printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
  250. printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
  251. printf("SIG: %08x\n\r", in_le32(&reg->sig));
  252. printf("ICC: %08x\n\r", in_le32(&reg->icc));
  253. printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
  254. printf("SError: %08x\n\r", in_le32(&reg->serror));
  255. printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
  256. printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
  257. printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
  258. printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
  259. printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
  260. printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
  261. printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
  262. printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
  263. printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
  264. printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
  265. printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
  266. }
  267. static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  268. int is_ncq, int tag, u8 *buffer, u32 len)
  269. {
  270. cmd_hdr_entry_t *cmd_hdr;
  271. cmd_desc_t *cmd_desc;
  272. sata_fis_h2d_t *h2d;
  273. prd_entry_t *prde;
  274. u32 ext_c_ddc;
  275. u32 prde_count;
  276. u32 val32;
  277. u32 ttl;
  278. fsl_sata_reg_t __iomem *reg = sata->reg_base;
  279. int i;
  280. /* Check xfer length */
  281. if (len > SATA_HC_MAX_XFER_LEN) {
  282. printf("max transfer length is 64MB\n\r");
  283. return 0;
  284. }
  285. /* Setup the command descriptor */
  286. cmd_desc = sata->cmd_desc + tag;
  287. /* Get the pointer cfis of command descriptor */
  288. h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
  289. /* Zero the cfis of command descriptor */
  290. memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
  291. /* Copy the cfis from user to command descriptor */
  292. h2d->fis_type = cfis->fis_type;
  293. h2d->pm_port_c = cfis->pm_port_c;
  294. h2d->command = cfis->command;
  295. h2d->features = cfis->features;
  296. h2d->features_exp = cfis->features_exp;
  297. h2d->lba_low = cfis->lba_low;
  298. h2d->lba_mid = cfis->lba_mid;
  299. h2d->lba_high = cfis->lba_high;
  300. h2d->lba_low_exp = cfis->lba_low_exp;
  301. h2d->lba_mid_exp = cfis->lba_mid_exp;
  302. h2d->lba_high_exp = cfis->lba_high_exp;
  303. if (!is_ncq) {
  304. h2d->sector_count = cfis->sector_count;
  305. h2d->sector_count_exp = cfis->sector_count_exp;
  306. } else { /* NCQ */
  307. h2d->sector_count = (u8)(tag << 3);
  308. }
  309. h2d->device = cfis->device;
  310. h2d->control = cfis->control;
  311. /* Setup the PRD table */
  312. prde = (prd_entry_t *)cmd_desc->prdt;
  313. memset((void *)prde, 0, sizeof(struct prdt));
  314. prde_count = 0;
  315. ttl = len;
  316. for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
  317. if (!len)
  318. break;
  319. prde->dba = cpu_to_le32((u32)buffer & ~0x3);
  320. debug("dba = %08x\n\r", (u32)buffer);
  321. if (len < PRD_ENTRY_MAX_XFER_SZ) {
  322. ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
  323. debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
  324. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  325. prde_count++;
  326. prde++;
  327. break;
  328. } else {
  329. ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
  330. debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
  331. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  332. buffer += PRD_ENTRY_MAX_XFER_SZ;
  333. len -= PRD_ENTRY_MAX_XFER_SZ;
  334. prde_count++;
  335. prde++;
  336. }
  337. }
  338. /* Setup the command slot of cmd hdr */
  339. cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
  340. cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
  341. val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
  342. val32 |= sizeof(sata_fis_h2d_t);
  343. cmd_hdr->prde_fis_len = cpu_to_le32(val32);
  344. cmd_hdr->ttl = cpu_to_le32(ttl);
  345. if (!is_ncq) {
  346. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
  347. } else {
  348. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
  349. }
  350. tag &= CMD_HDR_ATTR_TAG;
  351. val32 |= tag;
  352. debug("attribute = %08x\n\r", val32);
  353. cmd_hdr->attribute = cpu_to_le32(val32);
  354. /* Make sure cmd desc and cmd slot valid before command issue */
  355. sync();
  356. /* PMP*/
  357. val32 = (u32)(h2d->pm_port_c & 0x0f);
  358. out_le32(&reg->cqpmp, val32);
  359. /* Wait no active */
  360. if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
  361. printf("Wait no active time out\n\r");
  362. /* Issue command */
  363. if (!(in_le32(&reg->cqr) & (1 << tag))) {
  364. val32 = 1 << tag;
  365. out_le32(&reg->cqr, val32);
  366. }
  367. /* Wait command completed for 10s */
  368. if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
  369. if (!is_ncq)
  370. printf("Non-NCQ command time out\n\r");
  371. else
  372. printf("NCQ command time out\n\r");
  373. }
  374. val32 = in_le32(&reg->cer);
  375. if (val32) {
  376. u32 der;
  377. fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
  378. printf("CE at device\n\r");
  379. fsl_sata_dump_regs(reg);
  380. der = in_le32(&reg->der);
  381. out_le32(&reg->cer, val32);
  382. out_le32(&reg->der, der);
  383. }
  384. /* Clear complete flags */
  385. val32 = in_le32(&reg->ccr);
  386. out_le32(&reg->ccr, val32);
  387. return len;
  388. }
  389. static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  390. int tag, u8 *buffer, u32 len)
  391. {
  392. return 0;
  393. }
  394. static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  395. enum cmd_type command_type, int tag, u8 *buffer, u32 len)
  396. {
  397. int rc;
  398. if (tag > SATA_HC_MAX_CMD || tag < 0) {
  399. printf("tag is out of range, tag=%d\n\r", tag);
  400. return -1;
  401. }
  402. switch (command_type) {
  403. case CMD_ATA:
  404. rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
  405. return rc;
  406. case CMD_RESET:
  407. rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
  408. return rc;
  409. case CMD_NCQ:
  410. rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
  411. return rc;
  412. case CMD_ATAPI:
  413. case CMD_VENDOR_BIST:
  414. case CMD_BIST:
  415. printf("not support now\n\r");
  416. return -1;
  417. default:
  418. break;
  419. }
  420. return -1;
  421. }
  422. static void fsl_sata_xfer_mode(fsl_sata_t *sata, u16 *id)
  423. {
  424. sata->pio = id[ATA_ID_PIO_MODES];
  425. sata->mwdma = id[ATA_ID_MWDMA_MODES];
  426. sata->udma = id[ATA_ID_UDMA_MODES];
  427. debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
  428. }
  429. static void fsl_sata_set_features(fsl_sata_t *sata)
  430. {
  431. struct sata_fis_h2d h2d, *cfis = &h2d;
  432. u8 udma_cap;
  433. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  434. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  435. cfis->pm_port_c = 0x80; /* is command */
  436. cfis->command = ATA_CMD_SET_FEATURES;
  437. cfis->features = SETFEATURES_XFER;
  438. /* First check the device capablity */
  439. udma_cap = (u8)(sata->udma & 0xff);
  440. debug("udma_cap %02x\n\r", udma_cap);
  441. if (udma_cap == ATA_UDMA6)
  442. cfis->sector_count = XFER_UDMA_6;
  443. if (udma_cap == ATA_UDMA5)
  444. cfis->sector_count = XFER_UDMA_5;
  445. if (udma_cap == ATA_UDMA4)
  446. cfis->sector_count = XFER_UDMA_4;
  447. if (udma_cap == ATA_UDMA3)
  448. cfis->sector_count = XFER_UDMA_3;
  449. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  450. }
  451. static u32 fsl_sata_rw_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt, u8 *buffer,
  452. int is_write)
  453. {
  454. struct sata_fis_h2d h2d, *cfis = &h2d;
  455. u32 block;
  456. block = start;
  457. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  458. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  459. cfis->pm_port_c = 0x80; /* is command */
  460. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  461. cfis->device = ATA_LBA;
  462. cfis->device |= (block >> 24) & 0xf;
  463. cfis->lba_high = (block >> 16) & 0xff;
  464. cfis->lba_mid = (block >> 8) & 0xff;
  465. cfis->lba_low = block & 0xff;
  466. cfis->sector_count = (u8)(blkcnt & 0xff);
  467. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  468. return blkcnt;
  469. }
  470. static void fsl_sata_flush_cache(fsl_sata_t *sata)
  471. {
  472. struct sata_fis_h2d h2d, *cfis = &h2d;
  473. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  474. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  475. cfis->pm_port_c = 0x80; /* is command */
  476. cfis->command = ATA_CMD_FLUSH;
  477. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  478. }
  479. static u32 fsl_sata_rw_cmd_ext(fsl_sata_t *sata, u32 start, u32 blkcnt,
  480. u8 *buffer, int is_write)
  481. {
  482. struct sata_fis_h2d h2d, *cfis = &h2d;
  483. u64 block;
  484. block = (u64)start;
  485. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  486. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  487. cfis->pm_port_c = 0x80; /* is command */
  488. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  489. : ATA_CMD_READ_EXT;
  490. cfis->lba_high_exp = (block >> 40) & 0xff;
  491. cfis->lba_mid_exp = (block >> 32) & 0xff;
  492. cfis->lba_low_exp = (block >> 24) & 0xff;
  493. cfis->lba_high = (block >> 16) & 0xff;
  494. cfis->lba_mid = (block >> 8) & 0xff;
  495. cfis->lba_low = block & 0xff;
  496. cfis->device = ATA_LBA;
  497. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  498. cfis->sector_count = blkcnt & 0xff;
  499. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  500. return blkcnt;
  501. }
  502. static u32 fsl_sata_rw_ncq_cmd(fsl_sata_t *sata, u32 start, u32 blkcnt,
  503. u8 *buffer, int is_write)
  504. {
  505. struct sata_fis_h2d h2d, *cfis = &h2d;
  506. int ncq_channel;
  507. u64 block;
  508. if (sata->lba48 != 1) {
  509. printf("execute FPDMA command on non-LBA48 hard disk\n\r");
  510. return -1;
  511. }
  512. block = (u64)start;
  513. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  514. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  515. cfis->pm_port_c = 0x80; /* is command */
  516. cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
  517. : ATA_CMD_FPDMA_READ;
  518. cfis->lba_high_exp = (block >> 40) & 0xff;
  519. cfis->lba_mid_exp = (block >> 32) & 0xff;
  520. cfis->lba_low_exp = (block >> 24) & 0xff;
  521. cfis->lba_high = (block >> 16) & 0xff;
  522. cfis->lba_mid = (block >> 8) & 0xff;
  523. cfis->lba_low = block & 0xff;
  524. cfis->device = ATA_LBA;
  525. cfis->features_exp = (blkcnt >> 8) & 0xff;
  526. cfis->features = blkcnt & 0xff;
  527. if (sata->queue_depth >= SATA_HC_MAX_CMD)
  528. ncq_channel = SATA_HC_MAX_CMD - 1;
  529. else
  530. ncq_channel = sata->queue_depth - 1;
  531. /* Use the latest queue */
  532. fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
  533. return blkcnt;
  534. }
  535. static void fsl_sata_flush_cache_ext(fsl_sata_t *sata)
  536. {
  537. struct sata_fis_h2d h2d, *cfis = &h2d;
  538. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  539. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  540. cfis->pm_port_c = 0x80; /* is command */
  541. cfis->command = ATA_CMD_FLUSH_EXT;
  542. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  543. }
  544. static void fsl_sata_init_wcache(fsl_sata_t *sata, u16 *id)
  545. {
  546. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  547. sata->wcache = 1;
  548. if (ata_id_has_flush(id))
  549. sata->flush = 1;
  550. if (ata_id_has_flush_ext(id))
  551. sata->flush_ext = 1;
  552. }
  553. static u32 ata_low_level_rw_lba48(fsl_sata_t *sata, u32 blknr, lbaint_t blkcnt,
  554. const void *buffer, int is_write)
  555. {
  556. u32 start, blks;
  557. u8 *addr;
  558. int max_blks;
  559. start = blknr;
  560. blks = blkcnt;
  561. addr = (u8 *)buffer;
  562. max_blks = ATA_MAX_SECTORS_LBA48;
  563. do {
  564. if (blks > max_blks) {
  565. if (sata->dma_flag != FLAGS_FPDMA)
  566. fsl_sata_rw_cmd_ext(sata, start, max_blks, addr,
  567. is_write);
  568. else
  569. fsl_sata_rw_ncq_cmd(sata, start, max_blks, addr,
  570. is_write);
  571. start += max_blks;
  572. blks -= max_blks;
  573. addr += ATA_SECT_SIZE * max_blks;
  574. } else {
  575. if (sata->dma_flag != FLAGS_FPDMA)
  576. fsl_sata_rw_cmd_ext(sata, start, blks, addr,
  577. is_write);
  578. else
  579. fsl_sata_rw_ncq_cmd(sata, start, blks, addr,
  580. is_write);
  581. start += blks;
  582. blks = 0;
  583. addr += ATA_SECT_SIZE * blks;
  584. }
  585. } while (blks != 0);
  586. return blkcnt;
  587. }
  588. static u32 ata_low_level_rw_lba28(fsl_sata_t *sata, u32 blknr, u32 blkcnt,
  589. const void *buffer, int is_write)
  590. {
  591. u32 start, blks;
  592. u8 *addr;
  593. int max_blks;
  594. start = blknr;
  595. blks = blkcnt;
  596. addr = (u8 *)buffer;
  597. max_blks = ATA_MAX_SECTORS;
  598. do {
  599. if (blks > max_blks) {
  600. fsl_sata_rw_cmd(sata, start, max_blks, addr, is_write);
  601. start += max_blks;
  602. blks -= max_blks;
  603. addr += ATA_SECT_SIZE * max_blks;
  604. } else {
  605. fsl_sata_rw_cmd(sata, start, blks, addr, is_write);
  606. start += blks;
  607. blks = 0;
  608. addr += ATA_SECT_SIZE * blks;
  609. }
  610. } while (blks != 0);
  611. return blkcnt;
  612. }
  613. /*
  614. * SATA interface between low level driver and command layer
  615. */
  616. #if !CONFIG_IS_ENABLED(BLK)
  617. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  618. {
  619. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  620. #else
  621. static ulong sata_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  622. void *buffer)
  623. {
  624. struct fsl_ata_priv *priv = dev_get_plat(dev);
  625. fsl_sata_t *sata = priv->fsl_sata;
  626. #endif
  627. u32 rc;
  628. if (sata->lba48)
  629. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  630. READ_CMD);
  631. else
  632. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  633. READ_CMD);
  634. return rc;
  635. }
  636. #if !CONFIG_IS_ENABLED(BLK)
  637. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  638. {
  639. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  640. #else
  641. static ulong sata_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
  642. const void *buffer)
  643. {
  644. struct fsl_ata_priv *priv = dev_get_plat(dev);
  645. fsl_sata_t *sata = priv->fsl_sata;
  646. #endif
  647. u32 rc;
  648. if (sata->lba48) {
  649. rc = ata_low_level_rw_lba48(sata, blknr, blkcnt, buffer,
  650. WRITE_CMD);
  651. if (sata->wcache && sata->flush_ext)
  652. fsl_sata_flush_cache_ext(sata);
  653. } else {
  654. rc = ata_low_level_rw_lba28(sata, blknr, blkcnt, buffer,
  655. WRITE_CMD);
  656. if (sata->wcache && sata->flush)
  657. fsl_sata_flush_cache(sata);
  658. }
  659. return rc;
  660. }
  661. static void fsl_sata_identify(fsl_sata_t *sata, u16 *id)
  662. {
  663. struct sata_fis_h2d h2d, *cfis = &h2d;
  664. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  665. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  666. cfis->pm_port_c = 0x80; /* is command */
  667. cfis->command = ATA_CMD_ID_ATA;
  668. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
  669. ata_swap_buf_le16(id, ATA_ID_WORDS);
  670. }
  671. #if !CONFIG_IS_ENABLED(BLK)
  672. int scan_sata(int dev)
  673. {
  674. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  675. #else
  676. static int scan_sata(struct udevice *dev)
  677. {
  678. struct blk_desc *desc = dev_get_uclass_plat(dev);
  679. struct fsl_ata_priv *priv = dev_get_plat(dev);
  680. fsl_sata_t *sata = priv->fsl_sata;
  681. #endif
  682. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  683. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  684. unsigned char product[ATA_ID_PROD_LEN + 1];
  685. u16 *id;
  686. u64 n_sectors;
  687. /* if no detected link */
  688. if (!sata->link)
  689. return -1;
  690. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  691. if (!id) {
  692. printf("id malloc failed\n\r");
  693. return -1;
  694. }
  695. /* Identify device to get information */
  696. fsl_sata_identify(sata, id);
  697. /* Serial number */
  698. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  699. /* Firmware version */
  700. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  701. /* Product model */
  702. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  703. /* Totoal sectors */
  704. n_sectors = ata_id_n_sectors(id);
  705. #ifdef CONFIG_LBA48
  706. /* Check if support LBA48 */
  707. if (ata_id_has_lba48(id)) {
  708. sata->lba48 = 1;
  709. debug("Device support LBA48\n\r");
  710. } else
  711. debug("Device supports LBA28\n\r");
  712. #endif
  713. #if !CONFIG_IS_ENABLED(BLK)
  714. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  715. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  716. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  717. sata_dev_desc[dev].lba = (u32)n_sectors;
  718. #ifdef CONFIG_LBA48
  719. sata_dev_desc[dev].lba48 = sata->lba48;
  720. #endif
  721. #else
  722. memcpy(desc->product, serial, sizeof(serial));
  723. memcpy(desc->revision, firmware, sizeof(firmware));
  724. memcpy(desc->vendor, product, sizeof(product));
  725. desc->lba = n_sectors;
  726. #ifdef CONFIG_LBA48
  727. desc->lba48 = sata->lba48;
  728. #endif
  729. #endif
  730. /* Get the NCQ queue depth from device */
  731. sata->queue_depth = ata_id_queue_depth(id);
  732. /* Get the xfer mode from device */
  733. fsl_sata_xfer_mode(sata, id);
  734. /* Get the write cache status from device */
  735. fsl_sata_init_wcache(sata, id);
  736. /* Set the xfer mode to highest speed */
  737. fsl_sata_set_features(sata);
  738. #ifdef DEBUG
  739. ata_dump_id(id);
  740. #endif
  741. free((void *)id);
  742. return 0;
  743. }
  744. #if CONFIG_IS_ENABLED(BLK)
  745. static const struct blk_ops sata_fsl_blk_ops = {
  746. .read = sata_read,
  747. .write = sata_write,
  748. };
  749. U_BOOT_DRIVER(sata_fsl_driver) = {
  750. .name = "sata_fsl_blk",
  751. .id = UCLASS_BLK,
  752. .ops = &sata_fsl_blk_ops,
  753. .plat_auto = sizeof(struct fsl_ata_priv),
  754. };
  755. static int fsl_ata_of_to_plat(struct udevice *dev)
  756. {
  757. struct fsl_ata_priv *priv = dev_get_priv(dev);
  758. priv->number = dev_read_u32_default(dev, "sata-number", -1);
  759. priv->flag = dev_read_u32_default(dev, "sata-fpdma", -1);
  760. priv->offset = dev_read_u32_default(dev, "sata-offset", -1);
  761. priv->base = dev_read_addr(dev);
  762. if (priv->base == FDT_ADDR_T_NONE)
  763. return -EINVAL;
  764. return 0;
  765. }
  766. static int fsl_unbind_device(struct udevice *dev)
  767. {
  768. int ret;
  769. ret = device_remove(dev, DM_REMOVE_NORMAL);
  770. if (ret)
  771. return ret;
  772. ret = device_unbind(dev);
  773. if (ret)
  774. return ret;
  775. return 0;
  776. }
  777. static int fsl_ata_probe(struct udevice *dev)
  778. {
  779. struct fsl_ata_priv *blk_priv, *priv;
  780. struct udevice *blk;
  781. int failed_number;
  782. char sata_name[10];
  783. int nr_ports;
  784. int ret;
  785. int i;
  786. failed_number = 0;
  787. priv = dev_get_priv(dev);
  788. nr_ports = priv->number;
  789. nr_ports = min(nr_ports, CONFIG_SYS_SATA_MAX_DEVICE);
  790. for (i = 0; i < nr_ports; i++) {
  791. snprintf(sata_name, sizeof(sata_name), "fsl_sata%d", i);
  792. ret = blk_create_devicef(dev, "sata_fsl_blk", sata_name,
  793. IF_TYPE_SATA, -1, 512, 0, &blk);
  794. if (ret) {
  795. debug("Can't create device\n");
  796. return ret;
  797. }
  798. /* Init SATA port */
  799. ret = init_sata(priv, i);
  800. if (ret) {
  801. debug("%s: Failed to init sata\n", __func__);
  802. ret = fsl_unbind_device(blk);
  803. if (ret)
  804. return ret;
  805. failed_number++;
  806. continue;
  807. }
  808. blk_priv = dev_get_plat(blk);
  809. blk_priv->fsl_sata = priv->fsl_sata;
  810. /* Scan SATA port */
  811. ret = scan_sata(blk);
  812. if (ret) {
  813. debug("%s: Failed to scan bus\n", __func__);
  814. ret = fsl_unbind_device(blk);
  815. if (ret)
  816. return ret;
  817. failed_number++;
  818. continue;
  819. }
  820. }
  821. if (failed_number == nr_ports)
  822. return -ENODEV;
  823. else
  824. return 0;
  825. }
  826. static int fsl_ata_remove(struct udevice *dev)
  827. {
  828. fsl_sata_t *sata;
  829. struct fsl_ata_priv *priv;
  830. priv = dev_get_priv(dev);
  831. sata = priv->fsl_sata;
  832. free(sata->cmd_hdr_tbl_offset);
  833. free(sata->cmd_desc_offset);
  834. free(sata);
  835. return 0;
  836. }
  837. static int sata_fsl_scan(struct udevice *dev)
  838. {
  839. /* Nothing to do here */
  840. return 0;
  841. }
  842. struct ahci_ops sata_fsl_ahci_ops = {
  843. .scan = sata_fsl_scan,
  844. };
  845. static const struct udevice_id fsl_ata_ids[] = {
  846. { .compatible = "fsl,pq-sata-v2" },
  847. { }
  848. };
  849. U_BOOT_DRIVER(fsl_ahci) = {
  850. .name = "fsl_ahci",
  851. .id = UCLASS_AHCI,
  852. .of_match = fsl_ata_ids,
  853. .ops = &sata_fsl_ahci_ops,
  854. .of_to_plat = fsl_ata_of_to_plat,
  855. .probe = fsl_ata_probe,
  856. .remove = fsl_ata_remove,
  857. .priv_auto = sizeof(struct fsl_ata_priv),
  858. };
  859. #endif