meson-saradc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  4. * Copyright (C) 2018 BayLibre, SAS
  5. * Author: Neil Armstrong <narmstrong@baylibre.com>
  6. *
  7. * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
  8. */
  9. #include <common.h>
  10. #include <adc.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <regmap.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. #include <linux/delay.h>
  18. #include <linux/math64.h>
  19. #include <linux/bitfield.h>
  20. #include <power/regulator.h>
  21. #define MESON_SAR_ADC_REG0 0x00
  22. #define MESON_SAR_ADC_REG0_PANEL_DETECT BIT(31)
  23. #define MESON_SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
  24. #define MESON_SAR_ADC_REG0_DELTA_BUSY BIT(30)
  25. #define MESON_SAR_ADC_REG0_AVG_BUSY BIT(29)
  26. #define MESON_SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
  27. #define MESON_SAR_ADC_REG0_FIFO_FULL BIT(27)
  28. #define MESON_SAR_ADC_REG0_FIFO_EMPTY BIT(26)
  29. #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
  30. #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK GENMASK(20, 19)
  31. #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
  32. #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL BIT(15)
  33. #define MESON_SAR_ADC_REG0_SAMPLING_STOP BIT(14)
  34. #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK GENMASK(13, 12)
  35. #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL BIT(10)
  36. #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN BIT(9)
  37. #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
  38. #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
  39. #define MESON_SAR_ADC_REG0_SAMPLING_START BIT(2)
  40. #define MESON_SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
  41. #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
  42. #define MESON_SAR_ADC_CHAN_LIST 0x04
  43. #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
  44. #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
  45. (GENMASK(2, 0) << ((_chan) * 3))
  46. #define MESON_SAR_ADC_AVG_CNTL 0x08
  47. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
  48. (16 + ((_chan) * 2))
  49. #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
  50. (GENMASK(17, 16) << ((_chan) * 2))
  51. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  52. (0 + ((_chan) * 2))
  53. #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
  54. (GENMASK(1, 0) << ((_chan) * 2))
  55. #define MESON_SAR_ADC_REG3 0x0c
  56. #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY BIT(31)
  57. #define MESON_SAR_ADC_REG3_CLK_EN BIT(30)
  58. #define MESON_SAR_ADC_REG3_BL30_INITIALIZED BIT(28)
  59. #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
  60. #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
  61. #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
  62. #define MESON_SAR_ADC_REG3_DETECT_EN BIT(22)
  63. #define MESON_SAR_ADC_REG3_ADC_EN BIT(21)
  64. #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK GENMASK(20, 18)
  65. #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK GENMASK(17, 16)
  66. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT 10
  67. #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH 5
  68. #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
  69. #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
  70. #define MESON_SAR_ADC_DELAY 0x10
  71. #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
  72. #define MESON_SAR_ADC_DELAY_BL30_BUSY BIT(15)
  73. #define MESON_SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
  74. #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
  75. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
  76. #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
  77. #define MESON_SAR_ADC_LAST_RD 0x14
  78. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK GENMASK(23, 16)
  79. #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK GENMASK(9, 0)
  80. #define MESON_SAR_ADC_FIFO_RD 0x18
  81. #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
  82. #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
  83. #define MESON_SAR_ADC_AUX_SW 0x1c
  84. #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan) \
  85. (8 + (((_chan) - 2) * 3))
  86. #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX BIT(6)
  87. #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX BIT(5)
  88. #define MESON_SAR_ADC_AUX_SW_MODE_SEL BIT(4)
  89. #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW BIT(3)
  90. #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW BIT(2)
  91. #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW BIT(1)
  92. #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW BIT(0)
  93. #define MESON_SAR_ADC_CHAN_10_SW 0x20
  94. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
  95. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX BIT(22)
  96. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX BIT(21)
  97. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL BIT(20)
  98. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW BIT(19)
  99. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW BIT(18)
  100. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW BIT(17)
  101. #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW BIT(16)
  102. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
  103. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX BIT(6)
  104. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX BIT(5)
  105. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL BIT(4)
  106. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW BIT(3)
  107. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW BIT(2)
  108. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW BIT(1)
  109. #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW BIT(0)
  110. #define MESON_SAR_ADC_DETECT_IDLE_SW 0x24
  111. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
  112. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
  113. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX BIT(22)
  114. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX BIT(21)
  115. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL BIT(20)
  116. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
  117. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
  118. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
  119. #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
  120. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
  121. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX BIT(6)
  122. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX BIT(5)
  123. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL BIT(4)
  124. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW BIT(3)
  125. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW BIT(2)
  126. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW BIT(1)
  127. #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW BIT(0)
  128. #define MESON_SAR_ADC_DELTA_10 0x28
  129. #define MESON_SAR_ADC_DELTA_10_TEMP_SEL BIT(27)
  130. #define MESON_SAR_ADC_DELTA_10_TS_REVE1 BIT(26)
  131. #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK GENMASK(25, 16)
  132. #define MESON_SAR_ADC_DELTA_10_TS_REVE0 BIT(15)
  133. #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT 11
  134. #define MESON_SAR_ADC_DELTA_10_TS_C_MASK GENMASK(14, 11)
  135. #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN BIT(10)
  136. #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK GENMASK(9, 0)
  137. /*
  138. * NOTE: registers from here are undocumented (the vendor Linux kernel driver
  139. * and u-boot source served as reference). These only seem to be relevant on
  140. * GXBB and newer.
  141. */
  142. #define MESON_SAR_ADC_REG11 0x2c
  143. #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13)
  144. #define MESON_SAR_ADC_REG13 0x34
  145. #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8)
  146. #define MESON_SAR_ADC_MAX_FIFO_SIZE 32
  147. #define MESON_SAR_ADC_TIMEOUT 100 /* ms */
  148. #define NUM_CHANNELS 8
  149. #define MILLION 1000000
  150. struct meson_saradc_data {
  151. int num_bits;
  152. };
  153. struct meson_saradc_priv {
  154. const struct meson_saradc_data *data;
  155. struct regmap *regmap;
  156. struct clk core_clk;
  157. struct clk adc_clk;
  158. bool initialized;
  159. int active_channel;
  160. int calibbias;
  161. int calibscale;
  162. };
  163. static unsigned int
  164. meson_saradc_get_fifo_count(struct meson_saradc_priv *priv)
  165. {
  166. u32 regval;
  167. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  168. return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
  169. }
  170. static int meson_saradc_lock(struct meson_saradc_priv *priv)
  171. {
  172. uint val, timeout = 10000;
  173. /* prevent BL30 from using the SAR ADC while we are using it */
  174. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  175. MESON_SAR_ADC_DELAY_KERNEL_BUSY,
  176. MESON_SAR_ADC_DELAY_KERNEL_BUSY);
  177. /*
  178. * wait until BL30 releases it's lock (so we can use the SAR ADC)
  179. */
  180. do {
  181. udelay(1);
  182. regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
  183. } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
  184. if (timeout < 0) {
  185. printf("Timeout while waiting for BL30 unlock\n");
  186. return -ETIMEDOUT;
  187. }
  188. return 0;
  189. }
  190. static void meson_saradc_unlock(struct meson_saradc_priv *priv)
  191. {
  192. /* allow BL30 to use the SAR ADC again */
  193. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  194. MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
  195. }
  196. static void meson_saradc_clear_fifo(struct meson_saradc_priv *priv)
  197. {
  198. unsigned int count, tmp;
  199. for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
  200. if (!meson_saradc_get_fifo_count(priv))
  201. break;
  202. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
  203. }
  204. }
  205. static int meson_saradc_calib_val(struct meson_saradc_priv *priv, int val)
  206. {
  207. int tmp;
  208. /* use val_calib = scale * val_raw + offset calibration function */
  209. tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
  210. return clamp(tmp, 0, (1 << priv->data->num_bits) - 1);
  211. }
  212. static int meson_saradc_wait_busy_clear(struct meson_saradc_priv *priv)
  213. {
  214. uint regval, timeout = 10000;
  215. /*
  216. * NOTE: we need a small delay before reading the status, otherwise
  217. * the sample engine may not have started internally (which would
  218. * seem to us that sampling is already finished).
  219. */
  220. do {
  221. udelay(1);
  222. regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
  223. } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
  224. if (timeout < 0)
  225. return -ETIMEDOUT;
  226. return 0;
  227. }
  228. static int meson_saradc_read_raw_sample(struct meson_saradc_priv *priv,
  229. unsigned int channel, uint *val)
  230. {
  231. uint regval, fifo_chan, fifo_val, count;
  232. int ret;
  233. ret = meson_saradc_wait_busy_clear(priv);
  234. if (ret)
  235. return ret;
  236. count = meson_saradc_get_fifo_count(priv);
  237. if (count != 1) {
  238. printf("ADC FIFO has %d element(s) instead of one\n", count);
  239. return -EINVAL;
  240. }
  241. regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
  242. fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
  243. if (fifo_chan != channel) {
  244. printf("ADC FIFO entry belongs to channel %u instead of %u\n",
  245. fifo_chan, channel);
  246. return -EINVAL;
  247. }
  248. fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
  249. fifo_val &= GENMASK(priv->data->num_bits - 1, 0);
  250. *val = meson_saradc_calib_val(priv, fifo_val);
  251. return 0;
  252. }
  253. static void meson_saradc_start_sample_engine(struct meson_saradc_priv *priv)
  254. {
  255. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  256. MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
  257. MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
  258. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  259. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
  260. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
  261. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  262. MESON_SAR_ADC_REG0_SAMPLING_START,
  263. MESON_SAR_ADC_REG0_SAMPLING_START);
  264. }
  265. static void meson_saradc_stop_sample_engine(struct meson_saradc_priv *priv)
  266. {
  267. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  268. MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
  269. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  270. MESON_SAR_ADC_REG0_SAMPLING_STOP,
  271. MESON_SAR_ADC_REG0_SAMPLING_STOP);
  272. /* wait until all modules are stopped */
  273. meson_saradc_wait_busy_clear(priv);
  274. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  275. MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
  276. }
  277. enum meson_saradc_avg_mode {
  278. NO_AVERAGING = 0x0,
  279. MEAN_AVERAGING = 0x1,
  280. MEDIAN_AVERAGING = 0x2,
  281. };
  282. enum meson_saradc_num_samples {
  283. ONE_SAMPLE = 0x0,
  284. TWO_SAMPLES = 0x1,
  285. FOUR_SAMPLES = 0x2,
  286. EIGHT_SAMPLES = 0x3,
  287. };
  288. static void meson_saradc_set_averaging(struct meson_saradc_priv *priv,
  289. unsigned int channel,
  290. enum meson_saradc_avg_mode mode,
  291. enum meson_saradc_num_samples samples)
  292. {
  293. int val;
  294. val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
  295. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  296. MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
  297. val);
  298. val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
  299. regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
  300. MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
  301. }
  302. static void meson_saradc_enable_channel(struct meson_saradc_priv *priv,
  303. unsigned int channel)
  304. {
  305. uint regval;
  306. /*
  307. * the SAR ADC engine allows sampling multiple channels at the same
  308. * time. to keep it simple we're only working with one *internal*
  309. * channel, which starts counting at index 0 (which means: count = 1).
  310. */
  311. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
  312. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  313. MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
  314. /* map channel index 0 to the channel which we want to read */
  315. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), channel);
  316. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
  317. MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
  318. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  319. channel);
  320. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  321. MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
  322. regval);
  323. regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  324. channel);
  325. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
  326. MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
  327. regval);
  328. if (channel == 6)
  329. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
  330. MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
  331. }
  332. static int meson_saradc_get_sample(struct meson_saradc_priv *priv,
  333. int chan, uint *val)
  334. {
  335. int ret;
  336. ret = meson_saradc_lock(priv);
  337. if (ret)
  338. return ret;
  339. /* clear the FIFO to make sure we're not reading old values */
  340. meson_saradc_clear_fifo(priv);
  341. meson_saradc_set_averaging(priv, chan, MEAN_AVERAGING, EIGHT_SAMPLES);
  342. meson_saradc_enable_channel(priv, chan);
  343. meson_saradc_start_sample_engine(priv);
  344. ret = meson_saradc_read_raw_sample(priv, chan, val);
  345. meson_saradc_stop_sample_engine(priv);
  346. meson_saradc_unlock(priv);
  347. if (ret) {
  348. printf("failed to read sample for channel %d: %d\n",
  349. chan, ret);
  350. return ret;
  351. }
  352. return 0;
  353. }
  354. static int meson_saradc_channel_data(struct udevice *dev, int channel,
  355. unsigned int *data)
  356. {
  357. struct meson_saradc_priv *priv = dev_get_priv(dev);
  358. if (channel != priv->active_channel) {
  359. pr_err("Requested channel is not active!");
  360. return -EINVAL;
  361. }
  362. return meson_saradc_get_sample(priv, channel, data);
  363. }
  364. enum meson_saradc_chan7_mux_sel {
  365. CHAN7_MUX_VSS = 0x0,
  366. CHAN7_MUX_VDD_DIV4 = 0x1,
  367. CHAN7_MUX_VDD_DIV2 = 0x2,
  368. CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
  369. CHAN7_MUX_VDD = 0x4,
  370. CHAN7_MUX_CH7_INPUT = 0x7,
  371. };
  372. static void meson_saradc_set_chan7_mux(struct meson_saradc_priv *priv,
  373. enum meson_saradc_chan7_mux_sel sel)
  374. {
  375. u32 regval;
  376. regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
  377. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  378. MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
  379. udelay(20);
  380. }
  381. static int meson_saradc_calib(struct meson_saradc_priv *priv)
  382. {
  383. uint nominal0, nominal1, value0, value1;
  384. int ret;
  385. /* use points 25% and 75% for calibration */
  386. nominal0 = (1 << priv->data->num_bits) / 4;
  387. nominal1 = (1 << priv->data->num_bits) * 3 / 4;
  388. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_DIV4);
  389. udelay(20);
  390. ret = meson_saradc_get_sample(priv, 7, &value0);
  391. if (ret < 0)
  392. goto out;
  393. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_VDD_MUL3_DIV4);
  394. udelay(20);
  395. ret = meson_saradc_get_sample(priv, 7, &value1);
  396. if (ret < 0)
  397. goto out;
  398. if (value1 <= value0) {
  399. ret = -EINVAL;
  400. goto out;
  401. }
  402. priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
  403. value1 - value0);
  404. priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
  405. MILLION);
  406. ret = 0;
  407. out:
  408. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  409. return ret;
  410. }
  411. static int meson_saradc_init(struct meson_saradc_priv *priv)
  412. {
  413. uint regval;
  414. int ret, i;
  415. priv->calibscale = MILLION;
  416. /*
  417. * make sure we start at CH7 input since the other muxes are only used
  418. * for internal calibration.
  419. */
  420. meson_saradc_set_chan7_mux(priv, CHAN7_MUX_CH7_INPUT);
  421. /*
  422. * leave sampling delay and the input clocks as configured by
  423. * BL30 to make sure BL30 gets the values it expects when
  424. * reading the temperature sensor.
  425. */
  426. regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
  427. if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED) {
  428. regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
  429. if (regval & MESON_SAR_ADC_REG3_ADC_EN)
  430. return 0;
  431. }
  432. meson_saradc_stop_sample_engine(priv);
  433. /* update the channel 6 MUX to select the temperature sensor */
  434. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  435. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
  436. MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
  437. /* disable all channels by default */
  438. regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
  439. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  440. MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
  441. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  442. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
  443. MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
  444. /* delay between two samples = (10+1) * 1uS */
  445. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  446. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  447. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
  448. 10));
  449. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  450. MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  451. FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
  452. 0));
  453. /* delay between two samples = (10+1) * 1uS */
  454. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  455. MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  456. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
  457. 10));
  458. regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
  459. MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  460. FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
  461. 1));
  462. /*
  463. * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
  464. * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
  465. */
  466. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
  467. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  468. MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
  469. regval);
  470. regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
  471. regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
  472. MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
  473. regval);
  474. /*
  475. * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
  476. * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
  477. * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
  478. * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
  479. */
  480. regval = 0;
  481. for (i = 2; i <= 7; i++)
  482. regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
  483. regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
  484. regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
  485. regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
  486. ret = meson_saradc_lock(priv);
  487. if (ret)
  488. return ret;
  489. #if CONFIG_IS_ENABLED(CLK)
  490. ret = clk_enable(&priv->core_clk);
  491. if (ret)
  492. return ret;
  493. #endif
  494. regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
  495. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
  496. MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
  497. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
  498. MESON_SAR_ADC_REG11_BANDGAP_EN,
  499. MESON_SAR_ADC_REG11_BANDGAP_EN);
  500. regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
  501. MESON_SAR_ADC_REG3_ADC_EN,
  502. MESON_SAR_ADC_REG3_ADC_EN);
  503. udelay(5);
  504. #if CONFIG_IS_ENABLED(CLK)
  505. ret = clk_enable(&priv->adc_clk);
  506. if (ret)
  507. return ret;
  508. #endif
  509. meson_saradc_unlock(priv);
  510. ret = meson_saradc_calib(priv);
  511. if (ret) {
  512. printf("calibration failed\n");
  513. return -EIO;
  514. }
  515. return 0;
  516. }
  517. static int meson_saradc_start_channel(struct udevice *dev, int channel)
  518. {
  519. struct meson_saradc_priv *priv = dev_get_priv(dev);
  520. if (channel < 0 || channel >= NUM_CHANNELS) {
  521. printf("Requested channel is invalid!");
  522. return -EINVAL;
  523. }
  524. if (!priv->initialized) {
  525. int ret;
  526. ret = meson_saradc_init(priv);
  527. if (ret)
  528. return ret;
  529. priv->initialized = true;
  530. }
  531. priv->active_channel = channel;
  532. return 0;
  533. }
  534. static int meson_saradc_stop(struct udevice *dev)
  535. {
  536. struct meson_saradc_priv *priv = dev_get_priv(dev);
  537. priv->active_channel = -1;
  538. return 0;
  539. }
  540. static int meson_saradc_probe(struct udevice *dev)
  541. {
  542. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  543. struct meson_saradc_priv *priv = dev_get_priv(dev);
  544. struct udevice *vref;
  545. int vref_uv;
  546. int ret;
  547. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  548. if (ret)
  549. return ret;
  550. #if CONFIG_IS_ENABLED(CLK)
  551. ret = clk_get_by_name(dev, "core", &priv->core_clk);
  552. if (ret)
  553. return ret;
  554. ret = clk_get_by_name(dev, "adc_clk", &priv->adc_clk);
  555. if (ret)
  556. return ret;
  557. #endif
  558. priv->active_channel = -1;
  559. ret = device_get_supply_regulator(dev, "vref-supply", &vref);
  560. if (ret) {
  561. printf("can't get vref-supply: %d\n", ret);
  562. return ret;
  563. }
  564. vref_uv = regulator_get_value(vref);
  565. if (vref_uv < 0) {
  566. printf("can't get vref-supply value: %d\n", vref_uv);
  567. return vref_uv;
  568. }
  569. /* VDD supplied by common vref pin */
  570. uc_pdata->vdd_supply = vref;
  571. uc_pdata->vdd_microvolts = vref_uv;
  572. uc_pdata->vss_microvolts = 0;
  573. return 0;
  574. }
  575. int meson_saradc_of_to_plat(struct udevice *dev)
  576. {
  577. struct adc_uclass_plat *uc_pdata = dev_get_uclass_plat(dev);
  578. struct meson_saradc_priv *priv = dev_get_priv(dev);
  579. priv->data = (struct meson_saradc_data *)dev_get_driver_data(dev);
  580. uc_pdata->data_mask = GENMASK(priv->data->num_bits - 1, 0);
  581. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  582. uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT * 1000;
  583. uc_pdata->channel_mask = GENMASK(NUM_CHANNELS - 1, 0);
  584. return 0;
  585. }
  586. static const struct adc_ops meson_saradc_ops = {
  587. .start_channel = meson_saradc_start_channel,
  588. .channel_data = meson_saradc_channel_data,
  589. .stop = meson_saradc_stop,
  590. };
  591. static const struct meson_saradc_data gxbb_saradc_data = {
  592. .num_bits = 10,
  593. };
  594. static const struct meson_saradc_data gxl_saradc_data = {
  595. .num_bits = 12,
  596. };
  597. static const struct udevice_id meson_saradc_ids[] = {
  598. { .compatible = "amlogic,meson-gxbb-saradc",
  599. .data = (ulong)&gxbb_saradc_data },
  600. { .compatible = "amlogic,meson-gxl-saradc",
  601. .data = (ulong)&gxl_saradc_data },
  602. { .compatible = "amlogic,meson-gxm-saradc",
  603. .data = (ulong)&gxl_saradc_data },
  604. { .compatible = "amlogic,meson-g12a-saradc",
  605. .data = (ulong)&gxl_saradc_data },
  606. { }
  607. };
  608. U_BOOT_DRIVER(meson_saradc) = {
  609. .name = "meson_saradc",
  610. .id = UCLASS_ADC,
  611. .of_match = meson_saradc_ids,
  612. .ops = &meson_saradc_ops,
  613. .probe = meson_saradc_probe,
  614. .of_to_plat = meson_saradc_of_to_plat,
  615. .priv_auto = sizeof(struct meson_saradc_priv),
  616. };