sun4i-usb-phy.txt 2.4 KB

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  1. Allwinner sun4i USB PHY
  2. -----------------------
  3. Required properties:
  4. - compatible : should be one of
  5. * allwinner,sun4i-a10-usb-phy
  6. * allwinner,sun5i-a13-usb-phy
  7. * allwinner,sun6i-a31-usb-phy
  8. * allwinner,sun7i-a20-usb-phy
  9. * allwinner,sun8i-a23-usb-phy
  10. * allwinner,sun8i-a33-usb-phy
  11. * allwinner,sun8i-a83t-usb-phy
  12. * allwinner,sun8i-h3-usb-phy
  13. * allwinner,sun8i-v3s-usb-phy
  14. * allwinner,sun50i-a64-usb-phy
  15. - reg : a list of offset + length pairs
  16. - reg-names :
  17. * "phy_ctrl"
  18. * "pmu0" for H3, V3s and A64
  19. * "pmu1"
  20. * "pmu2" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
  21. * "pmu3" for sun8i-h3
  22. - #phy-cells : from the generic phy bindings, must be 1
  23. - clocks : phandle + clock specifier for the phy clocks
  24. - clock-names :
  25. * "usb_phy" for sun4i, sun5i or sun7i
  26. * "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
  27. * "usb0_phy", "usb1_phy" for sun8i
  28. * "usb0_phy", "usb1_phy", "usb2_phy" and "usb2_hsic_12M" for sun8i-a83t
  29. * "usb0_phy", "usb1_phy", "usb2_phy" and "usb3_phy" for sun8i-h3
  30. - resets : a list of phandle + reset specifier pairs
  31. - reset-names :
  32. * "usb0_reset"
  33. * "usb1_reset"
  34. * "usb2_reset" for sun4i, sun6i, sun7i, sun8i-a83t or sun8i-h3
  35. * "usb3_reset" for sun8i-h3
  36. Optional properties:
  37. - usb0_id_det-gpios : gpio phandle for reading the otg id pin value
  38. - usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
  39. - usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
  40. - usb0_vbus-supply : regulator phandle for controller usb0 vbus
  41. - usb1_vbus-supply : regulator phandle for controller usb1 vbus
  42. - usb2_vbus-supply : regulator phandle for controller usb2 vbus
  43. - usb3_vbus-supply : regulator phandle for controller usb3 vbus
  44. Example:
  45. usbphy: phy@01c13400 {
  46. #phy-cells = <1>;
  47. compatible = "allwinner,sun4i-a10-usb-phy";
  48. /* phy base regs, phy1 pmu reg, phy2 pmu reg */
  49. reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
  50. reg-names = "phy_ctrl", "pmu1", "pmu2";
  51. clocks = <&usb_clk 8>;
  52. clock-names = "usb_phy";
  53. resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
  54. reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
  55. pinctrl-names = "default";
  56. pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
  57. usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
  58. usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
  59. usb0_vbus-supply = <&reg_usb0_vbus>;
  60. usb1_vbus-supply = <&reg_usb1_vbus>;
  61. usb2_vbus-supply = <&reg_usb2_vbus>;
  62. };