mediatek-pcie.txt 4.4 KB

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  1. MediaTek Gen2 PCIe controller
  2. Required properties:
  3. - compatible: Should contain one of the following strings:
  4. "mediatek,mt7623-pcie"
  5. - device_type: Must be "pci"
  6. - reg: Base addresses and lengths of the PCIe subsys and root ports.
  7. - reg-names: Names of the above areas to use during resource lookup.
  8. - #address-cells: Address representation for root ports (must be 3)
  9. - #size-cells: Size representation for root ports (must be 2)
  10. - clocks: Must contain an entry for each entry in clock-names.
  11. - clock-names:
  12. Mandatory entries:
  13. - sys_ckN :transaction layer and data link layer clock
  14. Required entries for MT7623:
  15. - free_ck :for reference clock of PCIe subsys
  16. where N starting from 0 to one less than the number of root ports.
  17. - phys: List of PHY specifiers (used by generic PHY framework).
  18. - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
  19. number of PHYs as specified in *phys* property.
  20. - power-domains: A phandle and power domain specifier pair to the power domain
  21. which is responsible for collapsing and restoring power to the peripheral.
  22. - bus-range: Range of bus numbers associated with this controller.
  23. - ranges: Ranges for the PCI memory and I/O regions.
  24. Required properties for MT7623:
  25. - #interrupt-cells: Size representation for interrupts (must be 1)
  26. - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  27. Please refer to the standard PCI bus binding document for a more detailed
  28. explanation.
  29. - resets: Must contain an entry for each entry in reset-names.
  30. - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
  31. number of root ports.
  32. In addition, the device tree node must have sub-nodes describing each
  33. PCIe port interface, having the following mandatory properties:
  34. Required properties:
  35. - device_type: Must be "pci"
  36. - reg: Only the first four bytes are used to refer to the correct bus number
  37. and device number.
  38. - #address-cells: Must be 3
  39. - #size-cells: Must be 2
  40. - #interrupt-cells: Must be 1
  41. - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
  42. Please refer to the standard PCI bus binding document for a more detailed
  43. explanation.
  44. - ranges: Sub-ranges distributed from the PCIe controller node. An empty
  45. property is sufficient.
  46. Examples for MT7623:
  47. hifsys: syscon@1a000000 {
  48. compatible = "mediatek,mt7623-hifsys",
  49. "syscon";
  50. reg = <0x1a000000 0x1000>;
  51. #clock-cells = <1>;
  52. #reset-cells = <1>;
  53. };
  54. pcie: pcie@1a140000 {
  55. compatible = "mediatek,mt7623-pcie";
  56. device_type = "pci";
  57. reg = <0x1a140000 0x1000>, /* PCIe shared registers */
  58. <0x1a142000 0x1000>, /* Port0 registers */
  59. <0x1a143000 0x1000>, /* Port1 registers */
  60. <0x1a144000 0x1000>; /* Port2 registers */
  61. reg-names = "subsys", "port0", "port1", "port2";
  62. #address-cells = <3>;
  63. #size-cells = <2>;
  64. #interrupt-cells = <1>;
  65. interrupt-map-mask = <0xf800 0 0 0>;
  66. interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  67. <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  68. <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  69. clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
  70. <&hifsys CLK_HIFSYS_PCIE0>,
  71. <&hifsys CLK_HIFSYS_PCIE1>,
  72. <&hifsys CLK_HIFSYS_PCIE2>;
  73. clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
  74. resets = <&hifsys HIFSYS_PCIE0_RST>,
  75. <&hifsys HIFSYS_PCIE1_RST>,
  76. <&hifsys HIFSYS_PCIE2_RST>;
  77. reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
  78. phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
  79. <&pcie2_phy PHY_TYPE_PCIE>;
  80. phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
  81. power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
  82. bus-range = <0x00 0xff>;
  83. ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */
  84. 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */
  85. pcie@0,0 {
  86. reg = <0x0000 0 0 0 0>;
  87. #address-cells = <3>;
  88. #size-cells = <2>;
  89. #interrupt-cells = <1>;
  90. interrupt-map-mask = <0 0 0 0>;
  91. interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
  92. ranges;
  93. };
  94. pcie@1,0 {
  95. reg = <0x0800 0 0 0 0>;
  96. #address-cells = <3>;
  97. #size-cells = <2>;
  98. #interrupt-cells = <1>;
  99. interrupt-map-mask = <0 0 0 0>;
  100. interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
  101. ranges;
  102. };
  103. pcie@2,0 {
  104. reg = <0x1000 0 0 0 0>;
  105. #address-cells = <3>;
  106. #size-cells = <2>;
  107. #interrupt-cells = <1>;
  108. interrupt-map-mask = <0 0 0 0>;
  109. interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  110. ranges;
  111. };
  112. };