intel,x86-broadwell-pinctrl.txt 6.7 KB

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  1. Intel x86 PINCTRL/GPIO controller
  2. Pin-muxing on broadwell devices can be described with a node for the PINCTRL
  3. master node and a set of child nodes for each required pin state on the SoC.
  4. These pin states use phandles and are referred to but a configuration section
  5. which lists all pins in the device.
  6. The PINCTRL master node requires the following properties:
  7. - compatible : "intel,x86-broadwell-pinctrl"
  8. Pin state nodes must be sub-nodes of the pinctrl master node. The must have
  9. a phandle. They can contain the following optional properties:
  10. - mode-gpio - forces the pin into GPIO mode
  11. - output-value - sets the default output value of the GPIO, 0 (low, default)
  12. or 1 (high)
  13. - direction - sets the direction of the gpio, either PIN_INPUT (default)
  14. or PIN_OUTPUT
  15. - invert - the input pin is inverted
  16. - trigger - sets the trigger type, either TRIGGER_EDGE (default) or
  17. TRIGGER_LEVEL
  18. - sense-disable - the input state sense is disabled
  19. - owner 0 sets the owner of the pin, either OWNER_ACPI (default) or
  20. ONWER_GPIO
  21. - route - sets whether the pin is routed, either PIRQ_APIC_MASK or
  22. PIRQ_APIC_ROUTE
  23. - irq-enable - the interrupt is enabled
  24. - reset-rsmrst - the pin will only be reset by RSMRST
  25. - pirq-apic - the pin will be routed to the IOxAPIC
  26. The first pin state will be the default, so pins without a configuration will
  27. use that.
  28. The pin configuration node is also a sub-node of the pinctrl master node, but
  29. does not have a phandle. It has a single property:
  30. - config - configuration to use for each pin. Each entry has of 3 cells:
  31. - GPIO number (0..94)
  32. - phandle of configuration (above)
  33. - interrupt number (0..15)
  34. There should be one entry for each pin (i.e. 95 entries).
  35. But missing pins will receive the default configuration.
  36. Example:
  37. pch_pinctrl {
  38. compatible = "intel,x86-broadwell-pinctrl";
  39. /* Put this first: it is the default */
  40. gpio_unused: gpio-unused {
  41. mode-gpio;
  42. direction = <PIN_INPUT>;
  43. owner = <OWNER_GPIO>;
  44. sense-disable;
  45. };
  46. gpio_acpi_sci: acpi-sci {
  47. mode-gpio;
  48. direction = <PIN_INPUT>;
  49. invert;
  50. route = <ROUTE_SCI>;
  51. };
  52. gpio_acpi_smi: acpi-smi {
  53. mode-gpio;
  54. direction = <PIN_INPUT>;
  55. invert;
  56. route = <ROUTE_SMI>;
  57. };
  58. gpio_input: gpio-input {
  59. mode-gpio;
  60. direction = <PIN_INPUT>;
  61. owner = <OWNER_GPIO>;
  62. };
  63. gpio_input_invert: gpio-input-invert {
  64. mode-gpio;
  65. direction = <PIN_INPUT>;
  66. owner = <OWNER_GPIO>;
  67. invert;
  68. };
  69. gpio_native: gpio-native {
  70. };
  71. gpio_out_high: gpio-out-high {
  72. mode-gpio;
  73. direction = <PIN_OUTPUT>;
  74. output-value = <1>;
  75. owner = <OWNER_GPIO>;
  76. sense-disable;
  77. };
  78. gpio_out_low: gpio-out-low {
  79. mode-gpio;
  80. direction = <PIN_OUTPUT>;
  81. output-value = <0>;
  82. owner = <OWNER_GPIO>;
  83. sense-disable;
  84. };
  85. gpio_pirq: gpio-pirq {
  86. mode-gpio;
  87. direction = <PIN_INPUT>;
  88. owner = <OWNER_GPIO>;
  89. pirq-apic = <PIRQ_APIC_ROUTE>;
  90. };
  91. soc_gpio@0 {
  92. config =
  93. <0 &gpio_unused 0>, /* unused */
  94. <1 &gpio_unused 0>, /* unused */
  95. <2 &gpio_unused 0>, /* unused */
  96. <3 &gpio_unused 0>, /* unused */
  97. <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
  98. <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
  99. <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
  100. <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
  101. <8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */
  102. <9 &gpio_input_invert 0>,/* trackpad_int_l (wake) */
  103. <10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */
  104. <11 &gpio_unused 0>, /* unused */
  105. <12 &gpio_unused 0>, /* unused */
  106. <13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */
  107. <14 &gpio_pirq 4>, /* touch_int_l (pirqm) */
  108. <15 &gpio_unused 0>, /* unused (strap) */
  109. <16 &gpio_input 0>, /* pch_wp */
  110. <17 &gpio_unused 0>, /* unused */
  111. <18 &gpio_unused 0>, /* unused */
  112. <19 &gpio_unused 0>, /* unused */
  113. <20 &gpio_native 0>, /* pcie_wlan_clkreq_l */
  114. <21 &gpio_out_high 0>, /* pp3300_ssd_en */
  115. <22 &gpio_unused 0>, /* unused */
  116. <23 &gpio_out_low 0>, /* pp3300_autobahn_en */
  117. <24 &gpio_unused 0>, /* unused */
  118. <25 &gpio_input 0>, /* ec_in_rw */
  119. <26 &gpio_unused 0>, /* unused */
  120. <27 &gpio_acpi_sci 0>, /* pch_wake_l */
  121. <28 &gpio_unused 0>, /* unused */
  122. <29 &gpio_unused 0>, /* unused */
  123. <30 &gpio_native 0>, /* native: pch_suswarn_l */
  124. <31 &gpio_native 0>, /* native: acok_buf */
  125. <32 &gpio_native 0>, /* native: lpc_clkrun_l */
  126. <33 &gpio_native 0>, /* native: ssd_devslp */
  127. <34 &gpio_acpi_smi 0>, /* ec_smi_l */
  128. <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
  129. <36 &gpio_acpi_sci 0>, /* ec_sci_l */
  130. <37 &gpio_unused 0>, /* unused */
  131. <38 &gpio_unused 0>, /* unused */
  132. <39 &gpio_unused 0>, /* unused */
  133. <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
  134. <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
  135. <42 &gpio_unused 0>, /* wlan_disable_l */
  136. <43 &gpio_out_high 0>, /* pp1800_codec_en */
  137. <44 &gpio_unused 0>, /* unused */
  138. <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
  139. <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
  140. <47 &gpio_out_low 0>, /* ssd_reset_l */
  141. <48 &gpio_unused 0>, /* unused */
  142. <49 &gpio_unused 0>, /* unused */
  143. <50 &gpio_unused 0>, /* unused */
  144. <51 &gpio_unused 0>, /* unused */
  145. <52 &gpio_input 0>, /* sim_det */
  146. <53 &gpio_unused 0>, /* unused */
  147. <54 &gpio_unused 0>, /* unused */
  148. <55 &gpio_unused 0>, /* unused */
  149. <56 &gpio_unused 0>, /* unused */
  150. <57 &gpio_out_high 0>, /* codec_reset_l */
  151. <58 &gpio_unused 0>, /* unused */
  152. <59 &gpio_out_high 0>, /* lte_disable_l */
  153. <60 &gpio_unused 0>, /* unused */
  154. <61 &gpio_native 0>, /* native: pch_sus_stat */
  155. <62 &gpio_native 0>, /* native: pch_susclk */
  156. <63 &gpio_native 0>, /* native: pch_slp_s5_l */
  157. <64 &gpio_unused 0>, /* unused */
  158. <65 &gpio_input 0>, /* ram_id3 */
  159. <66 &gpio_input 0>, /* ram_id3_old (strap) */
  160. <67 &gpio_input 0>, /* ram_id0 */
  161. <68 &gpio_input 0>, /* ram_id1 */
  162. <69 &gpio_input 0>, /* ram_id2 */
  163. <70 &gpio_unused 0>, /* unused */
  164. <71 &gpio_native 0>, /* native: modphy_en */
  165. <72 &gpio_unused 0>, /* unused */
  166. <73 &gpio_unused 0>, /* unused */
  167. <74 &gpio_unused 0>, /* unused */
  168. <75 &gpio_unused 0>, /* unused */
  169. <76 &gpio_unused 0>, /* unused */
  170. <77 &gpio_unused 0>, /* unused */
  171. <78 &gpio_unused 0>, /* unused */
  172. <79 &gpio_unused 0>, /* unused */
  173. <80 &gpio_unused 0>, /* unused */
  174. <81 &gpio_unused 0>, /* unused */
  175. <82 &gpio_native 0>, /* native: ec_rcin_l */
  176. <83 &gpio_native 0>, /* gspi0_cs */
  177. <84 &gpio_native 0>, /* gspi0_clk */
  178. <85 &gpio_native 0>, /* gspi0_miso */
  179. <86 &gpio_native 0>, /* gspi0_mosi (strap) */
  180. <87 &gpio_unused 0>, /* unused */
  181. <88 &gpio_unused 0>, /* unused */
  182. <89 &gpio_out_high 0>, /* pp3300_sd_en */
  183. <90 &gpio_unused 0>, /* unused */
  184. <91 &gpio_unused 0>, /* unused */
  185. <92 &gpio_unused 0>, /* unused */
  186. <93 &gpio_unused 0>, /* unused */
  187. <94 &gpio_unused 0 >; /* unused */
  188. };
  189. };