altera-socfpga-a10-fpga-mgr.txt 1.6 KB

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  1. Altera SOCFPGA Arria10 FPGA Manager
  2. Required properties:
  3. - compatible : should contain "altr,socfpga-a10-fpga-mgr"
  4. - reg : base address and size for memory mapped io.
  5. - The first index is for FPGA manager register access.
  6. - The second index is for writing FPGA configuration data.
  7. - resets : Phandle and reset specifier for the device's reset.
  8. - clocks : Clocks used by the device.
  9. - altr,bitstream : Fit image file name for both FPGA peripheral bitstream,
  10. FPGA core bitstream and full bitstream.
  11. Full bitstream, consist of peripheral bitstream and core
  12. bitstream.
  13. FPGA peripheral bitstream is used to initialize FPGA IOs,
  14. PLL, IO48 and DDR. This bitstream is required to get DDR up
  15. running.
  16. FPGA core bitstream contains FPGA design which is used to
  17. program FPGA CRAM and ERAM.
  18. Example: Bundles both peripheral bitstream and core bitstream into FIT image
  19. called fit_spl_fpga.itb. This FIT image can be created through running
  20. this command: tools/mkimage
  21. -E -p 400
  22. -f board/altera/arria10-socdk/fit_spl_fpga.its
  23. fit_spl_fpga.itb
  24. For details of describing structure and contents of the FIT image,
  25. please refer board/altera/arria10-socdk/fit_spl_fpga.its
  26. - Examples for booting with full release or booting with early IO release, then
  27. follow by entering early user mode:
  28. fpga_mgr: fpga-mgr@ffd03000 {
  29. compatible = "altr,socfpga-a10-fpga-mgr";
  30. reg = <0xffd03000 0x100
  31. 0xffcfe400 0x20>;
  32. clocks = <&l4_mp_clk>;
  33. resets = <&rst FPGAMGR_RESET>;
  34. altr,bitstream = "fit_spl_fpga.itb";
  35. };