nios2.txt 1.7 KB

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  1. * Nios II Processor Binding
  2. This binding specifies what properties available in the device tree
  3. representation of a Nios II Processor Core.
  4. Users can use sopc2dts tool for generating device tree sources (dts) from a
  5. Qsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts
  6. Required properties:
  7. - compatible: Compatible property value should be "altr,nios2-1.0" or
  8. "altr,nios2-1.1".
  9. - reg: Contains CPU index.
  10. - clock-frequency: Contains the clock frequency for CPU, in Hz.
  11. - dcache-line-size: Contains data cache line size.
  12. - icache-line-size: Contains instruction line size.
  13. - dcache-size: Contains data cache size.
  14. - icache-size: Contains instruction cache size.
  15. - altr,reset-addr: Specifies CPU reset address
  16. - altr,exception-addr: Specifies CPU exception address
  17. Optional properties:
  18. - altr,has-initda: Specifies CPU support initda instruction, should be 1.
  19. - altr,has-mmu: Specifies CPU support MMU support.
  20. - altr,has-mul: Specifies CPU hardware multipy support.
  21. - altr,has-div: Specifies CPU hardware divide support
  22. - altr,implementation: Nios II core implementation, this should be "fast";
  23. Example:
  24. cpu@0x0 {
  25. device_type = "cpu";
  26. compatible = "altr,nios2-1.0";
  27. reg = <0>;
  28. interrupt-controller;
  29. #interrupt-cells = <1>;
  30. clock-frequency = <125000000>;
  31. dcache-line-size = <32>;
  32. icache-line-size = <32>;
  33. dcache-size = <32768>;
  34. icache-size = <32768>;
  35. altr,implementation = "fast";
  36. altr,pid-num-bits = <8>;
  37. altr,tlb-num-ways = <16>;
  38. altr,tlb-num-entries = <128>;
  39. altr,tlb-ptr-sz = <7>;
  40. altr,has-div = <1>;
  41. altr,has-mul = <1>;
  42. altr,reset-addr = <0xc2800000>;
  43. altr,fast-tlb-miss-addr = <0xc7fff400>;
  44. altr,exception-addr = <0xd0000020>;
  45. altr,has-initda = <1>;
  46. altr,has-mmu = <1>;
  47. };