minnowmax.rst 2.7 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. .. sectionauthor:: Simon Glass <sjg@chromium.org>
  3. Minnowboard MAX
  4. ===============
  5. This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
  6. Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
  7. the time of writing). Put it in the corresponding board directory and rename
  8. it to fsp.bin.
  9. Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
  10. board directory as vga.bin.
  11. You still need two more binary blobs. For Minnowboard MAX, we can reuse the
  12. same ME firmware above, but for flash descriptor, we need get that somewhere
  13. else, as the one above does not seem to work, probably because it is not
  14. designed for the Minnowboard MAX. Now download the original firmware image
  15. for this board from:
  16. * http://firmware.intel.com/sites/default/files/2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
  17. Unzip it::
  18. $ unzip 2014-WW42.4-MinnowBoardMax.73-64-bit.bin_Release.zip
  19. Use ifdtool in the U-Boot tools directory to extract the images from that
  20. file, for example::
  21. $ ./tools/ifdtool -x MNW2MAX1.X64.0073.R02.1409160934.bin
  22. This will provide the descriptor file - copy this into the correct place::
  23. $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
  24. Now you can build U-Boot and obtain u-boot.rom::
  25. $ make minnowmax_defconfig
  26. $ make all
  27. Checksums are as follows (but note that newer versions will invalidate this)::
  28. $ md5sum -b board/intel/minnowmax/*.bin
  29. ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
  30. 69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
  31. 894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
  32. a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
  33. The ROM image is broken up into these parts:
  34. ====== ================== ============================
  35. Offset Description Controlling config
  36. ====== ================== ============================
  37. 000000 descriptor.bin Hard-coded to 0 in ifdtool
  38. 001000 me.bin Set by the descriptor
  39. 500000 <spare>
  40. 6ef000 Environment CONFIG_ENV_OFFSET
  41. 6f0000 MRC cache CONFIG_ENABLE_MRC_CACHE
  42. 700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
  43. 7b0000 vga.bin CONFIG_VGA_BIOS_ADDR
  44. 7c0000 fsp.bin CONFIG_FSP_ADDR
  45. 7f8000 <spare> (depends on size of fsp.bin)
  46. 7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
  47. ====== ================== ============================
  48. Overall ROM image size is controlled by CONFIG_ROM_SIZE.
  49. Note that the debug version of the FSP is bigger in size. If this version
  50. is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
  51. the default value 0xfffc0000.