nds32.rst 3.2 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. NDS32
  3. =====
  4. NDS32 is a new high-performance 32-bit RISC microprocessor core.
  5. http://www.andestech.com/
  6. AndeStar ISA
  7. ------------
  8. AndeStar is a patent-pending 16-bit/32-bit mixed-length instruction set to
  9. achieve optimal system performance, code density, and power efficiency.
  10. It contains the following features:
  11. - Intermixable 32-bit and 16-bit instruction sets without the need for
  12. mode switch.
  13. - 16-bit instructions as a frequently used subset of 32-bit instructions.
  14. - RISC-style register-based instruction set.
  15. - 32 32-bit General Purpose Registers (GPR).
  16. - Upto 1024 User Special Registers (USR) for existing and extension
  17. instructions.
  18. - Rich load/store instructions for...
  19. - Single memory access with base address update.
  20. - Multiple aligned and unaligned memory accesses for memory copy and stack
  21. operations.
  22. - Data prefetch to improve data cache performance.
  23. - Non-bus locking synchronization instructions.
  24. - PC relative jump and PC read instructions for efficient position independent
  25. code.
  26. - Multiply-add and multiple-sub with 64-bit accumulator.
  27. - Instruction for efficient power management.
  28. - Bi-endian support.
  29. - Three instruction extension space for application acceleration:
  30. - Performance extension.
  31. - Andes future extensions (for floating-point, multimedia, etc.)
  32. - Customer extensions.
  33. AndesCore CPU
  34. -------------
  35. Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
  36. For details about N12 CPU family, please check below N1213 features.
  37. N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
  38. N1213 Features
  39. ^^^^^^^^^^^^^^
  40. CPU Core
  41. - 16-/32-bit mixable instruction format.
  42. - 32 general-purpose 32-bit registers.
  43. - 8-stage pipeline.
  44. - Dynamic branch prediction.
  45. - 32/64/128/256 BTB.
  46. - Return address stack (RAS).
  47. - Vector interrupts for internal/external.
  48. interrupt controller with 6 hardware interrupt signals.
  49. - 3 HW-level nested interruptions.
  50. - User and super-user mode support.
  51. - Memory-mapped I/O.
  52. - Address space up to 4GB.
  53. Memory Management Unit
  54. - TLB
  55. - 4/8-entry fully associative iTLB/dTLB.
  56. - 32/64/128-entry 4-way set-associati.ve main TLB.
  57. - TLB locking support
  58. - Optional hardware page table walker.
  59. - Two groups of page size support.
  60. - 4KB & 1MB.
  61. - 8KB & 1MB.
  62. Memory Subsystem
  63. - I & D cache.
  64. - Virtually indexed and physically tagged.
  65. - Cache size: 8KB/16KB/32KB/64KB.
  66. - Cache line size: 16B/32B.
  67. - Set associativity: 2-way, 4-way or direct-mapped.
  68. - Cache locking support.
  69. - I & D local memory (LM).
  70. - Size: 4KB to 1MB.
  71. - Bank numbers: 1 or 2.
  72. - Optional 1D/2D DMA engine.
  73. - Internal or external to CPU core.
  74. Bus Interface
  75. - Synchronous/Asynchronous AHB bus: 0, 1 or 2 ports.
  76. - Synchronous High speed memory port.
  77. (HSMP): 0, 1 or 2 ports.
  78. Debug
  79. - JTAG debug interface.
  80. - Embedded debug module (EDM).
  81. - Optional embedded program tracer interface.
  82. Miscellaneous
  83. - Programmable data endian control.
  84. - Performance monitoring mechanism.
  85. The NDS32 ports of u-boot, the Linux kernel, the GNU toolchain and other
  86. associated software are actively supported by Andes Technology Corporation.