mips.rst 1.7 KB

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  1. .. SPDX-License-Identifier: GPL-2.0+
  2. MIPS
  3. ====
  4. Notes for the MIPS architecture port of U-Boot
  5. Toolchains
  6. ----------
  7. * `ELDK < DULG < DENX <http://www.denx.de/wiki/DULG/ELDK>`_
  8. * `Embedded Debian -- Cross-development toolchains <http://www.emdebian.org/crosstools.html>`_
  9. * `Buildroot <http://buildroot.uclibc.org/>`_
  10. Known Issues
  11. ------------
  12. * Cache incoherency issue caused by do_bootelf_exec() at cmd_elf.c
  13. Cache will be disabled before entering the loaded ELF image without
  14. writing back and invalidating cache lines. This leads to cache
  15. incoherency in most cases, unless the code gets loaded after U-Boot
  16. re-initializes the cache. The more common uImage 'bootm' command does
  17. not suffer this problem.
  18. [workaround] To avoid this cache incoherency:
  19. - insert flush_cache(all) before calling dcache_disable(), or
  20. - fix dcache_disable() to do both flushing and disabling cache.
  21. * Note that Linux users need to kill dcache_disable() in do_bootelf_exec()
  22. or override do_bootelf_exec() not to disable I-/D-caches, because most
  23. Linux/MIPS ports don't re-enable caches after entering kernel_entry.
  24. TODOs
  25. -----
  26. * Probe CPU types, I-/D-cache and TLB size etc. automatically
  27. * Secondary cache support missing
  28. * Initialize TLB entries redardless of their use
  29. * R2000/R3000 class parts are not supported
  30. * Limited testing across different MIPS variants
  31. * Due to cache initialization issues, the DRAM on board must be
  32. initialized in board specific assembler language before the cache init
  33. code is run -- that is, initialize the DRAM in lowlevel_init().
  34. * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
  35. * support Qemu Malta