README.ubispl 4.1 KB

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  1. Lightweight UBI and UBI fastmap support
  2. # Copyright (C) Thomas Gleixner <tglx@linutronix.de>
  3. #
  4. # SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause
  5. Scans the UBI information and loads the requested static volumes into
  6. memory.
  7. Configuration Options:
  8. CONFIG_SPL_UBI
  9. Enables the SPL UBI support
  10. CONFIG_SPL_UBI_MAX_VOL_LEBS
  11. The maximum number of logical eraseblocks which a static volume
  12. to load can contain. Used for sizing the scan data structure
  13. CONFIG_SPL_UBI_MAX_PEB_SIZE
  14. The maximum physical erase block size. Either a compile time
  15. constant or runtime detection. Used for sizing the scan data
  16. structure
  17. CONFIG_SPL_UBI_MAX_PEBS
  18. The maximum physical erase block count. Either a compile time
  19. constant or runtime detection. Used for sizing the scan data
  20. structure
  21. CONFIG_SPL_UBI_VOL_IDS
  22. The maximum volume ids which can be loaded. Used for sizing the
  23. scan data structure.
  24. Usage notes:
  25. In the board config file define for example:
  26. #define CONFIG_SPL_UBI
  27. #define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
  28. #define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
  29. #define CONFIG_SPL_UBI_MAX_PEBS 4096
  30. #define CONFIG_SPL_UBI_VOL_IDS 8
  31. The size requirement is roughly as follows:
  32. 2k for the basic data structure
  33. + CONFIG_SPL_UBI_VOL_IDS * CONFIG_SPL_UBI_MAX_VOL_LEBS * 8
  34. + CONFIG_SPL_UBI_MAX_PEBS * 64
  35. + CONFIG_SPL_UBI_MAX_PEB_SIZE * UBI_FM_MAX_BLOCKS
  36. The last one is big, but I really don't care in that stage. Real world
  37. implementations only use the first couple of blocks, but the code
  38. handles up to UBI_FM_MAX_BLOCKS.
  39. Given the above configuration example the requirement is about 5M
  40. which is usually not a problem to reserve in the RAM along with the
  41. other areas like the kernel/dts load address.
  42. So something like this will do the trick:
  43. #define SPL_FINFO_ADDR 0x80800000
  44. #define SPL_DTB_LOAD_ADDR 0x81800000
  45. #define SPL_KERNEL_LOAD_ADDR 0x82000000
  46. In the board file, implement the following:
  47. static struct ubispl_load myvolumes[] = {
  48. {
  49. .vol_id = 0, /* kernel volume */
  50. .load_addr = (void *)SPL_KERNEL_LOAD_ADDR,
  51. },
  52. {
  53. .vol_id = 1, /* DT blob */
  54. .load_addr = (void *)SPL_DTB_LOAD_ADDR,
  55. }
  56. };
  57. int spl_start_uboot(void)
  58. {
  59. struct ubispl_info info;
  60. info.ubi = (struct ubi_scan_info *) SPL_FINFO_ADDR;
  61. info.fastmap = 1;
  62. info.read = nand_spl_read_flash;
  63. #if COMPILE_TIME_DEFINED
  64. /*
  65. * MY_NAND_NR_SPL_PEBS is the number of physical erase blocks
  66. * in the FLASH which are reserved for the SPL. Think about
  67. * mtd partitions:
  68. *
  69. * part_spl { .start = 0, .end = 4 }
  70. * part_ubi { .start = 4, .end = NR_PEBS }
  71. */
  72. info.peb_offset = MY_NAND_NR_SPL_PEBS;
  73. info.peb_size = CONFIG_SYS_NAND_BLOCK_SIZE;
  74. info.vid_offset = MY_NAND_UBI_VID_OFFS;
  75. info.leb_start = MY_NAND_UBI_DATA_OFFS;
  76. info.peb_count = MY_NAND_UBI_NUM_PEBS;
  77. #else
  78. get_flash_info(&flash_info);
  79. info.peb_offset = MY_NAND_NR_SPL_PEBS;
  80. info.peb_size = flash_info.peb_size;
  81. /*
  82. * The VID and Data offset depend on the capability of the
  83. * FLASH chip to do subpage writes.
  84. *
  85. * If the flash chip supports subpage writes, then the VID
  86. * header starts at the second subpage. So for 2k pages size
  87. * with 4 subpages the VID offset is 512. The DATA offset is 2k.
  88. *
  89. * If the flash chip does not support subpage writes then the
  90. * VID offset is FLASH_PAGE_SIZE and the DATA offset
  91. * 2 * FLASH_PAGE_SIZE
  92. */
  93. info.vid_offset = flash_info.vid_offset;
  94. info.leb_start = flash_info.data_offset;
  95. /*
  96. * The flash reports the total number of erase blocks, so
  97. * we need to subtract the number of blocks which are reserved
  98. * for the SPL itself and not managed by UBI.
  99. */
  100. info.peb_count = flash_info.peb_count - MY_NAND_NR_SPL_PEBS;
  101. #endif
  102. ret = ubispl_load_volumes(&info, myvolumes, ARRAY_SIZE(myvolumes);
  103. ....
  104. }
  105. Note: you can load any payload that way. You can even load u-boot from
  106. UBI, so the only non UBI managed FLASH area is the one which is
  107. reserved for the SPL itself and read from the SoC ROM.
  108. And you can do fallback scenarios:
  109. if (ubispl_load_volumes(&info, volumes0, ARRAY_SIZE(volumes0)))
  110. if (ubispl_load_volumes(&info, volumes1, ARRAY_SIZE(volumes1)))
  111. ubispl_load_volumes(&info, vol_uboot, ARRAY_SIZE(vol_uboot));