README.socfpga 6.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178
  1. ----------------------------------------
  2. SOCFPGA Documentation for U-Boot and SPL
  3. ----------------------------------------
  4. This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
  5. based SOCFPGA. To know more about the hardware itself, please refer to
  6. www.altera.com.
  7. socfpga_dw_mmc
  8. --------------
  9. Here are macro and detailed configuration required to enable DesignWare SDMMC
  10. controller support within SOCFPGA
  11. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256
  12. -> Using smaller max blk cnt to avoid flooding the limited stack in OCRAM
  13. ---------------------------------------------------------------------
  14. Cyclone 5 / Arria 5 generating the handoff header files for U-Boot SPL
  15. ---------------------------------------------------------------------
  16. This text is assuming quartus 16.1, but newer versions will probably work just fine too;
  17. verified with DE1_SOC_Linux_FB demo project (https://github.com/VCTLabs/DE1_SOC_Linux_FB).
  18. Updated/working projects should build using either process below.
  19. Note: it *should* work from Quartus 14.0.200 onwards, however, the current vendor demo
  20. projects must have the IP cores updated as shown below.
  21. Rebuilding your Quartus project
  22. -------------------------------
  23. Choose one of the follwing methods, either command line or GUI.
  24. Using the command line
  25. ~~~~~~~~~~~~~~~~~~~~~~
  26. First run the embedded command shell, using your path to the Quartus install:
  27. $ /path/to/intelFPGA/16.1/embedded/embedded_command_shell.sh
  28. Then (if necessary) update the IP cores in the project, generate HDL code, and
  29. build the project:
  30. $ cd path/to/project/dir
  31. $ qsys-generate soc_system.qsys --upgrade-ip-cores
  32. $ qsys-generate soc_system.qsys --synthesis=[VERILOG|VHDL]
  33. $ quartus_sh --flow compile <project name>
  34. Convert the resulting .sof file (SRAM object file) to .rbf file (Raw bit file):
  35. $ quartus_cpf -c <project_name>.sof soc_system.rbf
  36. Generate BSP handoff files
  37. ~~~~~~~~~~~~~~~~~~~~~~~~~~
  38. You can run the bsp editor GUI below, or run the following command from the
  39. project directory:
  40. $ /path/to/bsb/tools/bsp-create-settings --type spl --bsp-dir build \
  41. --preloader-settings-dir hps_isw_handoff/soc_system_hps_0/ \
  42. --settings build/settings.bsp
  43. You should use the bsp "build" directory above (ie, where the settings.bsp file is)
  44. in the following u-boot command to update the board headers. Once these headers
  45. are updated for a given project build, u-boot should be configured for the
  46. project board (eg, de0-nano-sockit) and then build the normal spl build.
  47. Now you can skip the GUI section.
  48. Using the Qsys GUI
  49. ~~~~~~~~~~~~~~~~~~
  50. 1. Navigate to your project directory
  51. 2. Run Quartus II
  52. 3. Open Project (Ctrl+J), select <project_name>.qpf
  53. 4. Run QSys [Tools->QSys]
  54. 4.1 In the Open dialog, select '<project_name>.qsys'
  55. 4.2 In the Open System dialog, wait until completion and press 'Close'
  56. 4.3 In the Qsys window, click on 'Generate HDL...' in bottom right corner
  57. 4.3.1 In the 'Generation' window, click 'Generate'
  58. 4.3.2 In the 'Generate' dialog, wait until completion and click 'Close'
  59. 4.4 In the QSys window, click 'Finish'
  60. 4.4.1 In the 'Quartus II' pop up window, click 'OK'
  61. 5. Back in Quartus II main window, do the following
  62. 5.1 Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
  63. 5.2 Use Processing -> Start Compilation (Ctrl+L)
  64. ... this may take some time, have patience ...
  65. 6. Start the embedded command shell as shown in the previous section
  66. 6.1 Change directory to 'software/spl_bsp'
  67. 6.2 Prepare BSP by launching the BSP editor from ECS
  68. => bsp-editor
  69. 6.3 In BSP editor
  70. 6.3.1 Use File -> Open
  71. 6.3.2 Select 'settings.bsp' file
  72. 6.3.3 Click Generate
  73. 6.3.4 Click Exit
  74. Post handoff generation
  75. ~~~~~~~~~~~~~~~~~~~~~~~
  76. Now that the handoff files are generated, U-Boot can be used to process
  77. the handoff files generated by the bsp-editor. For this, please use the
  78. following script from the u-boot source tree:
  79. $ ./arch/arm/mach-socfpga/qts-filter.sh \
  80. <soc_type> \
  81. <input_qts_dir> \
  82. <input_bsp_dir> \
  83. <output_dir>
  84. Process QTS-generated files into U-Boot compatible ones.
  85. soc_type - Type of SoC, either 'cyclone5' or 'arria5'.
  86. input_qts_dir - Directory with compiled Quartus project
  87. and containing the Quartus project file (QPF).
  88. input_bsp_dir - Directory with generated bsp containing
  89. the settings.bsp file.
  90. output_dir - Directory to store the U-Boot compatible
  91. headers.
  92. This will generate (or update) the following 4 files:
  93. iocsr_config.h
  94. pinmux_config.h
  95. pll_config.h
  96. sdram_config.h
  97. These files should be copied into "qts" directory in the board directory
  98. (see output argument of qts-filter.sh command above).
  99. Here is an example for the DE-0 Nano SoC after the above rebuild process:
  100. $ ll board/terasic/de0-nano-soc/qts/
  101. total 36
  102. -rw-r--r-- 1 sarnold sarnold 8826 Mar 21 18:11 iocsr_config.h
  103. -rw-r--r-- 1 sarnold sarnold 4398 Mar 21 18:11 pinmux_config.h
  104. -rw-r--r-- 1 sarnold sarnold 3190 Mar 21 18:11 pll_config.h
  105. -rw-r--r-- 1 sarnold sarnold 9022 Mar 21 18:11 sdram_config.h
  106. Note: file sizes will differ slightly depending on the selected board.
  107. Now your board is ready for full mainline support including U-Boot SPL.
  108. The Preloader will not be needed any more.
  109. ----------------------------------------------------------
  110. Arria 10 generating the handoff header files for U-Boot SPL
  111. ----------------------------------------------------------
  112. A header file for inclusion in a devicetree for Arria10 can be generated
  113. by the qts-filter-a10.sh script directly from the hps_isw_handoff/hps.xml
  114. file generated during the FPGA project compilation. The header contains
  115. all PLL, clock, pinmux, and bridge configurations required.
  116. Please look at the socfpga_arria10_socdk_sdmmc-u-boot.dtsi for an example
  117. that includes use of the generated handoff header.
  118. Devicetree header generation
  119. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  120. The qts-filter-a10.sh script can process the compile time genetated hps.xml
  121. to create the appropriate devicetree header.
  122. $ ./arch/arm/mach-socfpga/qts-filter-a10.sh \
  123. <hps_xml> \
  124. <output_file>
  125. hps_xml - hps_isw_handoff/hps.xml from Quartus project
  126. output_file - Output filename and location for header file
  127. The script generates a single header file names <output_file> that should
  128. be placed in arch/arm/dts.