README.nand 13 KB

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  1. # SPDX-License-Identifier: GPL-2.0+
  2. NAND FLASH commands and notes
  3. See NOTE below!!!
  4. # (C) Copyright 2003
  5. # Dave Ellis, SIXNET, dge@sixnetio.com
  6. #
  7. Commands:
  8. nand bad
  9. Print a list of all of the bad blocks in the current device.
  10. nand device
  11. Print information about the current NAND device.
  12. nand device num
  13. Make device `num' the current device and print information about it.
  14. nand erase off|partition size
  15. nand erase clean [off|partition size]
  16. Erase `size' bytes starting at offset `off'. Alternatively partition
  17. name can be specified, in this case size will be eventually limited
  18. to not exceed partition size (this behaviour applies also to read
  19. and write commands). Only complete erase blocks can be erased.
  20. If `erase' is specified without an offset or size, the entire flash
  21. is erased. If `erase' is specified with partition but without an
  22. size, the entire partition is erased.
  23. If `clean' is specified, a JFFS2-style clean marker is written to
  24. each block after it is erased.
  25. This command will not erase blocks that are marked bad. There is
  26. a debug option in cmd_nand.c to allow bad blocks to be erased.
  27. Please read the warning there before using it, as blocks marked
  28. bad by the manufacturer must _NEVER_ be erased.
  29. nand info
  30. Print information about all of the NAND devices found.
  31. nand read addr ofs|partition size
  32. Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
  33. are marked bad are skipped. If a page cannot be read because an
  34. uncorrectable data error is found, the command stops with an error.
  35. nand read.oob addr ofs|partition size
  36. Read `size' bytes from the out-of-band data area corresponding to
  37. `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
  38. data for one 512-byte page or 2 256-byte pages. There is no check
  39. for bad blocks or ECC errors.
  40. nand write addr ofs|partition size
  41. Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
  42. are marked bad are skipped. If a page cannot be read because an
  43. uncorrectable data error is found, the command stops with an error.
  44. As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
  45. as long as the image is short enough to fit even after skipping the
  46. bad blocks. Compact images, such as those produced by mkfs.jffs2
  47. should work well, but loading an image copied from another flash is
  48. going to be trouble if there are any bad blocks.
  49. nand write.trimffs addr ofs|partition size
  50. Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
  51. the NAND flash in a manner identical to the 'nand write' command
  52. described above -- with the additional check that all pages at the end
  53. of eraseblocks which contain only 0xff data will not be written to the
  54. NAND flash. This behaviour is required when flashing UBI images
  55. containing UBIFS volumes as per the UBI FAQ[1].
  56. [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
  57. nand write.oob addr ofs|partition size
  58. Write `size' bytes from `addr' to the out-of-band data area
  59. corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
  60. of data for one 512-byte page or 2 256-byte pages. There is no check
  61. for bad blocks.
  62. nand read.raw addr ofs|partition [count]
  63. nand write.raw addr ofs|partition [count]
  64. Read or write one or more pages at "ofs" in NAND flash, from or to
  65. "addr" in memory. This is a raw access, so ECC is avoided and the
  66. OOB area is transferred as well. If count is absent, it is assumed
  67. to be one page. As with .yaffs2 accesses, the data is formatted as
  68. a packed sequence of "data, oob, data, oob, ..." -- no alignment of
  69. individual pages is maintained.
  70. Configuration Options:
  71. CONFIG_SYS_NAND_U_BOOT_OFFS
  72. NAND Offset from where SPL will read u-boot image. This is the starting
  73. address of u-boot MTD partition in NAND.
  74. CONFIG_CMD_NAND
  75. Enables NAND support and commands.
  76. CONFIG_CMD_NAND_TORTURE
  77. Enables the torture command (see description of this command below).
  78. CONFIG_SYS_MAX_NAND_DEVICE
  79. The maximum number of NAND devices you want to support.
  80. CONFIG_SYS_NAND_MAX_ECCPOS
  81. If specified, overrides the maximum number of ECC bytes
  82. supported. Useful for reducing image size, especially with SPL.
  83. This must be at least 48 if nand_base.c is used.
  84. CONFIG_SYS_NAND_MAX_OOBFREE
  85. If specified, overrides the maximum number of free OOB regions
  86. supported. Useful for reducing image size, especially with SPL.
  87. This must be at least 2 if nand_base.c is used.
  88. CONFIG_SYS_NAND_MAX_CHIPS
  89. The maximum number of NAND chips per device to be supported.
  90. CONFIG_SYS_NAND_SELF_INIT
  91. Traditionally, glue code in drivers/mtd/nand/raw/nand.c has driven
  92. the initialization process -- it provides the mtd and nand
  93. structs, calls a board init function for a specific device,
  94. calls nand_scan(), and registers with mtd.
  95. This arrangement does not provide drivers with the flexibility to
  96. run code between nand_scan_ident() and nand_scan_tail(), or other
  97. deviations from the "normal" flow.
  98. If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/raw/nand.c
  99. will make one call to board_nand_init(), with no arguments. That
  100. function is responsible for calling a driver init function for
  101. each NAND device on the board, that performs all initialization
  102. tasks except setting mtd->name, and registering with the rest of
  103. U-Boot. Those last tasks are accomplished by calling nand_register()
  104. on the new mtd device.
  105. Example of new init to be added to the end of an existing driver
  106. init:
  107. /* chip is struct nand_chip, and is now provided by the driver. */
  108. mtd = nand_to_mtd(&chip);
  109. /*
  110. * Fill in appropriate values if this driver uses these fields,
  111. * or uses the standard read_byte/write_buf/etc. functions from
  112. * nand_base.c that use these fields.
  113. */
  114. chip.IO_ADDR_R = ...;
  115. chip.IO_ADDR_W = ...;
  116. if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
  117. error out
  118. /*
  119. * Insert here any code you wish to run after the chip has been
  120. * identified, but before any other I/O is done.
  121. */
  122. if (nand_scan_tail(mtd))
  123. error out
  124. /*
  125. * devnum is the device number to be used in nand commands
  126. * and in mtd->name. Must be less than CONFIG_SYS_MAX_NAND_DEVICE.
  127. */
  128. if (nand_register(devnum, mtd))
  129. error out
  130. In addition to providing more flexibility to the driver, it reduces
  131. the difference between a U-Boot driver and its Linux counterpart.
  132. nand_init() is now reduced to calling board_nand_init() once, and
  133. printing a size summary. This should also make it easier to
  134. transition to delayed NAND initialization.
  135. Please convert your driver even if you don't need the extra
  136. flexibility, so that one day we can eliminate the old mechanism.
  137. CONFIG_SYS_NAND_ONFI_DETECTION
  138. Enables detection of ONFI compliant devices during probe.
  139. And fetching device parameters flashed on device, by parsing
  140. ONFI parameter page.
  141. Platform specific options
  142. =========================
  143. CONFIG_NAND_OMAP_GPMC
  144. Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
  145. GPMC controller is used for parallel NAND flash devices, and can
  146. do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
  147. and BCH16 ECC algorithms.
  148. CONFIG_NAND_OMAP_ELM
  149. Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
  150. ELM controller is used for ECC error detection (not ECC calculation)
  151. of BCH4, BCH8 and BCH16 ECC algorithms.
  152. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  153. thus such SoC platforms need to depend on software library for ECC error
  154. detection. However ECC calculation on such plaforms would still be
  155. done by GPMC controller.
  156. CONFIG_SPL_NAND_AM33XX_BCH
  157. Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
  158. hardware ECC correction. This is useful for platforms which have ELM
  159. hardware engine and use NAND boot mode.
  160. Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
  161. so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
  162. SPL-NAND driver with software ECC correction support.
  163. CONFIG_NAND_OMAP_ECCSCHEME
  164. On OMAP platforms, this CONFIG specifies NAND ECC scheme.
  165. It can take following values:
  166. OMAP_ECC_HAM1_CODE_SW
  167. 1-bit Hamming code using software lib.
  168. (for legacy devices only)
  169. OMAP_ECC_HAM1_CODE_HW
  170. 1-bit Hamming code using GPMC hardware.
  171. (for legacy devices only)
  172. OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
  173. 4-bit BCH code (unsupported)
  174. OMAP_ECC_BCH4_CODE_HW
  175. 4-bit BCH code (unsupported)
  176. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
  177. 8-bit BCH code with
  178. - ecc calculation using GPMC hardware engine,
  179. - error detection using software library.
  180. - requires CONFIG_BCH to enable software BCH library
  181. (For legacy device which do not have ELM h/w engine)
  182. OMAP_ECC_BCH8_CODE_HW
  183. 8-bit BCH code with
  184. - ecc calculation using GPMC hardware engine,
  185. - error detection using ELM hardware engine.
  186. OMAP_ECC_BCH16_CODE_HW
  187. 16-bit BCH code with
  188. - ecc calculation using GPMC hardware engine,
  189. - error detection using ELM hardware engine.
  190. How to select ECC scheme on OMAP and AMxx platforms ?
  191. -----------------------------------------------------
  192. Though higher ECC schemes have more capability to detect and correct
  193. bit-flips, but still selection of ECC scheme is dependent on following
  194. - hardware engines present in SoC.
  195. Some legacy OMAP SoC do not have ELM h/w engine thus such
  196. SoC cannot support BCHx_HW ECC schemes.
  197. - size of OOB/Spare region
  198. With higher ECC schemes, more OOB/Spare area is required to
  199. store ECC. So choice of ECC scheme is limited by NAND oobsize.
  200. In general following expression can help:
  201. NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
  202. where
  203. NAND_OOBSIZE = number of bytes available in
  204. OOB/spare area per NAND page.
  205. NAND_PAGESIZE = bytes in main-area of NAND page.
  206. ECC_BYTES = number of ECC bytes generated to
  207. protect 512 bytes of data, which is:
  208. 3 for HAM1_xx ecc schemes
  209. 7 for BCH4_xx ecc schemes
  210. 14 for BCH8_xx ecc schemes
  211. 26 for BCH16_xx ecc schemes
  212. example to check for BCH16 on 2K page NAND
  213. NAND_PAGESIZE = 2048
  214. NAND_OOBSIZE = 64
  215. 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
  216. Thus BCH16 cannot be supported on 2K page NAND.
  217. However, for 4K pagesize NAND
  218. NAND_PAGESIZE = 4096
  219. NAND_OOBSIZE = 224
  220. ECC_BYTES = 26
  221. 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
  222. Thus BCH16 can be supported on 4K page NAND.
  223. CONFIG_NAND_OMAP_GPMC_PREFETCH
  224. On OMAP platforms that use the GPMC controller
  225. (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
  226. uses the prefetch mode to speed up read operations.
  227. NOTE:
  228. =====
  229. The Disk On Chip driver is currently broken and has been for some time.
  230. There is a driver in drivers/mtd/nand/raw, taken from Linux, that works with
  231. the current NAND system but has not yet been adapted to the u-boot
  232. environment.
  233. Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
  234. JFFS2 related commands:
  235. implement "nand erase clean" and old "nand erase"
  236. using both the new code which is able to skip bad blocks
  237. "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
  238. Miscellaneous and testing commands:
  239. "markbad [offset]"
  240. create an artificial bad block (for testing bad block handling)
  241. "scrub [offset length]"
  242. like "erase" but don't skip bad block. Instead erase them.
  243. DANGEROUS!!! Factory set bad blocks will be lost. Use only
  244. to remove artificial bad blocks created with the "markbad" command.
  245. "torture offset [size]"
  246. Torture block to determine if it is still reliable.
  247. Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
  248. This command returns 0 if the block is still reliable, else 1.
  249. If the block is detected as unreliable, it is up to the user to decide to
  250. mark this block as bad.
  251. The analyzed block is put through 3 erase / write cycles (or less if the block
  252. is detected as unreliable earlier).
  253. This command can be used in scripts, e.g. together with the markbad command to
  254. automate retries and handling of possibly newly detected bad blocks if the
  255. nand write command fails.
  256. It can also be used manually by users having seen some NAND errors in logs to
  257. search the root cause of these errors.
  258. The underlying nand_torture() function is also useful for code willing to
  259. automate actions following a nand->write() error. This would e.g. be required
  260. in order to program or update safely firmware to NAND, especially for the UBI
  261. part of such firmware.
  262. Optionally, a second parameter size can be given to test multiple blocks with
  263. one call. If size is not a multiple of the NAND's erase size, then the block
  264. that contains offset + size will be tested in full. If used with size, this
  265. command returns 0 if all tested blocks have been found reliable, else 1.
  266. NAND locking command (for chips with active LOCKPRE pin)
  267. "nand lock"
  268. set NAND chip to lock state (all pages locked)
  269. "nand lock tight"
  270. set NAND chip to lock tight state (software can't change locking anymore)
  271. "nand lock status"
  272. displays current locking status of all pages
  273. "nand unlock [offset] [size]"
  274. unlock consecutive area (can be called multiple times for different areas)
  275. "nand unlock.allexcept [offset] [size]"
  276. unlock all except specified consecutive area
  277. I have tested the code with board containing 128MiB NAND large page chips
  278. and 32MiB small page chips.