README.Heterogeneous-SoCs 3.6 KB

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  1. DSP side awareness for Freescale heterogeneous multicore chips based on
  2. StarCore and Power Architecture
  3. ===============================================================
  4. powerpc/mpc85xx code ve APIs and function to get the number,
  5. configuration and frequencies of all PowerPC cores and devices
  6. connected to them, but it didnt have the similar code ofr HEterogeneous
  7. SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
  8. Code for DSP side awareness provides such functionality for Freescale
  9. Heterogeneous SoCs which are chasis-2 compliant like B4860 and B4420
  10. As part of this feature, following changes have been made:
  11. ==========================================================
  12. 1. Changed files:
  13. =================
  14. - arch/powerpc/cpu/mpc85xx/cpu.c
  15. Code added in this file to print the DSP cores and other device's(CPRI,
  16. MAPLE etc) frequencies
  17. - arch/powerpc/cpu/mpc85xx/speed.c
  18. Added Defines and code to extract the frequncy information for all
  19. required cores and devices from RCW and System frequency
  20. - arch/powerpc/cpu/mpc8xxx/cpu.c
  21. Added API to get the number of SC cores in running system and Their BIT
  22. MASK, similar to the code written for PowerPC
  23. - arch/powerpc/include/asm/config_mpc85xx.h
  24. Added top level CONFIG to identify presence of HETEROGENUOUS clusters
  25. in the system and CONFIGS for SC3900/DSP components
  26. - arch/powerpc/include/asm/processor.h
  27. - include/common.h
  28. Added newly added Functions Declaration
  29. - include/e500.h
  30. Global structure updated for dsp cores and other components
  31. 2. CONFIGs ADDED
  32. ================
  33. CONFIG_HETROGENOUS_CLUSTERS - Define for checking the presence of
  34. DSP/SC3900 core clusters
  35. CONFIG_SYS_FSL_NUM_CC_PLLS - Define for number of PLLs
  36. Though there are only 4 PLLs in B4, but in sequence of PLLs from PLL1 -
  37. PLL5, PLL3 is Reserved(as mentioned in RM), so this define contains the
  38. value as 5 not 4, to iterate over all PLLs while coding
  39. CONFIG_SYS_MAPLE - Define for MAPLE Baseband Accelerator
  40. CONFIG_SYS_CPRI - Define for CPRI Interface
  41. CONFIG_PPC_CLUSTER_START - Start index of ppc clusters
  42. CONFIG_DSP_CLUSTER_START - Start index of dsp clusters
  43. Following are the defines for PLL's index that provide the Clocking to
  44. CPRI, ULB and ETVE components
  45. CONFIG_SYS_CPRI_CLK - Define PLL index for CPRI clock
  46. CONFIG_SYS_ULB_CLK - Define PLL index for ULB clock
  47. CONFIG_SYS_ETVPE_CLK - Define PLL index for ETVPE clock
  48. 3. Changes in MPC85xx_SYS_INFO Global structure
  49. ===============================================
  50. DSP cores and other device's components have been added in this structure.
  51. freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies
  52. freq_cpri - To store CPRI frequency
  53. freq_maple - To store MAPLE frequency
  54. freq_maple_ulb - To store MAPLE-ULB frequency
  55. freq_maple_etvpe - To store MAPLE-eTVPE frequency
  56. 4. U-BOOT LOGS
  57. ==============
  58. 4.1 B4860QDS board
  59. Boot from NOR flash
  60. U-Boot 2014.07-00222-g70587a8-dirty (Aug 07 2014 - 13:15:47)
  61. CPU0: B4860E, Version: 2.0, (0x86880020)
  62. Core: e6500, Version: 2.0, (0x80400020) Clock Configuration:
  63. CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
  64. DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
  65. DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
  66. CCB:666.667 MHz,
  67. DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
  68. CPRI:600 MHz
  69. MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
  70. FMAN1: 666.667 MHz
  71. QMAN: 333.333 MHz
  72. CPUn - PowerPC core
  73. DSP CPUn - SC3900 core
  74. Shaveta Leekha(shaveta@freescale.com)
  75. Created August 7, 2014
  76. ===========================================