pci.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
  9. */
  10. /*
  11. * PCI routines
  12. */
  13. #include <common.h>
  14. #include <bootretry.h>
  15. #include <cli.h>
  16. #include <command.h>
  17. #include <console.h>
  18. #include <dm.h>
  19. #include <init.h>
  20. #include <asm/processor.h>
  21. #include <asm/io.h>
  22. #include <pci.h>
  23. struct pci_reg_info {
  24. const char *name;
  25. enum pci_size_t size;
  26. u8 offset;
  27. };
  28. static int pci_byte_size(enum pci_size_t size)
  29. {
  30. switch (size) {
  31. case PCI_SIZE_8:
  32. return 1;
  33. case PCI_SIZE_16:
  34. return 2;
  35. case PCI_SIZE_32:
  36. default:
  37. return 4;
  38. }
  39. }
  40. static int pci_field_width(enum pci_size_t size)
  41. {
  42. return pci_byte_size(size) * 2;
  43. }
  44. static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
  45. {
  46. for (; regs->name; regs++) {
  47. unsigned long val;
  48. dm_pci_read_config(dev, regs->offset, &val, regs->size);
  49. printf(" %s =%*s%#.*lx\n", regs->name,
  50. (int)(28 - strlen(regs->name)), "",
  51. pci_field_width(regs->size), val);
  52. }
  53. }
  54. int pci_bar_show(struct udevice *dev)
  55. {
  56. u8 header_type;
  57. int bar_cnt, bar_id, mem_type;
  58. bool is_64, is_io;
  59. u32 base_low, base_high;
  60. u32 size_low, size_high;
  61. u64 base, size;
  62. u32 reg_addr;
  63. int prefetchable;
  64. dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
  65. if (header_type == PCI_HEADER_TYPE_CARDBUS) {
  66. printf("CardBus doesn't support BARs\n");
  67. return -ENOSYS;
  68. }
  69. bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
  70. printf("ID Base Size Width Type\n");
  71. printf("----------------------------------------------------------\n");
  72. bar_id = 0;
  73. reg_addr = PCI_BASE_ADDRESS_0;
  74. while (bar_cnt) {
  75. dm_pci_read_config32(dev, reg_addr, &base_low);
  76. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  77. dm_pci_read_config32(dev, reg_addr, &size_low);
  78. dm_pci_write_config32(dev, reg_addr, base_low);
  79. reg_addr += 4;
  80. base = base_low & ~0xf;
  81. size = size_low & ~0xf;
  82. base_high = 0x0;
  83. size_high = 0xffffffff;
  84. is_64 = 0;
  85. prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
  86. is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
  87. mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  88. if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
  89. dm_pci_read_config32(dev, reg_addr, &base_high);
  90. dm_pci_write_config32(dev, reg_addr, 0xffffffff);
  91. dm_pci_read_config32(dev, reg_addr, &size_high);
  92. dm_pci_write_config32(dev, reg_addr, base_high);
  93. bar_cnt--;
  94. reg_addr += 4;
  95. is_64 = 1;
  96. }
  97. base = base | ((u64)base_high << 32);
  98. size = size | ((u64)size_high << 32);
  99. if ((!is_64 && size_low) || (is_64 && size)) {
  100. size = ~size + 1;
  101. printf(" %d %#018llx %#018llx %d %s %s\n",
  102. bar_id, (unsigned long long)base,
  103. (unsigned long long)size, is_64 ? 64 : 32,
  104. is_io ? "I/O" : "MEM",
  105. prefetchable ? "Prefetchable" : "");
  106. }
  107. bar_id++;
  108. bar_cnt--;
  109. }
  110. return 0;
  111. }
  112. static struct pci_reg_info regs_start[] = {
  113. { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
  114. { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
  115. { "command register ID", PCI_SIZE_16, PCI_COMMAND },
  116. { "status register", PCI_SIZE_16, PCI_STATUS },
  117. { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
  118. {},
  119. };
  120. static struct pci_reg_info regs_rest[] = {
  121. { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
  122. { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
  123. { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
  124. { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
  125. { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
  126. { "BIST", PCI_SIZE_8, PCI_BIST },
  127. { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
  128. {},
  129. };
  130. static struct pci_reg_info regs_normal[] = {
  131. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  132. { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
  133. { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
  134. { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
  135. { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
  136. { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
  137. { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
  138. { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
  139. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
  140. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  141. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  142. { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
  143. { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
  144. {},
  145. };
  146. static struct pci_reg_info regs_bridge[] = {
  147. { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
  148. { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
  149. { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
  150. { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
  151. { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
  152. { "IO base", PCI_SIZE_8, PCI_IO_BASE },
  153. { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
  154. { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
  155. { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
  156. { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
  157. { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
  158. { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
  159. { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
  160. { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
  161. { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
  162. { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
  163. { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
  164. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  165. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  166. { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
  167. {},
  168. };
  169. static struct pci_reg_info regs_cardbus[] = {
  170. { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
  171. { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
  172. { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
  173. { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
  174. { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
  175. { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
  176. { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
  177. { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
  178. { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
  179. { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
  180. { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
  181. { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
  182. { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
  183. { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
  184. { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
  185. { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
  186. { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
  187. { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
  188. { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
  189. { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
  190. { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
  191. { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
  192. { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
  193. { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
  194. {},
  195. };
  196. /**
  197. * pci_header_show() - Show the header of the specified PCI device.
  198. *
  199. * @dev: Bus+Device+Function number
  200. */
  201. void pci_header_show(struct udevice *dev)
  202. {
  203. unsigned long class, header_type;
  204. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  205. dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
  206. pci_show_regs(dev, regs_start);
  207. printf(" class code = 0x%.2x (%s)\n", (int)class,
  208. pci_class_str(class));
  209. pci_show_regs(dev, regs_rest);
  210. switch (header_type & 0x03) {
  211. case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  212. pci_show_regs(dev, regs_normal);
  213. break;
  214. case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  215. pci_show_regs(dev, regs_bridge);
  216. break;
  217. case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  218. pci_show_regs(dev, regs_cardbus);
  219. break;
  220. default:
  221. printf("unknown header\n");
  222. break;
  223. }
  224. }
  225. void pciinfo_header(int busnum, bool short_listing)
  226. {
  227. printf("Scanning PCI devices on bus %d\n", busnum);
  228. if (short_listing) {
  229. printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
  230. printf("_____________________________________________________________\n");
  231. }
  232. }
  233. /**
  234. * pci_header_show_brief() - Show the short-form PCI device header
  235. *
  236. * Reads and prints the header of the specified PCI device in short form.
  237. *
  238. * @dev: PCI device to show
  239. */
  240. static void pci_header_show_brief(struct udevice *dev)
  241. {
  242. ulong vendor, device;
  243. ulong class, subclass;
  244. dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
  245. dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
  246. dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
  247. dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
  248. printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
  249. vendor, device,
  250. pci_class_str(class), subclass);
  251. }
  252. static void pciinfo(struct udevice *bus, bool short_listing)
  253. {
  254. struct udevice *dev;
  255. pciinfo_header(dev_seq(bus), short_listing);
  256. for (device_find_first_child(bus, &dev);
  257. dev;
  258. device_find_next_child(&dev)) {
  259. struct pci_child_plat *pplat;
  260. pplat = dev_get_parent_plat(dev);
  261. if (short_listing) {
  262. printf("%02x.%02x.%02x ", dev_seq(bus),
  263. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  264. pci_header_show_brief(dev);
  265. } else {
  266. printf("\nFound PCI device %02x.%02x.%02x:\n",
  267. dev_seq(bus),
  268. PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
  269. pci_header_show(dev);
  270. }
  271. }
  272. }
  273. /**
  274. * get_pci_dev() - Convert the "bus.device.function" identifier into a number
  275. *
  276. * @name: Device string in the form "bus.device.function" where each is in hex
  277. * @return encoded pci_dev_t or -1 if the string was invalid
  278. */
  279. static pci_dev_t get_pci_dev(char *name)
  280. {
  281. char cnum[12];
  282. int len, i, iold, n;
  283. int bdfs[3] = {0,0,0};
  284. len = strlen(name);
  285. if (len > 8)
  286. return -1;
  287. for (i = 0, iold = 0, n = 0; i < len; i++) {
  288. if (name[i] == '.') {
  289. memcpy(cnum, &name[iold], i - iold);
  290. cnum[i - iold] = '\0';
  291. bdfs[n++] = hextoul(cnum, NULL);
  292. iold = i + 1;
  293. }
  294. }
  295. strcpy(cnum, &name[iold]);
  296. if (n == 0)
  297. n = 1;
  298. bdfs[n] = hextoul(cnum, NULL);
  299. return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
  300. }
  301. static int pci_cfg_display(struct udevice *dev, ulong addr,
  302. enum pci_size_t size, ulong length)
  303. {
  304. #define DISP_LINE_LEN 16
  305. ulong i, nbytes, linebytes;
  306. int byte_size;
  307. int rc = 0;
  308. byte_size = pci_byte_size(size);
  309. if (length == 0)
  310. length = 0x40 / byte_size; /* Standard PCI config space */
  311. /* Print the lines.
  312. * once, and all accesses are with the specified bus width.
  313. */
  314. nbytes = length * byte_size;
  315. do {
  316. printf("%08lx:", addr);
  317. linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
  318. for (i = 0; i < linebytes; i += byte_size) {
  319. unsigned long val;
  320. dm_pci_read_config(dev, addr, &val, size);
  321. printf(" %0*lx", pci_field_width(size), val);
  322. addr += byte_size;
  323. }
  324. printf("\n");
  325. nbytes -= linebytes;
  326. if (ctrlc()) {
  327. rc = 1;
  328. break;
  329. }
  330. } while (nbytes > 0);
  331. return (rc);
  332. }
  333. static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
  334. ulong value, int incrflag)
  335. {
  336. ulong i;
  337. int nbytes;
  338. ulong val;
  339. /* Print the address, followed by value. Then accept input for
  340. * the next value. A non-converted value exits.
  341. */
  342. do {
  343. printf("%08lx:", addr);
  344. dm_pci_read_config(dev, addr, &val, size);
  345. printf(" %0*lx", pci_field_width(size), val);
  346. nbytes = cli_readline(" ? ");
  347. if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
  348. /* <CR> pressed as only input, don't modify current
  349. * location and move to next. "-" pressed will go back.
  350. */
  351. if (incrflag)
  352. addr += nbytes ? -size : size;
  353. nbytes = 1;
  354. /* good enough to not time out */
  355. bootretry_reset_cmd_timeout();
  356. }
  357. #ifdef CONFIG_BOOT_RETRY_TIME
  358. else if (nbytes == -2) {
  359. break; /* timed out, exit the command */
  360. }
  361. #endif
  362. else {
  363. char *endp;
  364. i = hextoul(console_buffer, &endp);
  365. nbytes = endp - console_buffer;
  366. if (nbytes) {
  367. /* good enough to not time out
  368. */
  369. bootretry_reset_cmd_timeout();
  370. dm_pci_write_config(dev, addr, i, size);
  371. if (incrflag)
  372. addr += size;
  373. }
  374. }
  375. } while (nbytes);
  376. return 0;
  377. }
  378. static const struct pci_flag_info {
  379. uint flag;
  380. const char *name;
  381. } pci_flag_info[] = {
  382. { PCI_REGION_IO, "io" },
  383. { PCI_REGION_PREFETCH, "prefetch" },
  384. { PCI_REGION_SYS_MEMORY, "sysmem" },
  385. { PCI_REGION_RO, "readonly" },
  386. { PCI_REGION_IO, "io" },
  387. };
  388. static void pci_show_regions(struct udevice *bus)
  389. {
  390. struct pci_controller *hose = dev_get_uclass_priv(bus);
  391. const struct pci_region *reg;
  392. int i, j;
  393. if (!hose) {
  394. printf("Bus '%s' is not a PCI controller\n", bus->name);
  395. return;
  396. }
  397. printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
  398. "Flags");
  399. for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
  400. printf("%d %#018llx %#018llx %#018llx ", i,
  401. (unsigned long long)reg->bus_start,
  402. (unsigned long long)reg->phys_start,
  403. (unsigned long long)reg->size);
  404. if (!(reg->flags & PCI_REGION_TYPE))
  405. printf("mem ");
  406. for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
  407. if (reg->flags & pci_flag_info[j].flag)
  408. printf("%s ", pci_flag_info[j].name);
  409. }
  410. printf("\n");
  411. }
  412. }
  413. /* PCI Configuration Space access commands
  414. *
  415. * Syntax:
  416. * pci display[.b, .w, .l] bus.device.function} [addr] [len]
  417. * pci next[.b, .w, .l] bus.device.function [addr]
  418. * pci modify[.b, .w, .l] bus.device.function [addr]
  419. * pci write[.b, .w, .l] bus.device.function addr value
  420. */
  421. static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
  422. {
  423. ulong addr = 0, value = 0, cmd_size = 0;
  424. enum pci_size_t size = PCI_SIZE_32;
  425. struct udevice *dev, *bus;
  426. int busnum = 0;
  427. pci_dev_t bdf = 0;
  428. char cmd = 's';
  429. int ret = 0;
  430. if (argc > 1)
  431. cmd = argv[1][0];
  432. switch (cmd) {
  433. case 'd': /* display */
  434. case 'n': /* next */
  435. case 'm': /* modify */
  436. case 'w': /* write */
  437. /* Check for a size specification. */
  438. cmd_size = cmd_get_data_size(argv[1], 4);
  439. size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
  440. if (argc > 3)
  441. addr = hextoul(argv[3], NULL);
  442. if (argc > 4)
  443. value = hextoul(argv[4], NULL);
  444. case 'h': /* header */
  445. case 'b': /* bars */
  446. if (argc < 3)
  447. goto usage;
  448. if ((bdf = get_pci_dev(argv[2])) == -1)
  449. return 1;
  450. break;
  451. case 'e':
  452. pci_init();
  453. return 0;
  454. case 'r': /* no break */
  455. default: /* scan bus */
  456. value = 1; /* short listing */
  457. if (argc > 1) {
  458. if (cmd != 'r' && argv[argc-1][0] == 'l') {
  459. value = 0;
  460. argc--;
  461. }
  462. if (argc > 1)
  463. busnum = hextoul(argv[1], NULL);
  464. }
  465. ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
  466. if (ret) {
  467. printf("No such bus\n");
  468. return CMD_RET_FAILURE;
  469. }
  470. if (cmd == 'r')
  471. pci_show_regions(bus);
  472. else
  473. pciinfo(bus, value);
  474. return 0;
  475. }
  476. ret = dm_pci_bus_find_bdf(bdf, &dev);
  477. if (ret) {
  478. printf("No such device\n");
  479. return CMD_RET_FAILURE;
  480. }
  481. switch (argv[1][0]) {
  482. case 'h': /* header */
  483. pci_header_show(dev);
  484. break;
  485. case 'd': /* display */
  486. return pci_cfg_display(dev, addr, size, value);
  487. case 'n': /* next */
  488. if (argc < 4)
  489. goto usage;
  490. ret = pci_cfg_modify(dev, addr, size, value, 0);
  491. break;
  492. case 'm': /* modify */
  493. if (argc < 4)
  494. goto usage;
  495. ret = pci_cfg_modify(dev, addr, size, value, 1);
  496. break;
  497. case 'w': /* write */
  498. if (argc < 5)
  499. goto usage;
  500. ret = dm_pci_write_config(dev, addr, value, size);
  501. break;
  502. case 'b': /* bars */
  503. return pci_bar_show(dev);
  504. default:
  505. ret = CMD_RET_USAGE;
  506. break;
  507. }
  508. return ret;
  509. usage:
  510. return CMD_RET_USAGE;
  511. }
  512. /***************************************************/
  513. #ifdef CONFIG_SYS_LONGHELP
  514. static char pci_help_text[] =
  515. "[bus] [long]\n"
  516. " - short or long list of PCI devices on bus 'bus'\n"
  517. "pci enum\n"
  518. " - Enumerate PCI buses\n"
  519. "pci header b.d.f\n"
  520. " - show header of PCI device 'bus.device.function'\n"
  521. "pci bar b.d.f\n"
  522. " - show BARs base and size for device b.d.f'\n"
  523. "pci regions\n"
  524. " - show PCI regions\n"
  525. "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
  526. " - display PCI configuration space (CFG)\n"
  527. "pci next[.b, .w, .l] b.d.f address\n"
  528. " - modify, read and keep CFG address\n"
  529. "pci modify[.b, .w, .l] b.d.f address\n"
  530. " - modify, auto increment CFG address\n"
  531. "pci write[.b, .w, .l] b.d.f address value\n"
  532. " - write to CFG address";
  533. #endif
  534. U_BOOT_CMD(
  535. pci, 5, 1, do_pci,
  536. "list and access PCI Configuration Space", pci_help_text
  537. );