wandboard.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2014 O.S. Systems Software LTDA.
  5. *
  6. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <image.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/crm_regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/mx6-pins.h>
  17. #include <asm/arch/mxc_hdmi.h>
  18. #include <asm/arch/sys_proto.h>
  19. #include <asm/global_data.h>
  20. #include <asm/gpio.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <asm/mach-imx/boot_mode.h>
  24. #include <asm/mach-imx/video.h>
  25. #include <asm/mach-imx/sata.h>
  26. #include <asm/io.h>
  27. #include <env.h>
  28. #include <linux/delay.h>
  29. #include <linux/sizes.h>
  30. #include <common.h>
  31. #include <miiphy.h>
  32. #include <netdev.h>
  33. #include <phy.h>
  34. #include <i2c.h>
  35. #include <power/pmic.h>
  36. #include <power/pfuze100_pmic.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  44. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. #define ETH_PHY_RESET IMX_GPIO_NR(3, 29)
  47. #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13)
  48. #define REV_DETECTION IMX_GPIO_NR(2, 28)
  49. /* Speed defined in Kconfig is only applicable when not using DM_I2C. */
  50. #if CONFIG_IS_ENABLED(DM_I2C)
  51. #define I2C1_SPEED_NON_DM 0
  52. #define I2C2_SPEED_NON_DM 0
  53. #else
  54. #define I2C1_SPEED_NON_DM CONFIG_SYS_MXC_I2C1_SPEED
  55. #define I2C2_SPEED_NON_DM CONFIG_SYS_MXC_I2C2_SPEED
  56. #endif
  57. static bool with_pmic;
  58. int dram_init(void)
  59. {
  60. gd->ram_size = imx_ddr_size();
  61. return 0;
  62. }
  63. static iomux_v3_cfg_t const uart1_pads[] = {
  64. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  65. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  66. };
  67. static iomux_v3_cfg_t const enet_pads[] = {
  68. /* AR8031 PHY Reset */
  69. IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  70. };
  71. static iomux_v3_cfg_t const enet_ar8035_power_pads[] = {
  72. /* AR8035 POWER */
  73. IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  74. };
  75. static iomux_v3_cfg_t const rev_detection_pad[] = {
  76. IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77. };
  78. static void setup_iomux_uart(void)
  79. {
  80. SETUP_IOMUX_PADS(uart1_pads);
  81. }
  82. static void setup_iomux_enet(void)
  83. {
  84. SETUP_IOMUX_PADS(enet_pads);
  85. if (with_pmic) {
  86. SETUP_IOMUX_PADS(enet_ar8035_power_pads);
  87. /* enable AR8035 POWER */
  88. gpio_request(ETH_PHY_AR8035_POWER, "PHY_POWER");
  89. gpio_direction_output(ETH_PHY_AR8035_POWER, 0);
  90. }
  91. /* wait until 3.3V of PHY and clock become stable */
  92. mdelay(10);
  93. /* Reset AR8031 PHY */
  94. gpio_request(ETH_PHY_RESET, "PHY_RESET");
  95. gpio_direction_output(ETH_PHY_RESET, 0);
  96. mdelay(10);
  97. gpio_set_value(ETH_PHY_RESET, 1);
  98. udelay(100);
  99. }
  100. static int ar8031_phy_fixup(struct phy_device *phydev)
  101. {
  102. unsigned short val;
  103. int mask;
  104. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  105. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  106. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  107. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  108. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  109. if (with_pmic)
  110. mask = 0xffe7; /* AR8035 */
  111. else
  112. mask = 0xffe3; /* AR8031 */
  113. val &= mask;
  114. val |= 0x18;
  115. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  116. /* introduce tx clock delay */
  117. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  118. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  119. val |= 0x0100;
  120. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  121. return 0;
  122. }
  123. int board_phy_config(struct phy_device *phydev)
  124. {
  125. ar8031_phy_fixup(phydev);
  126. if (phydev->drv->config)
  127. phydev->drv->config(phydev);
  128. return 0;
  129. }
  130. #if defined(CONFIG_VIDEO_IPUV3)
  131. struct i2c_pads_info mx6q_i2c2_pad_info = {
  132. .scl = {
  133. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
  134. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  135. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
  136. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  137. .gp = IMX_GPIO_NR(4, 12)
  138. },
  139. .sda = {
  140. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
  141. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  142. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
  143. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  144. .gp = IMX_GPIO_NR(4, 13)
  145. }
  146. };
  147. struct i2c_pads_info mx6dl_i2c2_pad_info = {
  148. .scl = {
  149. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL
  150. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  151. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12
  152. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  153. .gp = IMX_GPIO_NR(4, 12)
  154. },
  155. .sda = {
  156. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA
  157. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  158. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13
  159. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  160. .gp = IMX_GPIO_NR(4, 13)
  161. }
  162. };
  163. struct i2c_pads_info mx6q_i2c3_pad_info = {
  164. .scl = {
  165. .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL
  166. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  167. .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05
  168. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  169. .gp = IMX_GPIO_NR(1, 5)
  170. },
  171. .sda = {
  172. .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA
  173. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  174. .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11
  175. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  176. .gp = IMX_GPIO_NR(7, 11)
  177. }
  178. };
  179. struct i2c_pads_info mx6dl_i2c3_pad_info = {
  180. .scl = {
  181. .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL
  182. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  183. .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05
  184. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  185. .gp = IMX_GPIO_NR(1, 5)
  186. },
  187. .sda = {
  188. .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA
  189. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  190. .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11
  191. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  192. .gp = IMX_GPIO_NR(7, 11)
  193. }
  194. };
  195. static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
  196. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),
  197. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */
  198. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */
  199. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */
  200. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */
  201. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00),
  202. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01),
  203. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02),
  204. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03),
  205. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04),
  206. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05),
  207. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06),
  208. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07),
  209. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08),
  210. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09),
  211. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10),
  212. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11),
  213. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12),
  214. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13),
  215. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14),
  216. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15),
  217. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16),
  218. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17),
  219. IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */
  220. IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */
  221. };
  222. static void do_enable_hdmi(struct display_info_t const *dev)
  223. {
  224. imx_enable_hdmi_phy();
  225. }
  226. static int detect_i2c(struct display_info_t const *dev)
  227. {
  228. #if CONFIG_IS_ENABLED(DM_I2C)
  229. struct udevice *bus, *udev;
  230. int rc;
  231. rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
  232. if (rc)
  233. return rc;
  234. rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
  235. if (rc)
  236. return 0;
  237. return 1;
  238. #else
  239. return (0 == i2c_set_bus_num(dev->bus)) &&
  240. (0 == i2c_probe(dev->addr));
  241. #endif
  242. }
  243. static void enable_fwadapt_7wvga(struct display_info_t const *dev)
  244. {
  245. SETUP_IOMUX_PADS(fwadapt_7wvga_pads);
  246. gpio_request(IMX_GPIO_NR(2, 10), "DISP0_BKLEN");
  247. gpio_request(IMX_GPIO_NR(2, 11), "DISP0_VDDEN");
  248. gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
  249. gpio_direction_output(IMX_GPIO_NR(2, 11), 1);
  250. }
  251. struct display_info_t const displays[] = {{
  252. .bus = -1,
  253. .addr = 0,
  254. .pixfmt = IPU_PIX_FMT_RGB24,
  255. .detect = detect_hdmi,
  256. .enable = do_enable_hdmi,
  257. .mode = {
  258. .name = "HDMI",
  259. .refresh = 60,
  260. .xres = 1024,
  261. .yres = 768,
  262. .pixclock = 15385,
  263. .left_margin = 220,
  264. .right_margin = 40,
  265. .upper_margin = 21,
  266. .lower_margin = 7,
  267. .hsync_len = 60,
  268. .vsync_len = 10,
  269. .sync = FB_SYNC_EXT,
  270. .vmode = FB_VMODE_NONINTERLACED
  271. } }, {
  272. .bus = 1,
  273. .addr = 0x10,
  274. .pixfmt = IPU_PIX_FMT_RGB666,
  275. .detect = detect_i2c,
  276. .enable = enable_fwadapt_7wvga,
  277. .mode = {
  278. .name = "FWBADAPT-LCD-F07A-0102",
  279. .refresh = 60,
  280. .xres = 800,
  281. .yres = 480,
  282. .pixclock = 33260,
  283. .left_margin = 128,
  284. .right_margin = 128,
  285. .upper_margin = 22,
  286. .lower_margin = 22,
  287. .hsync_len = 1,
  288. .vsync_len = 1,
  289. .sync = 0,
  290. .vmode = FB_VMODE_NONINTERLACED
  291. } } };
  292. size_t display_count = ARRAY_SIZE(displays);
  293. static void setup_display(void)
  294. {
  295. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  296. int reg;
  297. enable_ipu_clock();
  298. imx_setup_hdmi();
  299. reg = readl(&mxc_ccm->chsccdr);
  300. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  301. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  302. writel(reg, &mxc_ccm->chsccdr);
  303. /* Disable LCD backlight */
  304. SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20);
  305. gpio_request(IMX_GPIO_NR(4, 20), "LCD_BKLEN");
  306. gpio_direction_input(IMX_GPIO_NR(4, 20));
  307. }
  308. #endif /* CONFIG_VIDEO_IPUV3 */
  309. int board_early_init_f(void)
  310. {
  311. setup_iomux_uart();
  312. #ifdef CONFIG_SATA
  313. setup_sata();
  314. #endif
  315. return 0;
  316. }
  317. #define PMIC_I2C_BUS 2
  318. int power_init_board(void)
  319. {
  320. struct udevice *dev;
  321. int reg, ret;
  322. ret = pmic_get("pfuze100@8", &dev);
  323. if (ret < 0) {
  324. debug("pmic_get() ret %d\n", ret);
  325. return 0;
  326. }
  327. reg = pmic_reg_read(dev, PFUZE100_DEVICEID);
  328. if (reg < 0) {
  329. debug("pmic_reg_read() ret %d\n", reg);
  330. return 0;
  331. }
  332. printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  333. with_pmic = true;
  334. /* Set VGEN2 to 1.5V and enable */
  335. reg = pmic_reg_read(dev, PFUZE100_VGEN2VOL);
  336. reg &= ~(LDO_VOL_MASK);
  337. reg |= (LDOA_1_50V | (1 << (LDO_EN)));
  338. pmic_reg_write(dev, PFUZE100_VGEN2VOL, reg);
  339. return 0;
  340. }
  341. /*
  342. * Do not overwrite the console
  343. * Use always serial for U-Boot console
  344. */
  345. int overwrite_console(void)
  346. {
  347. return 1;
  348. }
  349. #ifdef CONFIG_CMD_BMODE
  350. static const struct boot_mode board_boot_modes[] = {
  351. /* 4 bit bus width */
  352. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  353. {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  354. {NULL, 0},
  355. };
  356. #endif
  357. static bool is_revc1(void)
  358. {
  359. SETUP_IOMUX_PADS(rev_detection_pad);
  360. gpio_request(REV_DETECTION, "REV_DETECT");
  361. gpio_direction_input(REV_DETECTION);
  362. if (gpio_get_value(REV_DETECTION))
  363. return true;
  364. else
  365. return false;
  366. }
  367. static bool is_revd1(void)
  368. {
  369. if (with_pmic)
  370. return true;
  371. else
  372. return false;
  373. }
  374. int board_late_init(void)
  375. {
  376. #ifdef CONFIG_CMD_BMODE
  377. add_board_boot_modes(board_boot_modes);
  378. #endif
  379. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  380. if (is_mx6dqp())
  381. env_set("board_rev", "MX6QP");
  382. else if (is_mx6dq())
  383. env_set("board_rev", "MX6Q");
  384. else
  385. env_set("board_rev", "MX6DL");
  386. if (is_revd1())
  387. env_set("board_name", "D1");
  388. else if (is_revc1())
  389. env_set("board_name", "C1");
  390. else
  391. env_set("board_name", "B1");
  392. #endif
  393. setup_iomux_enet();
  394. if (is_revd1())
  395. puts("Board: Wandboard rev D1\n");
  396. else if (is_revc1())
  397. puts("Board: Wandboard rev C1\n");
  398. else
  399. puts("Board: Wandboard rev B1\n");
  400. return 0;
  401. }
  402. int board_init(void)
  403. {
  404. /* address of boot parameters */
  405. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  406. #if defined(CONFIG_VIDEO_IPUV3)
  407. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  408. if (is_mx6dq() || is_mx6dqp()) {
  409. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6q_i2c2_pad_info);
  410. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6q_i2c3_pad_info);
  411. } else {
  412. setup_i2c(1, I2C1_SPEED_NON_DM, 0x7f, &mx6dl_i2c2_pad_info);
  413. setup_i2c(2, I2C2_SPEED_NON_DM, 0x7f, &mx6dl_i2c3_pad_info);
  414. }
  415. setup_display();
  416. #endif
  417. return 0;
  418. }
  419. #ifdef CONFIG_SPL_LOAD_FIT
  420. int board_fit_config_name_match(const char *name)
  421. {
  422. if (is_mx6dq()) {
  423. if (!strcmp(name, "imx6q-wandboard-revd1"))
  424. return 0;
  425. } else if (is_mx6dqp()) {
  426. if (!strcmp(name, "imx6qp-wandboard-revd1"))
  427. return 0;
  428. } else if (is_mx6dl() || is_mx6solo()) {
  429. if (!strcmp(name, "imx6dl-wandboard-revd1"))
  430. return 0;
  431. }
  432. return -EINVAL;
  433. }
  434. #endif