udoo.c 4.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <env.h>
  13. #include <malloc.h>
  14. #include <asm/arch/mx6-pins.h>
  15. #include <asm/global_data.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <asm/gpio.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/sata.h>
  21. #include <asm/arch/crm_regs.h>
  22. #include <asm/io.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <micrel.h>
  25. #include <miiphy.h>
  26. #include <netdev.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  29. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  30. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  32. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  34. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  35. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define WDT_EN IMX_GPIO_NR(5, 4)
  37. #define WDT_TRG IMX_GPIO_NR(3, 19)
  38. int dram_init(void)
  39. {
  40. gd->ram_size = imx_ddr_size();
  41. return 0;
  42. }
  43. static iomux_v3_cfg_t const uart2_pads[] = {
  44. IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  45. IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  46. };
  47. static iomux_v3_cfg_t const wdog_pads[] = {
  48. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  49. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19),
  50. };
  51. int mx6_rgmii_rework(struct phy_device *phydev)
  52. {
  53. /*
  54. * Bug: Apparently uDoo does not works with Gigabit switches...
  55. * Limiting speed to 10/100Mbps, and setting master mode, seems to
  56. * be the only way to have a successfull PHY auto negotiation.
  57. * How to fix: Understand why Linux kernel do not have this issue.
  58. */
  59. phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
  60. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  61. ksz9031_phy_extended_write(phydev, 0x02,
  62. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  63. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  64. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  65. ksz9031_phy_extended_write(phydev, 0x02,
  66. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  67. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  68. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  69. ksz9031_phy_extended_write(phydev, 0x02,
  70. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  71. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  72. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  73. ksz9031_phy_extended_write(phydev, 0x02,
  74. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  75. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  76. return 0;
  77. }
  78. static void setup_iomux_enet(void)
  79. {
  80. gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
  81. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
  82. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  83. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  84. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  85. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  86. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  87. udelay(1000);
  88. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
  89. /* Need 100ms delay to exit from reset. */
  90. udelay(1000 * 100);
  91. gpio_free(IMX_GPIO_NR(6, 24));
  92. gpio_free(IMX_GPIO_NR(6, 25));
  93. gpio_free(IMX_GPIO_NR(6, 27));
  94. gpio_free(IMX_GPIO_NR(6, 28));
  95. gpio_free(IMX_GPIO_NR(6, 29));
  96. }
  97. static void setup_iomux_uart(void)
  98. {
  99. SETUP_IOMUX_PADS(uart2_pads);
  100. }
  101. static void setup_iomux_wdog(void)
  102. {
  103. SETUP_IOMUX_PADS(wdog_pads);
  104. gpio_direction_output(WDT_TRG, 0);
  105. gpio_direction_output(WDT_EN, 1);
  106. gpio_direction_input(WDT_TRG);
  107. }
  108. int board_early_init_f(void)
  109. {
  110. setup_iomux_wdog();
  111. setup_iomux_uart();
  112. return 0;
  113. }
  114. int board_phy_config(struct phy_device *phydev)
  115. {
  116. mx6_rgmii_rework(phydev);
  117. if (phydev->drv->config)
  118. phydev->drv->config(phydev);
  119. return 0;
  120. }
  121. int board_init(void)
  122. {
  123. /* address of boot parameters */
  124. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  125. return 0;
  126. }
  127. int board_late_init(void)
  128. {
  129. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  130. if (is_cpu_type(MXC_CPU_MX6Q))
  131. env_set("board_rev", "MX6Q");
  132. else
  133. env_set("board_rev", "MX6DL");
  134. #endif
  135. setup_iomux_enet();
  136. return 0;
  137. }
  138. int checkboard(void)
  139. {
  140. if (is_cpu_type(MXC_CPU_MX6Q))
  141. puts("Board: Udoo Quad\n");
  142. else
  143. puts("Board: Udoo DualLite\n");
  144. return 0;
  145. }