tqma6_mba6.c 5.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
  7. * Author: Markus Niebel <markus.niebel@tq-group.com>
  8. */
  9. #include <init.h>
  10. #include <net.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <asm/gpio.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <common.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <linux/libfdt.h>
  24. #include <malloc.h>
  25. #include <i2c.h>
  26. #include <micrel.h>
  27. #include <miiphy.h>
  28. #include <mmc.h>
  29. #include <netdev.h>
  30. #include "tqma6_bb.h"
  31. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  34. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  38. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39. #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  40. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  41. #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  43. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  45. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46. #if defined(CONFIG_TQMA6Q)
  47. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790
  48. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac
  49. #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  50. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768
  51. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788
  52. #else
  53. #error "need to select module"
  54. #endif
  55. /* disable on die termination for RGMII */
  56. #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000
  57. /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */
  58. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000
  59. /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */
  60. #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000
  61. static void mba6_setup_iomuxc_enet(void)
  62. {
  63. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  64. /* clear gpr1[ENET_CLK_SEL] for externel clock */
  65. clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
  66. __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE,
  67. (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM);
  68. __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V,
  69. (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII);
  70. }
  71. static iomux_v3_cfg_t const mba6_uart2_pads[] = {
  72. NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL),
  73. NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL),
  74. };
  75. static void mba6_setup_iomuxc_uart(void)
  76. {
  77. imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads,
  78. ARRAY_SIZE(mba6_uart2_pads));
  79. }
  80. int board_mmc_get_env_dev(int devno)
  81. {
  82. /*
  83. * This assumes that the baseboard registered
  84. * the boot device first ...
  85. * Note: SDHC3 == idx2
  86. */
  87. return (2 == devno) ? 0 : 1;
  88. }
  89. int board_phy_config(struct phy_device *phydev)
  90. {
  91. /*
  92. * optimized pad skew values depends on CPU variant on the TQMa6x module:
  93. * CONFIG_TQMA6Q: i.MX6Q/D
  94. * CONFIG_TQMA6S: i.MX6S
  95. * CONFIG_TQMA6DL: i.MX6DL
  96. */
  97. #if defined(CONFIG_TQMA6Q)
  98. #define MBA6X_KSZ9031_CTRL_SKEW 0x0032
  99. #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
  100. #define MBA6X_KSZ9031_RX_SKEW 0x3333
  101. #define MBA6X_KSZ9031_TX_SKEW 0x2036
  102. #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL)
  103. #define MBA6X_KSZ9031_CTRL_SKEW 0x0030
  104. #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
  105. #define MBA6X_KSZ9031_RX_SKEW 0x3333
  106. #define MBA6X_KSZ9031_TX_SKEW 0x2052
  107. #else
  108. #error
  109. #endif
  110. /* min rx/tx ctrl delay */
  111. ksz9031_phy_extended_write(phydev, 2,
  112. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  113. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  114. MBA6X_KSZ9031_CTRL_SKEW);
  115. /* min rx delay */
  116. ksz9031_phy_extended_write(phydev, 2,
  117. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  118. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  119. MBA6X_KSZ9031_RX_SKEW);
  120. /* max tx delay */
  121. ksz9031_phy_extended_write(phydev, 2,
  122. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  123. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  124. MBA6X_KSZ9031_TX_SKEW);
  125. /* rx/tx clk skew */
  126. ksz9031_phy_extended_write(phydev, 2,
  127. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  128. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  129. MBA6X_KSZ9031_CLK_SKEW);
  130. phydev->drv->config(phydev);
  131. return 0;
  132. }
  133. int tqma6_bb_board_early_init_f(void)
  134. {
  135. mba6_setup_iomuxc_uart();
  136. return 0;
  137. }
  138. int tqma6_bb_board_init(void)
  139. {
  140. mba6_setup_iomuxc_enet();
  141. return 0;
  142. }
  143. int tqma6_bb_board_late_init(void)
  144. {
  145. return 0;
  146. }
  147. const char *tqma6_bb_get_boardname(void)
  148. {
  149. return "MBa6x";
  150. }
  151. /*
  152. * Device Tree Support
  153. */
  154. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  155. void tqma6_bb_ft_board_setup(void *blob, struct bd_info *bd)
  156. {
  157. /* TBD */
  158. }
  159. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */