colibri_imx7.c 9.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2018 Toradex AG
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/mx7-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/global_data.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/io.h>
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <dm/platform_data/serial_mxc.h>
  21. #include <fdt_support.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <jffs2/load_kernel.h>
  24. #include <linux/delay.h>
  25. #include <linux/sizes.h>
  26. #include <mmc.h>
  27. #include <miiphy.h>
  28. #include <mtd_node.h>
  29. #include <netdev.h>
  30. #include <power/pmic.h>
  31. #include <power/rn5t567_pmic.h>
  32. #include <usb.h>
  33. #include <usb/ehci-ci.h>
  34. #include "../common/tdx-common.h"
  35. DECLARE_GLOBAL_DATA_PTR;
  36. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  37. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  38. #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  39. #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
  40. #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  41. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  42. PAD_CTL_DSE_3P3V_49OHM)
  43. #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  44. #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  45. #define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
  46. int dram_init(void)
  47. {
  48. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
  49. return 0;
  50. }
  51. static iomux_v3_cfg_t const uart1_pads[] = {
  52. MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  53. MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  54. MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  55. MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
  56. };
  57. #ifdef CONFIG_USB_EHCI_MX7
  58. static iomux_v3_cfg_t const usb_cdet_pads[] = {
  59. MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  60. };
  61. #endif
  62. #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  63. static iomux_v3_cfg_t const gpmi_pads[] = {
  64. MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  65. MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66. MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77. MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78. MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  79. };
  80. static void setup_gpmi_nand(void)
  81. {
  82. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  83. /* NAND_USDHC_BUS_CLK is set in rom */
  84. set_clk_nand();
  85. }
  86. #endif
  87. #ifdef CONFIG_DM_VIDEO
  88. static iomux_v3_cfg_t const backlight_pads[] = {
  89. /* Backlight On */
  90. MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  91. /* Backlight PWM<A> (multiplexed pin) */
  92. MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
  93. MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  94. };
  95. #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
  96. #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
  97. static int setup_lcd(void)
  98. {
  99. imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
  100. /* Set BL_ON */
  101. gpio_request(GPIO_BL_ON, "BL_ON");
  102. gpio_direction_output(GPIO_BL_ON, 1);
  103. /* Set PWM<A> to full brightness (assuming inversed polarity) */
  104. gpio_request(GPIO_PWM_A, "PWM<A>");
  105. gpio_direction_output(GPIO_PWM_A, 0);
  106. return 0;
  107. }
  108. #endif
  109. /*
  110. * Backlight off before OS handover
  111. */
  112. void board_preboot_os(void)
  113. {
  114. #ifdef CONFIG_DM_VIDEO
  115. gpio_direction_output(GPIO_PWM_A, 1);
  116. gpio_direction_output(GPIO_BL_ON, 0);
  117. #endif
  118. }
  119. static void setup_iomux_uart(void)
  120. {
  121. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  122. }
  123. #ifdef CONFIG_FEC_MXC
  124. static int setup_fec(void)
  125. {
  126. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  127. = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  128. #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
  129. /*
  130. * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
  131. * and output it on the pin
  132. */
  133. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  134. IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
  135. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
  136. #else
  137. /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
  138. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  139. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
  140. IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
  141. #endif
  142. return set_clk_enet(ENET_50MHZ);
  143. }
  144. #endif
  145. int board_early_init_f(void)
  146. {
  147. setup_iomux_uart();
  148. return 0;
  149. }
  150. int board_init(void)
  151. {
  152. /* address of boot parameters */
  153. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  154. #ifdef CONFIG_FEC_MXC
  155. setup_fec();
  156. #endif
  157. #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
  158. setup_gpmi_nand();
  159. #endif
  160. #ifdef CONFIG_USB_EHCI_MX7
  161. imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
  162. gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
  163. #endif
  164. return 0;
  165. }
  166. #ifdef CONFIG_DM_PMIC
  167. int power_init_board(void)
  168. {
  169. struct udevice *dev;
  170. int reg, ver;
  171. int ret;
  172. ret = pmic_get("rn5t567@33", &dev);
  173. if (ret)
  174. return ret;
  175. ver = pmic_reg_read(dev, RN5T567_LSIVER);
  176. reg = pmic_reg_read(dev, RN5T567_OTPVER);
  177. printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
  178. /* set judge and press timer of N_OE to minimal values */
  179. pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
  180. /* configure sleep slot for 3.3V Ethernet */
  181. reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
  182. reg = (reg & 0xf0) | reg >> 4;
  183. pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
  184. /* disable DCDC2 discharge to avoid backfeeding through VFB2 */
  185. pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
  186. /* configure sleep slot for ARM rail */
  187. reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
  188. reg = (reg & 0xf0) | reg >> 4;
  189. pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
  190. /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
  191. pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
  192. return 0;
  193. }
  194. void reset_cpu(void)
  195. {
  196. struct udevice *dev;
  197. pmic_get("rn5t567@33", &dev);
  198. /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
  199. pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
  200. pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
  201. /*
  202. * Re-power factor detection on PMIC side is not instant. 1ms
  203. * proved to be enough time until reset takes effect.
  204. */
  205. mdelay(1);
  206. }
  207. #endif
  208. int checkboard(void)
  209. {
  210. printf("Model: Toradex Colibri iMX7%c\n",
  211. is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
  212. return 0;
  213. }
  214. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  215. int ft_board_setup(void *blob, struct bd_info *bd)
  216. {
  217. #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
  218. int up;
  219. up = arch_auxiliary_core_check_up(0);
  220. if (up) {
  221. int ret;
  222. int areas = 1;
  223. u64 start[2], size[2];
  224. /*
  225. * Reserve 1MB of memory for M4 (1MiB is also the minimum
  226. * alignment for Linux due to MMU section size restrictions).
  227. */
  228. start[0] = gd->bd->bi_dram[0].start;
  229. size[0] = SZ_256M - SZ_1M;
  230. /* If needed, create a second entry for memory beyond 256M */
  231. if (gd->bd->bi_dram[0].size > SZ_256M) {
  232. start[1] = gd->bd->bi_dram[0].start + SZ_256M;
  233. size[1] = gd->bd->bi_dram[0].size - SZ_256M;
  234. areas = 2;
  235. }
  236. ret = fdt_set_usable_memory(blob, start, size, areas);
  237. if (ret) {
  238. eprintf("Cannot set usable memory\n");
  239. return ret;
  240. }
  241. } else {
  242. int off;
  243. off = fdt_node_offset_by_compatible(blob, -1,
  244. "fsl,imx7d-rpmsg");
  245. if (off > 0)
  246. fdt_status_disabled(blob, off);
  247. }
  248. #endif
  249. #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
  250. static const struct node_info nodes[] = {
  251. { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  252. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
  253. };
  254. /* Update partition nodes using info from mtdparts env var */
  255. puts(" Updating MTD partitions...\n");
  256. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  257. #endif
  258. return ft_common_board_setup(blob, bd);
  259. }
  260. #endif
  261. #ifdef CONFIG_USB_EHCI_MX7
  262. static iomux_v3_cfg_t const usb_otg2_pads[] = {
  263. MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  264. };
  265. int board_ehci_hcd_init(int port)
  266. {
  267. switch (port) {
  268. case 0:
  269. break;
  270. case 1:
  271. if (is_cpu_type(MXC_CPU_MX7S))
  272. return -ENODEV;
  273. imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  274. ARRAY_SIZE(usb_otg2_pads));
  275. break;
  276. default:
  277. return -EINVAL;
  278. }
  279. return 0;
  280. }
  281. int board_usb_phy_mode(int port)
  282. {
  283. switch (port) {
  284. case 0:
  285. if (gpio_get_value(USB_CDET_GPIO))
  286. return USB_INIT_DEVICE;
  287. else
  288. return USB_INIT_HOST;
  289. case 1:
  290. default:
  291. return USB_INIT_HOST;
  292. }
  293. }
  294. #if defined(CONFIG_BOARD_LATE_INIT)
  295. int board_late_init(void)
  296. {
  297. #if defined(CONFIG_DM_VIDEO)
  298. setup_lcd();
  299. #endif
  300. #if defined(CONFIG_CMD_USB_SDP)
  301. if (is_boot_from_usb()) {
  302. printf("Serial Downloader recovery mode, using sdp command\n");
  303. env_set("bootdelay", "0");
  304. env_set("bootcmd", "sdp 0");
  305. }
  306. #endif
  307. return 0;
  308. }
  309. #endif /* CONFIG_BOARD_LATE_INIT */
  310. #endif