as3722_init.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2012-2016 Toradex, Inc.
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <asm/arch-tegra/tegra_i2c.h>
  9. #include <linux/delay.h>
  10. #include "as3722_init.h"
  11. /* AS3722-PMIC-specific early init code - get CPU rails up, etc */
  12. void tegra_i2c_ll_write_addr(uint addr, uint config)
  13. {
  14. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  15. writel(addr, &reg->cmd_addr0);
  16. writel(config, &reg->cnfg);
  17. }
  18. void tegra_i2c_ll_write_data(uint data, uint config)
  19. {
  20. struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  21. writel(data, &reg->cmd_data1);
  22. writel(config, &reg->cnfg);
  23. }
  24. void pmic_enable_cpu_vdd(void)
  25. {
  26. debug("%s entry\n", __func__);
  27. #ifdef AS3722_SD1VOLTAGE_DATA
  28. /* Set up VDD_CORE, for boards where OTP is incorrect*/
  29. debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__);
  30. /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */
  31. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  32. tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  33. /*
  34. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  35. * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES);
  36. */
  37. udelay(10 * 1000);
  38. #endif
  39. /*
  40. * Make sure all non-fused regulators are down.
  41. * That way we're in known state after software reboot from linux
  42. */
  43. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  44. tegra_i2c_ll_write_data(0x0003, I2C_SEND_2_BYTES);
  45. udelay(10 * 1000);
  46. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  47. tegra_i2c_ll_write_data(0x0004, I2C_SEND_2_BYTES);
  48. udelay(10 * 1000);
  49. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  50. tegra_i2c_ll_write_data(0x001b, I2C_SEND_2_BYTES);
  51. udelay(10 * 1000);
  52. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  53. tegra_i2c_ll_write_data(0x0014, I2C_SEND_2_BYTES);
  54. udelay(10 * 1000);
  55. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  56. tegra_i2c_ll_write_data(0x001a, I2C_SEND_2_BYTES);
  57. udelay(10 * 1000);
  58. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  59. tegra_i2c_ll_write_data(0x0019, I2C_SEND_2_BYTES);
  60. udelay(10 * 1000);
  61. debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__);
  62. /*
  63. * Bring up VDD_CPU via the AS3722 PMIC on the PWR I2C bus.
  64. * First set VDD to 1.0V, then enable the VDD regulator.
  65. */
  66. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  67. tegra_i2c_ll_write_data(AS3722_SD0VOLTAGE_DATA, I2C_SEND_2_BYTES);
  68. /*
  69. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  70. * tegra_i2c_ll_write_data(AS3722_SD0CONTROL_DATA, I2C_SEND_2_BYTES);
  71. */
  72. udelay(10 * 1000);
  73. debug("%s: Setting VDD_GPU to 1.0V via AS3722 reg 6/4D\n", __func__);
  74. /*
  75. * Bring up VDD_GPU via the AS3722 PMIC on the PWR I2C bus.
  76. * First set VDD to 1.0V, then enable the VDD regulator.
  77. */
  78. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  79. tegra_i2c_ll_write_data(AS3722_SD6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  80. /*
  81. * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
  82. * tegra_i2c_ll_write_data(AS3722_SD6CONTROL_DATA, I2C_SEND_2_BYTES);
  83. */
  84. udelay(10 * 1000);
  85. debug("%s: Set VPP_FUSE to 1.2V via AS3722 reg 0x12/4E\n", __func__);
  86. /*
  87. * Bring up VPP_FUSE via the AS3722 PMIC on the PWR I2C bus.
  88. * First set VDD to 1.2V, then enable the VDD regulator.
  89. */
  90. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  91. tegra_i2c_ll_write_data(AS3722_LDO2VOLTAGE_DATA, I2C_SEND_2_BYTES);
  92. /*
  93. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  94. * tegra_i2c_ll_write_data(AS3722_LDO2CONTROL_DATA, I2C_SEND_2_BYTES);
  95. */
  96. udelay(10 * 1000);
  97. debug("%s: Set VDD_SDMMC1 to 3.3V via AS3722 reg 0x11/4E\n", __func__);
  98. /*
  99. * Bring up VDD_SDMMC1 via the AS3722 PMIC on the PWR I2C bus.
  100. * First set it to value closest to 3.3V, then enable the regulator
  101. *
  102. * NOTE: We do this early because doing it later seems to hose the CPU
  103. * power rail/partition startup. Need to debug.
  104. */
  105. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  106. tegra_i2c_ll_write_data(AS3722_LDO1VOLTAGE_DATA, I2C_SEND_2_BYTES);
  107. /*
  108. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  109. * tegra_i2c_ll_write_data(AS3722_LDO1CONTROL_DATA, I2C_SEND_2_BYTES);
  110. */
  111. udelay(10 * 1000);
  112. debug("%s: Set VDD_SDMMC3 to 3.3V via AS3722 reg 0x16/4E\n", __func__);
  113. /*
  114. * Bring up VDD_SDMMC3 via the AS3722 PMIC on the PWR I2C bus.
  115. * First set it to bypass 3.3V straight thru, then enable the regulator
  116. *
  117. * NOTE: We do this early because doing it later seems to hose the CPU
  118. * power rail/partition startup. Need to debug.
  119. */
  120. tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2);
  121. tegra_i2c_ll_write_data(AS3722_LDO6VOLTAGE_DATA, I2C_SEND_2_BYTES);
  122. /*
  123. * Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
  124. * tegra_i2c_ll_write_data(AS3722_LDO6CONTROL_DATA, I2C_SEND_2_BYTES);
  125. */
  126. udelay(10 * 1000);
  127. }