apalis-imx8x.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2020 Toradex
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx8-pins.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/sci/sci.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/global_data.h>
  14. #include <asm/gpio.h>
  15. #include <asm/io.h>
  16. #include <env.h>
  17. #include <errno.h>
  18. #include <linux/libfdt.h>
  19. #include "../common/tdx-cfg-block.h"
  20. DECLARE_GLOBAL_DATA_PTR;
  21. #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  22. (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  23. (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  24. (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  25. static iomux_cfg_t uart1_pads[] = {
  26. SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  27. SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  28. };
  29. static void setup_iomux_uart(void)
  30. {
  31. imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  32. }
  33. void board_mem_get_layout(u64 *phys_sdram_1_start,
  34. u64 *phys_sdram_1_size,
  35. u64 *phys_sdram_2_start,
  36. u64 *phys_sdram_2_size)
  37. {
  38. u32 is_dualx = 0, val = 0;
  39. sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
  40. if (scierr == SC_ERR_NONE) {
  41. /* DX has two A35 cores disabled */
  42. is_dualx = (val & 0xf) != 0x0;
  43. }
  44. *phys_sdram_1_start = PHYS_SDRAM_1;
  45. if (is_dualx)
  46. /* Our DX based SKUs only have 1 GB RAM */
  47. *phys_sdram_1_size = SZ_1G;
  48. else
  49. *phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
  50. *phys_sdram_2_start = PHYS_SDRAM_2;
  51. *phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
  52. }
  53. int board_early_init_f(void)
  54. {
  55. sc_pm_clock_rate_t rate;
  56. sc_err_t err = 0;
  57. /*
  58. * This works around that having only UART3 up the baudrate is 1.2M
  59. * instead of 115.2k. Set UART0 clock root to 80 MHz
  60. */
  61. rate = 80000000;
  62. err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate);
  63. if (err != SC_ERR_NONE)
  64. return 0;
  65. /* Set UART3 clock root to 80 MHz and enable it */
  66. rate = SC_80MHZ;
  67. err = sc_pm_setup_uart(SC_R_UART_1, rate);
  68. if (err != SC_ERR_NONE)
  69. return 0;
  70. setup_iomux_uart();
  71. return 0;
  72. }
  73. #if IS_ENABLED(CONFIG_DM_GPIO)
  74. static void board_gpio_init(void)
  75. {
  76. /* TODO */
  77. }
  78. #else
  79. static inline void board_gpio_init(void) {}
  80. #endif
  81. #if IS_ENABLED(CONFIG_FEC_MXC)
  82. #include <miiphy.h>
  83. int board_phy_config(struct phy_device *phydev)
  84. {
  85. if (phydev->drv->config)
  86. phydev->drv->config(phydev);
  87. return 0;
  88. }
  89. #endif
  90. int checkboard(void)
  91. {
  92. puts("Model: Toradex Apalis iMX8X\n");
  93. build_info();
  94. print_bootinfo();
  95. return 0;
  96. }
  97. int board_init(void)
  98. {
  99. board_gpio_init();
  100. return 0;
  101. }
  102. /*
  103. * Board specific reset that is system reset.
  104. */
  105. void reset_cpu(void)
  106. {
  107. /* TODO */
  108. }
  109. #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
  110. int ft_board_setup(void *blob, struct bd_info *bd)
  111. {
  112. return ft_common_board_setup(blob, bd);
  113. }
  114. #endif
  115. int board_mmc_get_env_dev(int devno)
  116. {
  117. return devno;
  118. }
  119. int board_late_init(void)
  120. {
  121. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  122. /* TODO move to common */
  123. env_set("board_name", "Apalis iMX8X");
  124. #endif
  125. return 0;
  126. }